There are cases that the operands of an expression are all with rank less
than UINT64/INT64 and the result of the expression is explicitly cast to
UINT64/INT64 to fit the target size.
An example will be:
UINT32 a,b;
// a and b can be any unsigned int type with rank less than UINT64, like
// UINT8, UINT16, etc.
UINT64 c;
c = (UINT64) (a + b);
Some static code checkers may warn that the expression result might
overflow within the rank of "int" (integer promotions) and the result is
then cast to a bigger size.
The commit refines codes by the following rules:
1). When the expression is possible to overflow the range of unsigned int/
int:
c = (UINT64)a + b;
2). When the expression will not overflow within the rank of "int", remove
the explicit type casts:
c = a + b;
3). When the expression will be cast to pointer of possible greater size:
UINT32 a,b;
VOID *c;
c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b);
4). When one side of a comparison expression contains only operands with
rank less than UINT32:
UINT8 a;
UINT16 b;
UINTN c;
if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...}
For rule 4), if we remove the 'UINTN' type cast like:
if (a + b > c) {...}
The VS compiler will complain with warning C4018 (signed/unsigned
mismatch, level 3 warning) due to promoting 'a + b' to type 'int'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
/** @file\r
ConsoleOut Routines that speak VGA.\r
\r
/** @file\r
ConsoleOut Routines that speak VGA.\r
\r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
// Check bit 6 of Feature Byte 2.\r
// If it is set, then Int 16 Func 09 is supported\r
//\r
// Check bit 6 of Feature Byte 2.\r
// If it is set, then Int 16 Func 09 is supported\r
//\r
- if (*(UINT8 *)(UINTN) ((Regs.X.ES << 4) + Regs.X.BX + 0x06) & 0x40) {\r
+ if (*(UINT8 *) (((UINTN) Regs.X.ES << 4) + Regs.X.BX + 0x06) & 0x40) {\r
//\r
// Get Keyboard Functionality\r
//\r
//\r
// Get Keyboard Functionality\r
//\r
-Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
- (VOID *)(UINTN) ((SimpleNetworkDevice->Isr.FrameSegSel << 4) + SimpleNetworkDevice->Isr.FrameOffset),\r
+ (VOID *) (((UINTN) SimpleNetworkDevice->Isr.FrameSegSel << 4) + SimpleNetworkDevice->Isr.FrameOffset),\r
SimpleNetworkDevice->Isr.BufferLength\r
);\r
Frame = Frame + SimpleNetworkDevice->Isr.BufferLength;\r
SimpleNetworkDevice->Isr.BufferLength\r
);\r
Frame = Frame + SimpleNetworkDevice->Isr.BufferLength;\r
/** @file\r
Helper Routines that use a PXE-enabled NIC option ROM.\r
\r
/** @file\r
Helper Routines that use a PXE-enabled NIC option ROM.\r
\r
-Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
{\r
UINT32 *Address;\r
\r
{\r
UINT32 *Address;\r
\r
- Address = (UINT32 *)(UINTN) (IVT_BASE + VectorNumber * 4);\r
+ Address = (UINT32 *) ((UINTN) IVT_BASE + VectorNumber * 4);\r
CachedVectorAddress[VectorNumber] = *Address;\r
return EFI_SUCCESS;\r
}\r
CachedVectorAddress[VectorNumber] = *Address;\r
return EFI_SUCCESS;\r
}\r
{\r
UINT32 *Address;\r
\r
{\r
UINT32 *Address;\r
\r
- Address = (UINT32 *)(UINTN) (IVT_BASE + VectorNumber * 4);\r
+ Address = (UINT32 *) ((UINTN) IVT_BASE + VectorNumber * 4);\r
*Address = CachedVectorAddress[VectorNumber];\r
return EFI_SUCCESS;\r
}\r
*Address = CachedVectorAddress[VectorNumber];\r
return EFI_SUCCESS;\r
}\r
\r
RomIdTableAddress = (UNDI_ROMID_T *) (RomAddress + OPTION_ROM_PTR->PxeRomIdOffset);\r
\r
\r
RomIdTableAddress = (UNDI_ROMID_T *) (RomAddress + OPTION_ROM_PTR->PxeRomIdOffset);\r
\r
- if ((UINTN) (OPTION_ROM_PTR->PxeRomIdOffset + RomIdTableAddress->StructLength) > RomLength) {\r
+ if (((UINT32)OPTION_ROM_PTR->PxeRomIdOffset + RomIdTableAddress->StructLength) > RomLength) {\r
DEBUG ((DEBUG_ERROR, "ROM ID Offset Error\n\r"));\r
return EFI_NOT_FOUND;\r
}\r
DEBUG ((DEBUG_ERROR, "ROM ID Offset Error\n\r"));\r
return EFI_NOT_FOUND;\r
}\r
Print_Undi_Loader_Table (UndiLoaderTable);\r
\r
DEBUG ((DEBUG_NET, "Display the PXENV+ and !PXE tables exported by NIC\n\r"));\r
Print_Undi_Loader_Table (UndiLoaderTable);\r
\r
DEBUG ((DEBUG_NET, "Display the PXENV+ and !PXE tables exported by NIC\n\r"));\r
- Print_PXENV_Table ((VOID *)(UINTN)((UndiLoaderTable->PXENVptr.Segment << 4) | UndiLoaderTable->PXENVptr.Offset));\r
- Print_PXE_Table ((VOID *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) + UndiLoaderTable->PXEptr.Offset));\r
+ Print_PXENV_Table ((VOID *)(((UINTN)UndiLoaderTable->PXENVptr.Segment << 4) | UndiLoaderTable->PXENVptr.Offset));\r
+ Print_PXE_Table ((VOID *)(((UINTN)UndiLoaderTable->PXEptr.Segment << 4) + UndiLoaderTable->PXEptr.Offset));\r
- Pxe = (PXE_T *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) + UndiLoaderTable->PXEptr.Offset);\r
+ Pxe = (PXE_T *)(((UINTN)UndiLoaderTable->PXEptr.Segment << 4) + UndiLoaderTable->PXEptr.Offset);\r
SimpleNetworkDevice->Nii.Id = (UINT64)(UINTN) Pxe;\r
\r
gBS->FreePool (Buffer);\r
SimpleNetworkDevice->Nii.Id = (UINT64)(UINTN) Pxe;\r
\r
gBS->FreePool (Buffer);\r
/** @file\r
ConsoleOut Routines that speak VGA.\r
\r
/** @file\r
ConsoleOut Routines that speak VGA.\r
\r
-Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
//\r
// Make sure the FrameBufferSize does not exceed the max available frame buffer size reported by VEB.\r
//\r
//\r
// Make sure the FrameBufferSize does not exceed the max available frame buffer size reported by VEB.\r
//\r
- ASSERT (CurrentModeData->FrameBufferSize <= (UINTN)(BiosVideoPrivate->VbeInformationBlock->TotalMemory * 64 * 1024));\r
+ ASSERT (CurrentModeData->FrameBufferSize <= ((UINT32)BiosVideoPrivate->VbeInformationBlock->TotalMemory * 64 * 1024));\r
\r
BiosVideoPrivate->ModeData = ModeBuffer;\r
}\r
\r
BiosVideoPrivate->ModeData = ModeBuffer;\r
}\r
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
);\r
\r
if (Regs.X.AX == 0) {\r
);\r
\r
if (Regs.X.AX == 0) {\r
- *LegacyMemoryAddress = (VOID *) (UINTN) ((Regs.X.DS << 4) + Regs.X.BX);\r
+ *LegacyMemoryAddress = (VOID *) (((UINTN) Regs.X.DS << 4) + Regs.X.BX);\r
Status = EFI_SUCCESS;\r
} else {\r
Status = EFI_OUT_OF_RESOURCES;\r
Status = EFI_SUCCESS;\r
} else {\r
Status = EFI_OUT_OF_RESOURCES;\r
}\r
\r
if ((mStructureTableAddress != 0) && \r
}\r
\r
if ((mStructureTableAddress != 0) && \r
- (mStructureTablePages < (UINTN) EFI_SIZE_TO_PAGES (EntryPointStructure->TableLength))) {\r
+ (mStructureTablePages < EFI_SIZE_TO_PAGES ((UINT32)EntryPointStructure->TableLength))) {\r
//\r
// If original buffer is not enough for the new SMBIOS table, free original buffer and re-allocate\r
//\r
//\r
// If original buffer is not enough for the new SMBIOS table, free original buffer and re-allocate\r
//\r
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
//\r
// Print DescString\r
//\r
//\r
// Print DescString\r
//\r
- String = (CHAR8 *)(UINTN)((BbsTable[Index].DescStringSegment << 4) + BbsTable[Index].DescStringOffset);\r
+ String = (CHAR8 *)(((UINTN)BbsTable[Index].DescStringSegment << 4) + BbsTable[Index].DescStringOffset);\r
if (String != NULL) {\r
DEBUG ((EFI_D_INFO," ("));\r
for (SubIndex = 0; String[SubIndex] != 0; SubIndex++) {\r
if (String != NULL) {\r
DEBUG ((EFI_D_INFO," ("));\r
for (SubIndex = 0; String[SubIndex] != 0; SubIndex++) {\r
//\r
// If current BBS entry has its description then use it.\r
//\r
//\r
// If current BBS entry has its description then use it.\r
//\r
- StringDesc = (UINT8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) + CurBBSEntry->DescStringOffset);\r
+ StringDesc = (UINT8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4) + CurBBSEntry->DescStringOffset);\r
if (NULL != StringDesc) {\r
//\r
// Only get fisrt 32 characters, this is suggested by BBS spec\r
if (NULL != StringDesc) {\r
//\r
// Only get fisrt 32 characters, this is suggested by BBS spec\r
)\r
{\r
if ((Char >= L'0') && (Char <= L'9')) {\r
)\r
{\r
if ((Char >= L'0') && (Char <= L'9')) {\r
- return (UINTN) (Char - L'0');\r
+ return (Char - L'0');\r
}\r
\r
if ((Char >= L'A') && (Char <= L'F')) {\r
}\r
\r
if ((Char >= L'A') && (Char <= L'F')) {\r
- return (UINTN) (Char - L'A' + 0xA);\r
+ return (Char - L'A' + 0xA);\r
//\r
// If current BBS entry has its description then use it.\r
//\r
//\r
// If current BBS entry has its description then use it.\r
//\r
- StringDesc = (CHAR8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) + CurBBSEntry->DescStringOffset);\r
+ StringDesc = (CHAR8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4) + CurBBSEntry->DescStringOffset);\r
if (NULL != StringDesc) {\r
//\r
// Only get fisrt 32 characters, this is suggested by BBS spec\r
if (NULL != StringDesc) {\r
//\r
// Only get fisrt 32 characters, this is suggested by BBS spec\r
\r
if (Base10Exponent >= 6) {\r
FreqMhz = ProcessorFrequency;\r
\r
if (Base10Exponent >= 6) {\r
FreqMhz = ProcessorFrequency;\r
- for (Index = 0; Index < (UINTN) (Base10Exponent - 6); Index++) {\r
+ for (Index = 0; Index < ((UINT32)Base10Exponent - 6); Index++) {\r
FreqMhz *= 10;\r
}\r
} else {\r
FreqMhz *= 10;\r
}\r
} else {\r
/** @file\r
Uses the services of the I/O Library to produce the CPU I/O Protocol\r
\r
/** @file\r
Uses the services of the I/O Library to produce the CPU I/O Protocol\r
\r
-Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials \r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials \r
//\r
// Check to see if Address is aligned\r
//\r
//\r
// Check to see if Address is aligned\r
//\r
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
+ if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
projects / mirror_edk2.git / commitdiff