AcpiS3Save could try to check PcdIdentifyMappingPageTablePtr is NULL, if it is not...

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Elvin Li <elvin.li@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15910 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3Save.c b/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3Save.c
index 4ef272c2b3efd88ebd47415167d5037a111a62fa..6de1871f67ffa3b0a7ab92035a51da9edbe1ef31 100644 (file)
--- a/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3Save.c
+++ b/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3Save.c
@@ -328,68 +328,74 @@ S3CreateIdentityMappingPageTables (
     VOID                                          *Hob;\r
     BOOLEAN                                       Page1GSupport;\r
 \r
-    Page1GSupport = FALSE;\r
-    if (PcdGetBool(PcdUse1GPageTable)) {\r
-      AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
-      if (RegEax >= 0x80000001) {\r
-        AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
-        if ((RegEdx & BIT26) != 0) {\r
-          Page1GSupport = TRUE;\r
+    S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdIdentifyMappingPageTablePtr);\r
+    if (S3NvsPageTableAddress != 0x0) {\r
+      return S3NvsPageTableAddress;\r
+    } else {\r
+      Page1GSupport = FALSE;\r
+      if (PcdGetBool(PcdUse1GPageTable)) {\r
+        AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+        if (RegEax >= 0x80000001) {\r
+          AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
+          if ((RegEdx & BIT26) != 0) {\r
+            Page1GSupport = TRUE;\r
+          }\r
         }\r
       }\r
-    }\r
-\r
-    //\r
-    // Get physical address bits supported.\r
-    //\r
-    Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
-    if (Hob != NULL) {\r
-      PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
-    } else {\r
-      AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
-      if (RegEax >= 0x80000008) {\r
-        AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
-        PhysicalAddressBits = (UINT8) RegEax;\r
+      \r
+      //\r
+      // Get physical address bits supported.\r
+      //\r
+      Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
+      if (Hob != NULL) {\r
+        PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
       } else {\r
-        PhysicalAddressBits = 36;\r
+        AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
+        if (RegEax >= 0x80000008) {\r
+          AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
+          PhysicalAddressBits = (UINT8) RegEax;\r
+        } else {\r
+          PhysicalAddressBits = 36;\r
+        }\r
       }\r
+      \r
+      //\r
+      // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
+      //\r
+      ASSERT (PhysicalAddressBits <= 52);\r
+      if (PhysicalAddressBits > 48) {\r
+        PhysicalAddressBits = 48;\r
+      }\r
+      \r
+      //\r
+      // Calculate the table entries needed.\r
+      //\r
+      if (PhysicalAddressBits <= 39 ) {\r
+        NumberOfPml4EntriesNeeded = 1;\r
+        NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
+      } else {\r
+        NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
+        NumberOfPdpEntriesNeeded = 512;\r
+      }\r
+      \r
+      //\r
+      // We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.\r
+      //\r
+      if (!Page1GSupport) {\r
+        TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);\r
+      } else {\r
+        TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);\r
+      }\r
+      DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));\r
+      \r
+      //\r
+      // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
+      //\r
+      S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
+      ASSERT (S3NvsPageTableAddress != 0);\r
+      PcdSet64 (PcdIdentifyMappingPageTablePtr, S3NvsPageTableAddress); \r
+      return S3NvsPageTableAddress;\r
     }\r
-    \r
-    //\r
-    // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
-    //\r
-    ASSERT (PhysicalAddressBits <= 52);\r
-    if (PhysicalAddressBits > 48) {\r
-      PhysicalAddressBits = 48;\r
-    }\r
-\r
-    //\r
-    // Calculate the table entries needed.\r
-    //\r
-    if (PhysicalAddressBits <= 39 ) {\r
-      NumberOfPml4EntriesNeeded = 1;\r
-      NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
-    } else {\r
-      NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
-      NumberOfPdpEntriesNeeded = 512;\r
-    }\r
-\r
-    //\r
-    // We need calculate whole page size then allocate once, because S3 restore page table does not know each page in Nvs.\r
-    //\r
-    if (!Page1GSupport) {\r
-      TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded + NumberOfPml4EntriesNeeded * NumberOfPdpEntriesNeeded);\r
-    } else {\r
-      TotalPageTableSize = (UINTN)(1 + NumberOfPml4EntriesNeeded);\r
-    }\r
-    DEBUG ((EFI_D_ERROR, "TotalPageTableSize - %x pages\n", TotalPageTableSize));\r
-\r
-    //\r
-    // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
-    //\r
-    S3NvsPageTableAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateMemoryBelow4G (EfiReservedMemoryType, EFI_PAGES_TO_SIZE(TotalPageTableSize));\r
-    ASSERT (S3NvsPageTableAddress != 0);\r
-    return S3NvsPageTableAddress;\r
   } else {\r
     //\r
     // If DXE is running 32-bit mode, no need to establish page table.\r

diff --git a/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf b/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
index dc6da58f9f28921fd1c758d12c35e42d0cc96eb7..9618dc2bae9237865d0b218f55924664511522a7 100644 (file)
--- a/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
+++ b/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
@@ -75,6 +75,9 @@
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize    ## CONSUMES\r
   gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3BootScriptStackSize       ## CONSUMES\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable\r
+  ## SOMETIMES_CONSUMES\r
+  ## SOMETIMES_PRODUCES\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdIdentifyMappingPageTablePtr\r
 \r
 [Depex]\r
   #\r