OvmfPkg/AcpiTables: Update GPE0 block address range for QEMU

QEMU hard codes the GPE0 registers at 0xafe0.

Previously the code assumed that the GPE0 block
would move when the PM Base Address of the PIIX4
PCI device was programmed. It appears QEMU does not
emulate this behaviour of the PIIX4 PCI device.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/OvmfPkg/AcpiTables/Dsdt.asl b/OvmfPkg/AcpiTables/Dsdt.asl
index ac0fec49e8ad373411b6751e889f2566123f6391..a0c762291e28432822c20eee731b63ae062f1ca4 100644 (file)
--- a/OvmfPkg/AcpiTables/Dsdt.asl
+++ b/OvmfPkg/AcpiTables/Dsdt.asl
@@ -368,6 +368,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF    ", 3) {
             IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
             IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
             IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r
+            IO (Decode16, 0xafe0, 0xafe0, 0x00, 0x04)     // QEMU GPE0 BLK\r
             Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000)  // IO APIC\r
             Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)\r
           })\r

diff --git a/OvmfPkg/AcpiTables/Platform.h b/OvmfPkg/AcpiTables/Platform.h
index 4e56947270bd8f3feffbd09d43d7697eab7084f4..c9aa5470672820d074ccc7e6b9393141cc9b4c3d 100644 (file)
--- a/OvmfPkg/AcpiTables/Platform.h
+++ b/OvmfPkg/AcpiTables/Platform.h
@@ -39,7 +39,7 @@
 #define PM1b_CNT_BLK    0x00000000\r
 #define PM2_CNT_BLK     0x00000022\r
 #define PM_TMR_BLK      0x00000408\r
-#define GPE0_BLK        0x0000040C\r
+#define GPE0_BLK        0x0000afe0\r
 #define GPE1_BLK        0x00000000\r
 #define PM1_EVT_LEN     0x04\r
 #define PM1_CNT_LEN     0x02\r