MdeModulePkg/XhciDxe: Check return value of XHC_PAGESIZE register

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3954

Report error if reserved bits are not 0 for PageSize

Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index b79499e22565e90389e027e4ba281b4f8bdb3f20..381d7a9536b9be1abfc4bad08c8ab286f4f77e90 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -1,7 +1,7 @@
 /** @file\r
   The XHCI controller driver.\r
 \r
-Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2022, Intel Corporation. All rights reserved.<BR>\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -1813,7 +1813,13 @@ XhcCreateUsbHc (
   // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,\r
   // if bit 0 is Set, the xHC supports 4k byte page sizes.\r
   //\r
-  PageSize      = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;\r
+  PageSize = XhcReadOpReg (Xhc, XHC_PAGESIZE_OFFSET);\r
+  if ((PageSize & (~XHC_PAGESIZE_MASK)) != 0) {\r
+    DEBUG ((DEBUG_ERROR, "XhcCreateUsb3Hc: Reserved bits are not 0 for PageSize\n"));\r
+    goto ON_ERROR;\r
+  }\r
+\r
+  PageSize     &= XHC_PAGESIZE_MASK;\r
   Xhc->PageSize = 1 << (HighBitSet32 (PageSize) + 12);\r
 \r
   ExtCapReg              = (UINT16)(Xhc->HcCParams.Data.ExtCapReg);\r