MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]

This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30].

Signed-off-by: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
index 6f77e174c115bd08bb9508f286b8c3e55a18dcee..5ec85ba561ac9f489e6c61183ce4464f9df4a221 100644 (file)
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1587,9 +1587,9 @@ typedef union {
     ///\r
     UINT32  EnumeratesSupportForCapability:1;\r
     ///\r
-    /// [Bit 30] Reserved.\r
+    /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.\r
     ///\r
-    UINT32  Reserved3:1;\r
+    UINT32  EnumeratesSupportForCoreCapabilitiesMsr:1;\r
     ///\r
     /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).\r
     /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow\r