/** @file\r
Internal library implementation for PCI Bus module.\r
\r
-Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
UINT8 StartBusNumber;\r
LIST_ENTRY RootBridgeList;\r
LIST_ENTRY *Link;\r
+ EFI_STATUS RootBridgeEnumerationStatus;\r
\r
if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
InitializeHotPlugSupport ();\r
}\r
\r
DEBUG ((DEBUG_INFO, "PCI Bus First Scanning\n"));\r
- RootBridgeHandle = NULL;\r
+ RootBridgeHandle = NULL;\r
+ RootBridgeEnumerationStatus = EFI_SUCCESS;\r
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {\r
//\r
// if a root bridge instance is found, create root bridge device for it\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ RootBridgeEnumerationStatus = Status;\r
}\r
}\r
\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
\r
+ if (EFI_ERROR (RootBridgeEnumerationStatus)) {\r
+ return RootBridgeEnumerationStatus;\r
+ }\r
+\r
if ((gPciHotPlugInit != NULL) && FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) {\r
//\r
// Reset all assigned PCI bus number in all PPB\r
\r
DestroyRootBridge (RootBridgeDev);\r
if (EFI_ERROR (Status)) {\r
- return Status;\r
+ RootBridgeEnumerationStatus = Status;\r
}\r
}\r
\r
// Notify the bus allocation phase is to end for the 2nd time\r
//\r
NotifyPhase (PciResAlloc, EfiPciHostBridgeEndBusAllocation);\r
+\r
+ if (EFI_ERROR (RootBridgeEnumerationStatus)) {\r
+ return RootBridgeEnumerationStatus;\r
+ }\r
}\r
\r
//\r