BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459

This patch adds support for R_RISCV_PCREL_LO12_S relocation type.
The logic is same as existing R_RISCV_PCREL_LO12_I relocation
except the difference between load vs store instruction formats.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Abner Chang <abner.chang@hpe.com>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 3d7e20aaff30ba41447643cda46f6bf59acf5ebf..0bb3ead228c9066ec2af015e5b6f391c72c155bf 100644 (file)
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -557,6 +557,60 @@ WriteSectionRiscV64 (
     Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));\r
     break;\r
 \r
+  case R_RISCV_PCREL_LO12_S:\r
+    if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {\r
+      int i;\r
+      Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));\r
+\r
+      Value = ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5);\r
+      Value = (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5)));\r
+\r
+      if(Value & (RISCV_IMM_REACH/2)) {\r
+        Value |= ~(RISCV_IMM_REACH-1);\r
+      }\r
+      Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];\r
+\r
+      if(-2048 > (INT32)Value) {\r
+        i = (((INT32)Value * -1) / 4096);\r
+        Value2 -= i;\r
+        Value += 4096 * i;\r
+        if(-2048 > (INT32)Value) {\r
+          Value2 -= 1;\r
+          Value += 4096;\r
+        }\r
+      }\r
+      else if( 2047 < (INT32)Value) {\r
+        i = (Value / 4096);\r
+        Value2 += i;\r
+        Value -= 4096 * i;\r
+        if(2047 < (INT32)Value) {\r
+          Value2 += 1;\r
+          Value -= 4096;\r
+        }\r
+      }\r
+\r
+      // Update the IMM of SD instruction\r
+      //\r
+      // |31      25|24  20|19  15|14   12 |11      7|6     0|\r
+      // |-------------------------------------------|-------|\r
+      // |imm[11:5] | rs2  | rs1  | funct3 |imm[4:0] | opcode|\r
+      //  ---------------------------------------------------\r
+\r
+      // First Zero out current IMM\r
+      *(UINT32 *)Targ &= ~0xfe000f80;\r
+\r
+      // Update with new IMM\r
+      *(UINT32 *)Targ |= (RV_X(Value, 5, 7) << 25);\r
+      *(UINT32 *)Targ |= (RV_X(Value, 0, 5) << 7);\r
+\r
+      // Update previous instruction\r
+      *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));\r
+    }\r
+    mRiscVPass1Sym = NULL;\r
+    mRiscVPass1Targ = NULL;\r
+    mRiscVPass1SymSecIndex = 0;\r
+    break;\r
+\r
   case R_RISCV_PCREL_LO12_I:\r
     if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {\r
       int i;\r
@@ -1587,6 +1641,7 @@ WriteRelocations64 (
             case R_RISCV_PCREL_HI20:\r
             case R_RISCV_GOT_HI20:\r
             case R_RISCV_PCREL_LO12_I:\r
+            case R_RISCV_PCREL_LO12_S:\r
               break;\r
 \r
             default:\r