--- /dev/null
+/** @file\r
+ MSR Definitions for Intel processors based on the Haswell-E microarchitecture.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.\r
+\r
+**/\r
+\r
+#ifndef __HASWELL_E_MSR_H__\r
+#define __HASWELL_E_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ UINT32 Reserved3:9;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package. MC Bank Error Configuration (R/W).\r
+\r
+ @param ECX MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_ERROR_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
+ /// to log additional info in bits 36:32.\r
+ ///\r
+ UINT32 MemErrorLogEnable:1;\r
+ UINT32 Reserved2:30;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
+ /// limit of 1 core active.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
+ /// limit of 2 core active.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
+ /// limit of 3 core active.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
+ /// limit of 4 core active.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
+ /// limit of 5 core active.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
+ /// limit of 6 core active.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
+ /// limit of 7 core active.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
+ /// limit of 8 core active.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
+ /// limit of 9 core active.\r
+ ///\r
+ UINT32 Maximum9C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
+ /// limit of 10 core active.\r
+ ///\r
+ UINT32 Maximum10C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
+ /// limit of 11 core active.\r
+ ///\r
+ UINT32 Maximum11C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
+ /// limit of 12 core active.\r
+ ///\r
+ UINT32 Maximum12C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
+ /// limit of 13 core active.\r
+ ///\r
+ UINT32 Maximum13C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
+ /// limit of 14 core active.\r
+ ///\r
+ UINT32 Maximum14C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
+ /// limit of 15 core active.\r
+ ///\r
+ UINT32 Maximum15C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
+ /// limit of 16 core active.\r
+ ///\r
+ UINT32 Maximum16C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
+ /// limit of 17 core active.\r
+ ///\r
+ UINT32 Maximum17C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
+ /// limit of 18 core active.\r
+ ///\r
+ UINT32 Maximum18C:8;\r
+ UINT32 Reserved1:16;\r
+ UINT32 Reserved2:31;\r
+ ///\r
+ /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+ /// the processor uses override configuration specified in\r
+ /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and\r
+ /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
+ /// configuration (Default).\r
+ ///\r
+ UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ * Bank MC5 reports MC error from the Intel QPI 0 module.\r
+ * Bank MC6 reports MC error from the integrated I/O module.\r
+ * Bank MC7 reports MC error from the home agent HA 0.\r
+ * Bank MC8 reports MC error from the home agent HA 1.\r
+ * Banks MC9 through MC16 report MC error from each channel of the integrated\r
+ memory controllers.\r
+ * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
+ * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
+ * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
+ * Bank MC20 reports MC error from the Intel QPI 1 module.\r
+ * Bank MC21 reports MC error from the Intel QPI 2 module.\r
+\r
+ @param ECX MSR_HASWELL_E_MCi_CTL\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_MC5_CTL 0x00000414\r
+#define MSR_HASWELL_E_MC6_CTL 0x00000418\r
+#define MSR_HASWELL_E_MC7_CTL 0x0000041C\r
+#define MSR_HASWELL_E_MC8_CTL 0x00000420\r
+#define MSR_HASWELL_E_MC9_CTL 0x00000424\r
+#define MSR_HASWELL_E_MC10_CTL 0x00000428\r
+#define MSR_HASWELL_E_MC11_CTL 0x0000042C\r
+#define MSR_HASWELL_E_MC12_CTL 0x00000430\r
+#define MSR_HASWELL_E_MC13_CTL 0x00000434\r
+#define MSR_HASWELL_E_MC14_CTL 0x00000438\r
+#define MSR_HASWELL_E_MC15_CTL 0x0000043C\r
+#define MSR_HASWELL_E_MC16_CTL 0x00000440\r
+#define MSR_HASWELL_E_MC17_CTL 0x00000444\r
+#define MSR_HASWELL_E_MC18_CTL 0x00000448\r
+#define MSR_HASWELL_E_MC19_CTL 0x0000044C\r
+#define MSR_HASWELL_E_MC20_CTL 0x00000450\r
+#define MSR_HASWELL_E_MC21_CTL 0x00000454\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_HASWELL_E_MCi_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_MC5_STATUS 0x00000415\r
+#define MSR_HASWELL_E_MC6_STATUS 0x00000419\r
+#define MSR_HASWELL_E_MC7_STATUS 0x0000041D\r
+#define MSR_HASWELL_E_MC8_STATUS 0x00000421\r
+#define MSR_HASWELL_E_MC9_STATUS 0x00000425\r
+#define MSR_HASWELL_E_MC10_STATUS 0x00000429\r
+#define MSR_HASWELL_E_MC11_STATUS 0x0000042D\r
+#define MSR_HASWELL_E_MC12_STATUS 0x00000431\r
+#define MSR_HASWELL_E_MC13_STATUS 0x00000435\r
+#define MSR_HASWELL_E_MC14_STATUS 0x00000439\r
+#define MSR_HASWELL_E_MC15_STATUS 0x0000043D\r
+#define MSR_HASWELL_E_MC16_STATUS 0x00000441\r
+#define MSR_HASWELL_E_MC17_STATUS 0x00000445\r
+#define MSR_HASWELL_E_MC18_STATUS 0x00000449\r
+#define MSR_HASWELL_E_MC19_STATUS 0x0000044D\r
+#define MSR_HASWELL_E_MC20_STATUS 0x00000451\r
+#define MSR_HASWELL_E_MC21_STATUS 0x00000455\r
+/// @}\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_HASWELL_E_MCi_ADDR\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_MC5_ADDR 0x00000416\r
+#define MSR_HASWELL_E_MC6_ADDR 0x0000041A\r
+#define MSR_HASWELL_E_MC7_ADDR 0x0000041E\r
+#define MSR_HASWELL_E_MC8_ADDR 0x00000422\r
+#define MSR_HASWELL_E_MC9_ADDR 0x00000426\r
+#define MSR_HASWELL_E_MC10_ADDR 0x0000042A\r
+#define MSR_HASWELL_E_MC11_ADDR 0x0000042E\r
+#define MSR_HASWELL_E_MC12_ADDR 0x00000432\r
+#define MSR_HASWELL_E_MC13_ADDR 0x00000436\r
+#define MSR_HASWELL_E_MC14_ADDR 0x0000043A\r
+#define MSR_HASWELL_E_MC15_ADDR 0x0000043E\r
+#define MSR_HASWELL_E_MC16_ADDR 0x00000442\r
+#define MSR_HASWELL_E_MC17_ADDR 0x00000446\r
+#define MSR_HASWELL_E_MC18_ADDR 0x0000044A\r
+#define MSR_HASWELL_E_MC19_ADDR 0x0000044E\r
+#define MSR_HASWELL_E_MC20_ADDR 0x00000452\r
+#define MSR_HASWELL_E_MC21_ADDR 0x00000456\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_HASWELL_E_MCi_MISC\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_MC5_MISC 0x00000417\r
+#define MSR_HASWELL_E_MC6_MISC 0x0000041B\r
+#define MSR_HASWELL_E_MC7_MISC 0x0000041F\r
+#define MSR_HASWELL_E_MC8_MISC 0x00000423\r
+#define MSR_HASWELL_E_MC9_MISC 0x00000427\r
+#define MSR_HASWELL_E_MC10_MISC 0x0000042B\r
+#define MSR_HASWELL_E_MC11_MISC 0x0000042F\r
+#define MSR_HASWELL_E_MC12_MISC 0x00000433\r
+#define MSR_HASWELL_E_MC13_MISC 0x00000437\r
+#define MSR_HASWELL_E_MC14_MISC 0x0000043B\r
+#define MSR_HASWELL_E_MC15_MISC 0x0000043F\r
+#define MSR_HASWELL_E_MC16_MISC 0x00000443\r
+#define MSR_HASWELL_E_MC17_MISC 0x00000447\r
+#define MSR_HASWELL_E_MC18_MISC 0x0000044B\r
+#define MSR_HASWELL_E_MC19_MISC 0x0000044F\r
+#define MSR_HASWELL_E_MC20_MISC 0x00000453\r
+#define MSR_HASWELL_E_MC21_MISC 0x00000457\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to PBM limit.\r
+ ///\r
+ UINT32 PowerBudgetManagementStatus:1;\r
+ ///\r
+ /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to PCS\r
+ /// limit.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesStatus:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Multi-Core Turbo limits.\r
+ ///\r
+ UINT32 MultiCoreTurboStatus:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
+ /// below max non-turbo P1.\r
+ ///\r
+ UINT32 FrequencyP1Status:1;\r
+ ///\r
+ /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
+ /// set, frequency is reduced below max n-core turbo frequency.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
+ /// reduced below the operating system request.\r
+ ///\r
+ UINT32 FrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ ///\r
+ /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PowerBudgetManagementLog:1;\r
+ ///\r
+ /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
+ /// the PCS Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the AUBFC Status bit has asserted since the log bit was\r
+ /// last cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
+ /// Turbo Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MultiCoreTurboLog:1;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
+ /// Frequency P1 Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyP1Log:1;\r
+ ///\r
+ /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
+ /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingLog:1;\r
+ ///\r
+ /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
+ /// Frequency Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyLimitingLog:1;\r
+ UINT32 Reserved9:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
+ ECX=0):EBX.PQM[bit 12] = 1.\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
+ /// occupancy monitoring all other encoding reserved..\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W)..\r
+\r
+ @param ECX MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global control.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global status.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
+\r
+\r
+/**\r
+ Package. Uncore perfmon per-socket global configuration.\r
+\r
+ @param ECX MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter control.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
+\r
+\r
+/**\r
+ Package. Uncore U-box UCLK fixed counter.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon event select for U-box counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon U-box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
+\r
+\r
+/**\r
+ Package. Uncore U-box perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon for PCU-box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon event select for PCU counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
+\r
+\r
+/**\r
+ Package. Uncore PCU perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 0 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 1 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 2 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon box-wide filter.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
+\r
+\r
+/**\r
+ Package. Uncore SBo 3 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide filter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 0 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 1 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 2 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 3 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 4 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 5 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 6 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 7 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 8 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 9 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 10 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 11 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 12 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 13 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 14 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon local box wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide filter0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 15 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide filter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 16 perfmon counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon for box-wide control.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide filter 0.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide filter1.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon box wide status.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
+\r
+\r
+/**\r
+ Package. Uncore C-box 17 perfmon counter n.\r
+\r
+ @param ECX MSR_HASWELL_E_C17_PMON_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);\r
+ AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
+#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
+#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
+#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
+/// @}\r
+\r
+#endif\r
projects / mirror_edk2.git / commitdiff