DEBUG ((\r
DebugPrintErrorLevel,\r
"Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
- ProcessorNumber,\r
- FeatureIndex,\r
+ (UINT32) ProcessorNumber,\r
+ (UINT32) FeatureIndex,\r
RegisterTableEntry->Index,\r
RegisterTableEntry->ValidBitStart,\r
RegisterTableEntry->ValidBitLength,\r
DEBUG ((\r
DebugPrintErrorLevel,\r
"Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
- ProcessorNumber,\r
- FeatureIndex,\r
+ (UINT32) ProcessorNumber,\r
+ (UINT32) FeatureIndex,\r
RegisterTableEntry->Index,\r
RegisterTableEntry->ValidBitStart,\r
RegisterTableEntry->ValidBitLength,\r
case MemoryMapped:\r
DEBUG ((\r
DebugPrintErrorLevel,\r
- "Processor: %04d: Index %04d, MMIO : %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
- ProcessorNumber,\r
- FeatureIndex,\r
+ "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+ (UINT32) ProcessorNumber,\r
+ (UINT32) FeatureIndex,\r
RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),\r
RegisterTableEntry->ValidBitStart,\r
RegisterTableEntry->ValidBitLength,\r
case CacheControl:\r
DEBUG ((\r
DebugPrintErrorLevel,\r
- "Processor: %04d: Index %04d, CACHE: %08lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
- ProcessorNumber,\r
- FeatureIndex,\r
+ "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+ (UINT32) ProcessorNumber,\r
+ (UINT32) FeatureIndex,\r
RegisterTableEntry->Index,\r
RegisterTableEntry->ValidBitStart,\r
RegisterTableEntry->ValidBitLength,\r
DEBUG ((\r
DebugPrintErrorLevel,\r
"Processor: %04d: Index %04d, SEMAP: %s\r\n",\r
- ProcessorNumber,\r
- FeatureIndex,\r
+ (UINT32) ProcessorNumber,\r
+ (UINT32) FeatureIndex,\r
mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]\r
));\r
break;\r