Did not check in new files correctly the first time!

Updated FPD files that include Runtime driver as a new lib was added to Runtime Driver for the cache flush. Removed Cache Flush routine from EDK DXE SAL Lib.
Cleaned up BaseLib IPF cache routines to only Flush ranges when needed and not to flush the entire cache.

Removed the need for processor specific code in the Runtime driver by using MDE Cache Lib.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1822 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s
new file mode 100644 (file)
index 0000000..655ab37
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.s
@@ -0,0 +1,96 @@
+//++\r
+// Copyright (c) 2006, Intel Corporation                                                         \r
+// All rights reserved. This program and the accompanying materials                          \r
+// are licensed and made available under the terms and conditions of the BSD License         \r
+// which accompanies this distribution.  The full text of the license may be found at        \r
+// http://opensource.org/licenses/bsd-license.php                                            \r
+//                                                                                           \r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+// \r
+//  Module Name:\r
+//    FlushCacheRange.s \r
+//\r
+//  Abstract:\r
+//    Assemble routine to flush cache lines \r
+//\r
+// Revision History:\r
+//\r
+//--\r
+.file  "IpfCpuCache.s"\r
+\r
+#include  "IpfMacro.i"\r
+#include  "IpfDefines.h"\r
+\r
+//\r
+//  Invalidates a range of instruction cache lines in the cache coherency domain\r
+//  of the calling CPU.\r
+//\r
+//  Invalidates the instruction cache lines specified by Address and Length. If\r
+//  Address is not aligned on a cache line boundary, then entire instruction\r
+//  cache line containing Address is invalidated. If Address + Length is not\r
+//  aligned on a cache line boundary, then the entire instruction cache line\r
+//  containing Address + Length -1 is invalidated. This function may choose to\r
+//  invalidate the entire instruction cache if that is more efficient than\r
+//  invalidating the specified range. If Length is 0, the no instruction cache\r
+//  lines are invalidated. Address is returned.\r
+//\r
+//  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r
+//\r
+//  @param  Address The base address of the instruction cache lines to\r
+//                  invalidate. If the CPU is in a physical addressing mode, then\r
+//                  Address is a physical address. If the CPU is in a virtual\r
+//                  addressing mode, then Address is a virtual address.\r
+//\r
+//  @param  Length  The number of bytes to invalidate from the instruction cache.\r
+//\r
+//  @return Address\r
+//  \r
+//  VOID *\r
+//  EFIAPI\r
+//  IpfFlushCacheRange (\r
+//    IN      VOID                      *Address,\r
+//    IN      UINTN                     Length\r
+//    );\r
+//\r
+PROCEDURE_ENTRY (IpfFlushCacheRange)\r
+\r
+      NESTED_SETUP (5,8,0,0)\r
+            \r
+      mov         loc2 = ar.lc\r
+      \r
+      mov         loc3 = in0                  // Start address.\r
+      mov         loc4 = in1;;                // Length in bytes.\r
+      \r
+      cmp.eq  p6,p7 = loc4, r0;;               // If Length is zero then don't flush any cache\r
+      (p6)  br.spnt.many DoneFlushingC;;         \r
+      \r
+      add         loc4 = loc4,loc3 \r
+      mov         loc5 = 1;;\r
+      sub         loc4 = loc4, loc5 ;; // the End address to flush\r
+                                         \r
+      dep         loc3 = r0,loc3,0,5          \r
+      dep         loc4 = r0,loc4,0,5;;         \r
+      shr         loc3 = loc3,5             \r
+      shr         loc4 = loc4,5;;    // 32 byte cache line\r
+      \r
+      sub         loc4 = loc4,loc3;; // total flush count, It should be add 1 but \r
+                                     // the br.cloop will first execute one time \r
+      mov         loc3 = in0                  \r
+      mov         loc5 = 32      \r
+      mov         ar.lc = loc4;;\r
+\r
+StillFlushingC:\r
+      fc          loc3;; \r
+      sync.i;;\r
+      srlz.i;;\r
+      add         loc3 = loc5,loc3;;\r
+      br.cloop.sptk.few StillFlushingC;;\r
+\r
+DoneFlushingC:      \r
+      mov         ar.lc = loc2     \r
+      mov          r8   = in0       // return *Address\r
+      NESTED_RETURN\r
+\r
+PROCEDURE_EXIT (IpfFlushCacheRange)\r
+\r

diff --git a/MdePkg/Library/BaseLib/Ipf/ReadItc.s b/MdePkg/Library/BaseLib/Ipf/ReadItc.s
new file mode 100644 (file)
index 0000000..74759b5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ipf/ReadItc.s
@@ -0,0 +1,26 @@
+/// @file\r
+///   Contains an implementation of IpfReadItc () on Itanium-based\r
+///   architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution.  The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name:  ReadItc.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc   IpfReadItc\r
+.type   IpfReadItc, @function\r
+IpfReadItc::\r
+        mov                 r8  = ar.itc\r
+        br.ret.sptk.many    b0\r
+.endp   IpfReadItc\r