OvmfPkg/Bhyve: detach ResetVector from before the SEV-ES changes

Commits 6995a1b79bab, 8a2732186a53 and 30937f2f98c4 modified all four
regular files under "OvmfPkg/ResetVector" with SEV-ES dependencies.
These are not relevant for Bhyve. Detach the pre-SEV-ES version of
ResetVector for Bhyve.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Message-Id: <20201112053153.22038-2-rebecca@bsdio.com>
Acked-by: Peter Grehan <grehan@freebsd.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/OvmfPkg/Bhyve/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/Bhyve/ResetVector/Ia32/PageTables64.asm
new file mode 100644 (file)
index 0000000..d60cbfd
--- /dev/null
+++ b/OvmfPkg/Bhyve/ResetVector/Ia32/PageTables64.asm
@@ -0,0 +1,149 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+; Sets the CR3 register for 64-bit paging\r
+;\r
+; Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS    32\r
+\r
+%define PAGE_PRESENT            0x01\r
+%define PAGE_READ_WRITE         0x02\r
+%define PAGE_USER_SUPERVISOR    0x04\r
+%define PAGE_WRITE_THROUGH      0x08\r
+%define PAGE_CACHE_DISABLE     0x010\r
+%define PAGE_ACCESSED          0x020\r
+%define PAGE_DIRTY             0x040\r
+%define PAGE_PAT               0x080\r
+%define PAGE_GLOBAL           0x0100\r
+%define PAGE_2M_MBO            0x080\r
+%define PAGE_2M_PAT          0x01000\r
+\r
+%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r
+                          PAGE_ACCESSED + \\r
+                          PAGE_DIRTY + \\r
+                          PAGE_READ_WRITE + \\r
+                          PAGE_PRESENT)\r
+\r
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r
+                       PAGE_READ_WRITE + \\r
+                       PAGE_PRESENT)\r
+\r
+; Check if Secure Encrypted Virtualization (SEV) feature is enabled\r
+;\r
+; If SEV is enabled then EAX will be at least 32\r
+; If SEV is disabled then EAX will be zero.\r
+;\r
+CheckSevFeature:\r
+    ; Check if we have a valid (0x8000_001F) CPUID leaf\r
+    mov       eax, 0x80000000\r
+    cpuid\r
+\r
+    ; This check should fail on Intel or Non SEV AMD CPUs. In future if\r
+    ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact\r
+    ; same bit definition.\r
+    cmp       eax, 0x8000001f\r
+    jl        NoSev\r
+\r
+    ; Check for memory encryption feature:\r
+    ;  CPUID  Fn8000_001F[EAX] - Bit 1\r
+    ;\r
+    mov       eax,  0x8000001f\r
+    cpuid\r
+    bt        eax, 1\r
+    jnc       NoSev\r
+\r
+    ; Check if memory encryption is enabled\r
+    ;  MSR_0xC0010131 - Bit 0 (SEV enabled)\r
+    mov       ecx, 0xc0010131\r
+    rdmsr\r
+    bt        eax, 0\r
+    jnc       NoSev\r
+\r
+    ; Get pte bit position to enable memory encryption\r
+    ; CPUID Fn8000_001F[EBX] - Bits 5:0\r
+    ;\r
+    mov       eax, ebx\r
+    and       eax, 0x3f\r
+    jmp       SevExit\r
+\r
+NoSev:\r
+    xor       eax, eax\r
+\r
+SevExit:\r
+    OneTimeCallRet CheckSevFeature\r
+\r
+;\r
+; Modified:  EAX, EBX, ECX, EDX\r
+;\r
+SetCr3ForPageTables64:\r
+\r
+    OneTimeCall   CheckSevFeature\r
+    xor     edx, edx\r
+    test    eax, eax\r
+    jz      SevNotActive\r
+\r
+    ; If SEV is enabled, C-bit is always above 31\r
+    sub     eax, 32\r
+    bts     edx, eax\r
+\r
+SevNotActive:\r
+\r
+    ;\r
+    ; For OVMF, build some initial page tables at\r
+    ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r
+    ;\r
+    ; This range should match with PcdOvmfSecPageTablesSize which is\r
+    ; declared in the FDF files.\r
+    ;\r
+    ; At the end of PEI, the pages tables will be rebuilt into a\r
+    ; more permanent location by DxeIpl.\r
+    ;\r
+\r
+    mov     ecx, 6 * 0x1000 / 4\r
+    xor     eax, eax\r
+clearPageTablesMemoryLoop:\r
+    mov     dword[ecx * 4 + PT_ADDR (0) - 4], eax\r
+    loop    clearPageTablesMemoryLoop\r
+\r
+    ;\r
+    ; Top level Page Directory Pointers (1 * 512GB entry)\r
+    ;\r
+    mov     dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r
+    mov     dword[PT_ADDR (4)], edx\r
+\r
+    ;\r
+    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r
+    ;\r
+    mov     dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r
+    mov     dword[PT_ADDR (0x1004)], edx\r
+    mov     dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r
+    mov     dword[PT_ADDR (0x100C)], edx\r
+    mov     dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r
+    mov     dword[PT_ADDR (0x1014)], edx\r
+    mov     dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r
+    mov     dword[PT_ADDR (0x101C)], edx\r
+\r
+    ;\r
+    ; Page Table Entries (2048 * 2MB entries => 4GB)\r
+    ;\r
+    mov     ecx, 0x800\r
+pageTableEntriesLoop:\r
+    mov     eax, ecx\r
+    dec     eax\r
+    shl     eax, 21\r
+    add     eax, PAGE_2M_PDE_ATTR\r
+    mov     [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r
+    mov     [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx\r
+    loop    pageTableEntriesLoop\r
+\r
+    ;\r
+    ; Set CR3 now that the paging structures are available\r
+    ;\r
+    mov     eax, PT_ADDR (0)\r
+    mov     cr3, eax\r
+\r
+    OneTimeCallRet SetCr3ForPageTables64\r

diff --git a/OvmfPkg/Bhyve/ResetVector/ResetVector.inf b/OvmfPkg/Bhyve/ResetVector/ResetVector.inf
new file mode 100644 (file)
index 0000000..772dda5
--- /dev/null
+++ b/OvmfPkg/Bhyve/ResetVector/ResetVector.inf
@@ -0,0 +1,38 @@
+## @file\r
+#  Reset Vector\r
+#\r
+#  Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r
+#  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 1.29\r
+  BASE_NAME                      = ResetVector\r
+  FILE_GUID                      = 1BA0062E-C779-4582-8566-336AE8F78F09\r
+  MODULE_TYPE                    = SEC\r
+  VERSION_STRING                 = 1.1\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources]\r
+  ResetVector.nasmb\r
+\r
+[Packages]\r
+  OvmfPkg/OvmfPkg.dec\r
+  MdePkg/MdePkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+\r
+[BuildOptions]\r
+   *_*_IA32_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/\r
+   *_*_X64_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/\r
+\r
+[Pcd]\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase\r
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize\r

diff --git a/OvmfPkg/Bhyve/ResetVector/ResetVector.nasmb b/OvmfPkg/Bhyve/ResetVector/ResetVector.nasmb
new file mode 100644 (file)
index 0000000..ec869e8
--- /dev/null
+++ b/OvmfPkg/Bhyve/ResetVector/ResetVector.nasmb
@@ -0,0 +1,68 @@
+;------------------------------------------------------------------------------\r
+; @file\r
+; This file includes all other code files to assemble the reset vector code\r
+;\r
+; Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>.\r
+; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r
+; SPDX-License-Identifier: BSD-2-Clause-Patent\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+;\r
+; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include\r
+; Base.h to use the C pre-processor to determine the architecture.\r
+;\r
+%ifndef ARCH_IA32\r
+  %ifndef ARCH_X64\r
+    #include <Base.h>\r
+    #if defined (MDE_CPU_IA32)\r
+      %define ARCH_IA32\r
+    #elif defined (MDE_CPU_X64)\r
+      %define ARCH_X64\r
+    #endif\r
+  %endif\r
+%endif\r
+\r
+%ifdef ARCH_IA32\r
+  %ifdef ARCH_X64\r
+    %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."\r
+  %endif\r
+%elifdef ARCH_X64\r
+%else\r
+  %error "Either ARCH_IA32 or ARCH_X64 must be defined."\r
+%endif\r
+\r
+%include "CommonMacros.inc"\r
+\r
+%include "PostCodes.inc"\r
+\r
+%ifdef DEBUG_PORT80\r
+  %include "Port80Debug.asm"\r
+%elifdef DEBUG_SERIAL\r
+  %include "SerialDebug.asm"\r
+%else\r
+  %include "DebugDisabled.asm"\r
+%endif\r
+\r
+%include "Ia32/SearchForBfvBase.asm"\r
+%include "Ia32/SearchForSecEntry.asm"\r
+\r
+%ifdef ARCH_X64\r
+  #include <AutoGen.h>\r
+\r
+  %if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000)\r
+    %error "This implementation inherently depends on PcdOvmfSecPageTablesSize"\r
+  %endif\r
+\r
+  %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))\r
+%include "Ia32/Flat32ToFlat64.asm"\r
+%include "Ia32/PageTables64.asm"\r
+%endif\r
+\r
+%include "Ia16/Real16ToFlat32.asm"\r
+%include "Ia16/Init16.asm"\r
+\r
+%include "Main.asm"\r
+\r
+%include "Ia16/ResetVectorVtf0.asm"\r
+\r