This driver is not used by any platforms so remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/ArmLib.h>\r
-#include <Drivers/PL310L2Cache.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r
-#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)\r
-\r
-// Initialize PL320 L2 Cache Controller\r
-VOID\r
-L2x0CacheInit (\r
- IN UINTN L2x0Base,\r
- IN UINT32 L2x0TagLatencies,\r
- IN UINT32 L2x0DataLatencies,\r
- IN UINT32 L2x0AuxValue,\r
- IN UINT32 L2x0AuxMask,\r
- IN BOOLEAN CacheEnabled\r
- )\r
-{\r
- UINT32 Data;\r
- UINT32 Revision;\r
- UINT32 Aux;\r
- UINT32 PfCtl;\r
- UINT32 PwrCtl;\r
-\r
- // Check if L2x0 is present and is an ARM implementation\r
- Data = L2x0ReadReg(L2X0_CACHEID);\r
- if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // Check if L2x0 is PL310\r
- if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r
- ASSERT(0);\r
- return;\r
- }\r
-\r
- // RTL release\r
- Revision = Data & 0x3F;\r
-\r
- // Check if L2x0 is already enabled then we disable it\r
- Data = L2x0ReadReg(L2X0_CTRL);\r
- if (Data & L2X0_CTRL_ENABLED) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r
- }\r
-\r
- //\r
- // Set up global configurations\r
- //\r
-\r
- // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r
- Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r
- // Use AWCACHE attributes for WA\r
- Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
- // Use default Size\r
- Data = L2x0ReadReg(L2X0_AUXCTRL);\r
- Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;\r
- // Use default associativity\r
- Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;\r
- // Enabled I & D Prefetch\r
- Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
-\r
- if (Revision >= 5) {\r
- // Prefetch Offset Register\r
- PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r
- // - Prefetch increment set to 0\r
- // - Prefetch dropping off\r
- // - Double linefills off\r
- L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r
-\r
- // Power Control Register - L2X0_PWRCTRL\r
- PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r
- // - Standby when idle off\r
- // - Dynamic clock gating off\r
- // - Nc,NC-shared dropping off\r
- L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
- }\r
-\r
- if (Revision >= 2) {\r
- L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);\r
- L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);\r
- } else {\r
- // PL310 old style latency is not supported yet\r
- ASSERT(0);\r
- }\r
-\r
- // Set the platform specific values\r
- Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;\r
-\r
- // Write Auxiliary value\r
- L2x0WriteReg(L2X0_AUXCTRL, Aux);\r
-\r
- //\r
- // Invalidate all entries in cache\r
- //\r
- L2x0WriteReg(L2X0_INVWAY, 0xffff);\r
- // Poll cache maintenance register until invalidate operation is complete\r
- while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r
-\r
- // Write to the Lockdown D and Lockdown I Register 9 if required\r
- // - Not required\r
-\r
- // Clear any residual raw interrupts\r
- L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r
-\r
- // Enable the cache\r
- if (CacheEnabled) {\r
- L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r
- }\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL310L2Cache\r
- FILE_GUID = 16ad4fe0-b5b1-11df-8cbf-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = L2X0CacheLib\r
-\r
-[Sources]\r
- PL310L2Cache.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef L2CACHELIB_H_\r
-#define L2CACHELIB_H_\r
-\r
-#define L2X0_CACHEID 0x000\r
-#define L2X0_CTRL 0x100\r
-#define L2X0_AUXCTRL 0x104\r
-#define L230_TAG_LATENCY 0x108\r
-#define L230_DATA_LATENCY 0x10C\r
-#define L2X0_INTCLEAR 0x220\r
-#define L2X0_CACHE_SYNC 0x730\r
-#define L2X0_INVWAY 0x77C\r
-#define L2X0_CLEAN_WAY 0x7BC\r
-#define L2X0_PFCTRL 0xF60\r
-#define L2X0_PWRCTRL 0xF80\r
-\r
-#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41\r
-#define L2X0_CACHEID_PARTNUM_PL310 0x03\r
-\r
-#define L2X0_CTRL_ENABLED 0x1\r
-#define L2X0_CTRL_DISABLED 0x0\r
-\r
-#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)\r
-#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)\r
-#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)\r
-#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)\r
-#define L2X0_AUXCTRL_EM (1 << 20)\r
-#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)\r
-#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)\r
-#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)\r
-#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)\r
-#define L2X0_AUXCTRL_SBO (1 << 25)\r
-#define L2X0_AUXCTRL_NSAC (1 << 27)\r
-#define L2x0_AUXCTRL_DPREFETCH (1 << 28)\r
-#define L2x0_AUXCTRL_IPREFETCH (1 << 29)\r
-#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)\r
-\r
-#define L2x0_LATENCY_1_CYCLE 0\r
-#define L2x0_LATENCY_2_CYCLES 1\r
-#define L2x0_LATENCY_3_CYCLES 2\r
-#define L2x0_LATENCY_4_CYCLES 3\r
-#define L2x0_LATENCY_5_CYCLES 4\r
-#define L2x0_LATENCY_6_CYCLES 5\r
-#define L2x0_LATENCY_7_CYCLES 6\r
-#define L2x0_LATENCY_8_CYCLES 7\r
-\r
-#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))\r
-#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
-#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)\r
-\r
-VOID\r
-L2x0CacheInit (\r
- IN UINTN L2x0Base,\r
- IN UINT32 L2x0TagLatencies,\r
- IN UINT32 L2x0DataLatencies,\r
- IN UINT32 L2x0AuxValue,\r
- IN UINT32 L2x0AuxMask,\r
- IN BOOLEAN CacheEnabled\r
- );\r
-\r
-#endif /* L2CACHELIB_H_ */\r
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