ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3

This is already taken care by Sec when PcdTrustzoneSupport = TRUE.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 39f264251bb13038a09705cd498ecaab1b7d680e..0f094c12a23b0d0ad3794f9a79969b09eb70ab4c 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -110,24 +110,6 @@
   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B\r
   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C\r
   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D\r
- \r
-  #\r
-  # ARM Security Extension\r
-  #\r
-  \r
-  # Secure Configuration Register\r
-  # - BIT0 : NS - Non Secure bit \r
-  # - BIT1 : IRQ Handler\r
-  # - BIT2 : FIQ Handler\r
-  # - BIT3 : EA - External Abort\r
-  # - BIT4 : FW - F bit writable\r
-  # - BIT5 : AW - A bit writable\r
-  # - BIT6 : nET - Not Early Termination\r
-  # - BIT7 : SCD - Secure Monitor Call Disable\r
-  # - BIT8 : HCE - Hyp Call enable\r
-  # - BIT9 : SIF - Secure Instruction Fetch\r
-  # 0x31 = NS | EA | FW\r
-  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
 \r
   # System Memory (DRAM): These PCDs define the region of in-built system memory\r
   # Some platforms can get DRAM extensions, these additional regions will be declared\r
@@ -161,6 +143,24 @@
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
 \r
 [PcdsFixedAtBuild.ARM]\r
+  #\r
+  # ARM Security Extension\r
+  #\r
+\r
+  # Secure Configuration Register\r
+  # - BIT0 : NS - Non Secure bit\r
+  # - BIT1 : IRQ Handler\r
+  # - BIT2 : FIQ Handler\r
+  # - BIT3 : EA - External Abort\r
+  # - BIT4 : FW - F bit writable\r
+  # - BIT5 : AW - A bit writable\r
+  # - BIT6 : nET - Not Early Termination\r
+  # - BIT7 : SCD - Secure Monitor Call Disable\r
+  # - BIT8 : HCE - Hyp Call enable\r
+  # - BIT9 : SIF - Secure Instruction Fetch\r
+  # 0x31 = NS | EA | FW\r
+  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038\r
+\r
   # By default we do not do a transition to non-secure mode\r
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
 \r
@@ -183,6 +183,28 @@
   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039\r
 \r
 [PcdsFixedAtBuild.AARCH64]\r
+  #\r
+  # AArch64 Security Extension\r
+  #\r
+\r
+  # Secure Configuration Register\r
+  # - BIT0 : NS - Non Secure bit\r
+  # - BIT1 : IRQ Handler\r
+  # - BIT2 : FIQ Handler\r
+  # - BIT3 : EA - External Abort\r
+  # - BIT4 : FW - F bit writable\r
+  # - BIT5 : AW - A bit writable\r
+  # - BIT6 : nET - Not Early Termination\r
+  # - BIT7 : SCD - Secure Monitor Call Disable\r
+  # - BIT8 : HCE - Hyp Call enable\r
+  # - BIT9 : SIF - Secure Instruction Fetch\r
+  # - BIT10: RW -  Register width control for lower exception levels\r
+  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
+  # - BIT12: TWI - Trap WFI\r
+  # - BIT13: TWE - Trap WFE\r
+  # 0x501 = NS | HCE | RW\r
+  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
+\r
   # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
   #        Mode Description              Bits\r
   # NS EL2 SP2 all interupts disabled =  0x3c9\r

diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S
index ff4625576355701365b640b3ddfac31cb10eb958..3b833bad7cfb67ac14eb2359aeaa561d6cc2a114 100644 (file)
--- a/ArmPlatformPkg/Sec/AArch64/Helper.S
+++ b/ArmPlatformPkg/Sec/AArch64/Helper.S
@@ -26,20 +26,6 @@ ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
 ASM_GLOBAL ASM_PFX(set_non_secure_mode)\r
 \r
 ASM_PFX(SetupExceptionLevel3):\r
-   mrs    x0, scr_el3            // Read EL3 Secure Configuration Register\r
-   orr    x0, x0, #1             // EL0 an EL1 cannot access secure memory\r
-\r
-   // Send all interrupts to their respective Exception levels for EL3\r
-   bic    x0, x0, #(1 << 1)      // IRQ\r
-   bic    x0, x0, #(1 << 2)      // FIQ\r
-   bic    x0, x0, #(1 << 3)      // Serror and Abort\r
-   orr    x0, x0, #(1 << 8)      // Enable HVC\r
-   orr    x0, x0, #(1 << 10)     // Make next level down 64Bit. This is EL2 in the case of the Model.\r
-                                 // We need a nice way to detect this.\r
-   msr    scr_el3, x0            // Write back our settings\r
-\r
-   msr    cptr_el3, xzr          // Disable copro traps to EL3\r
-\r
    // Check for the primary CPU to avoid a race on the distributor registers.\r
    mrs     x0, mpidr_el1\r
    tst     x0, #15\r