+++ /dev/null
-/** @file\r
-* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __ARM_VEXPRESS_H__\r
-#define __ARM_VEXPRESS_H__\r
-\r
-#include <Base.h>\r
-#include <VExpressMotherBoard.h>\r
-\r
-/***********************************************************************************\r
-// Platform Memory Map\r
-************************************************************************************/\r
-\r
-// Can be NOR0, NOR1, DRAM\r
-#define ARM_VE_REMAP_BASE 0x00000000\r
-#define ARM_VE_REMAP_SZ SIZE_64MB\r
-\r
-// Motherboard Peripheral and On-chip peripheral\r
-#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
-#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB\r
-#define ARM_VE_BOARD_PERIPH_BASE 0x10000000\r
-#define ARM_VE_CHIP_PERIPH_BASE 0x10020000\r
-\r
-// SMC\r
-#define ARM_VE_SMC_BASE 0x40000000\r
-#define ARM_VE_SMC_SZ 0x1C000000\r
-\r
-// NOR Flash 1\r
-#define ARM_VE_SMB_NOR0_BASE 0x40000000\r
-#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
-// NOR Flash 2\r
-#define ARM_VE_SMB_NOR1_BASE 0x44000000\r
-#define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r
-// SRAM\r
-#define ARM_VE_SMB_SRAM_BASE 0x48000000\r
-#define ARM_VE_SMB_SRAM_SZ SIZE_32MB\r
-// USB, Ethernet, VRAM\r
-#define ARM_VE_SMB_PERIPH_BASE 0x4C000000\r
-#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r
-#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
-\r
-// DRAM\r
-#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)\r
-#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)\r
-// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
-#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
-\r
-// External AXI between daughterboards (Logic Tile)\r
-#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
-#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */\r
-\r
-\r
-/***********************************************************************************\r
- Core Tile memory-mapped Peripherals\r
-************************************************************************************/\r
-\r
-// PL111 Colour LCD Controller - core tile\r
-#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)\r
-#define PL111_CLCD_SITE ARM_VE_DAUGHTERBOARD_1_SITE\r
-\r
-// PL341 Dynamic Memory Controller Base\r
-#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)\r
-\r
-// PL354 Static Memory Controller Base\r
-#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
-\r
-// System Configuration Controller register Base addresses\r
-#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
-#define ARM_VE_SCC_BASE ARM_VE_SYS_CFG_CTRL_BASE\r
-#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
-#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)\r
-#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)\r
-\r
-// SP805 Watchdog on Cortex A9 core tile\r
-#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)\r
-\r
-// BP147 TZPC Base Address\r
-#define ARM_VE_TZPC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)\r
-\r
-// PL301 Fast AXI Base Address\r
-#define ARM_VE_FAXI_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)\r
-\r
-// TZASC Trust Zone Address Space Controller Base Address\r
-#define ARM_VE_TZASC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)\r
-\r
-// PL310 L2x0 Cache Controller Base Address\r
-//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
-\r
-/***********************************************************************************\r
- Peripherals' misc settings\r
-************************************************************************************/\r
-\r
-#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000\r
-#define ARM_VE_CFGRW1_REMAP_NOR0 0\r
-#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)\r
-#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
-#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)\r
-\r
-// TZASC - Other settings\r
-#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)\r
-#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)\r
-#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)\r
-#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)\r
-#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)\r
-#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)\r
-#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
-#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
-\r
-#endif\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = CTA9x4ArmVExpressLib\r
- FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- ArmTrustZoneLib\r
- MemoryAllocationLib\r
- PL341DmcLib\r
- PL301AxiLib\r
-\r
-[Sources.common]\r
- CTA9x4Helper.asm | RVCT\r
- CTA9x4Helper.S | GCC\r
- CTA9x4.c\r
- CTA9x4Mem.c\r
- CTA9x4Helper.S | GCC\r
- CTA9x4Helper.asm | RVCT\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = CTA9x4ArmVExpressLibSec\r
- FILE_GUID = 8d25ef2c-2015-416e-b8aa-2369fecd4bda\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- ArmTrustZoneLib\r
- PL341DmcLib\r
- PL301AxiLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- CTA9x4.c\r
- CTA9x4Helper.S | GCC\r
- CTA9x4Helper.asm | RVCT\r
-\r
-[FeaturePcd]\r
- gEmbeddedTokenSpaceGuid.PcdCacheEnable\r
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase\r
- gArmTokenSpaceGuid.PcdSystemMemorySize\r
-\r
- gArmTokenSpaceGuid.PcdArmPrimaryCoreMask\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore\r
-\r
-[Ppis]\r
- gArmMpCoreInfoPpiGuid\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Drivers/PL341Dmc.h>\r
-#include <Drivers/PL301Axi.h>\r
-#include <Drivers/SP804Timer.h>\r
-\r
-#include <Ppi/ArmMpCoreInfo.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {\r
- {\r
- // Cluster 0, Core 0\r
- 0x0, 0x0,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 1\r
- 0x0, 0x1,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 2\r
- 0x0, 0x2,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- },\r
- {\r
- // Cluster 0, Core 3\r
- 0x0, 0x3,\r
-\r
- // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
- (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
- (UINT64)0xFFFFFFFF\r
- }\r
-};\r
-\r
-// DDR2 timings\r
-PL341_DMC_CONFIG DDRTimings = {\r
- .MaxChip = 1,\r
- .IsUserCfg = TRUE,\r
- .User0Cfg = 0x7C924924,\r
- .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),\r
- .HasQos = TRUE,\r
- .RefreshPeriod = 0x3D0,\r
- .CasLatency = 0x8,\r
- .WriteLatency = 0x3,\r
- .t_mrd = 0x2,\r
- .t_ras = 0xA,\r
- .t_rc = 0xE,\r
- .t_rcd = 0x104,\r
- .t_rfc = 0x2f32,\r
- .t_rp = 0x14,\r
- .t_rrd = 0x2,\r
- .t_wr = 0x4,\r
- .t_wtr = 0x2,\r
- .t_xp = 0x2,\r
- .t_xsr = 0xC8,\r
- .t_esr = 0x14,\r
- .MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |\r
- DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,\r
- .MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |\r
- DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,\r
- .MemoryCfg3 = 0x00000001,\r
- .ChipCfg0 = 0x00010000,\r
- .t_faw = 0x00000A0D,\r
- .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,\r
- .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),\r
-};\r
-\r
-/**\r
- Return the current Boot Mode\r
-\r
- This function returns the boot reason on the platform\r
-\r
- @return Return the current Boot Mode of the platform\r
-\r
-**/\r
-EFI_BOOT_MODE\r
-ArmPlatformGetBootMode (\r
- VOID\r
- )\r
-{\r
- if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {\r
- return BOOT_WITH_FULL_CONFIGURATION;\r
- } else {\r
- return BOOT_ON_S2_RESUME;\r
- }\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup in the normal world\r
-\r
- This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r
- in the PEI phase.\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // Configure periodic timer (TIMER0) for 1MHz operation\r
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
- // Configure 1MHz clock\r
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
- // configure SP810 to use 1MHz clock and disable\r
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
- // Configure SP810 to use 1MHz clock and disable\r
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Initialize the system (or sometimes called permanent) memory\r
-\r
- This memory is generally represented by the DRAM.\r
-\r
-**/\r
-VOID\r
-ArmPlatformInitializeSystemMemory (\r
- VOID\r
- )\r
-{\r
- PL341DmcInit (ARM_VE_DMC_BASE, &DDRTimings);\r
- PL301AxiInit (ARM_VE_FAXI_BASE);\r
-}\r
-\r
-EFI_STATUS\r
-PrePeiCoreGetMpCoreInfo (\r
- OUT UINTN *CoreCount,\r
- OUT ARM_CORE_INFO **ArmCoreTable\r
- )\r
-{\r
- *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);\r
- *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;\r
-\r
- return EFI_SUCCESS;\r
-}\r
-\r
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
-\r
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
- {\r
- EFI_PEI_PPI_DESCRIPTOR_PPI,\r
- &gArmMpCoreInfoPpiGuid,\r
- &mMpCoreInfoPpi\r
- }\r
-};\r
-\r
-VOID\r
-ArmPlatformGetPlatformPpiList (\r
- OUT UINTN *PpiListSize,\r
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
- )\r
-{\r
- *PpiListSize = sizeof(gPlatformPpiTable);\r
- *PpiList = gPlatformPpiTable;\r
-}\r
-\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmLib.h>\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r
- MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore))\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformIsPrimaryCore)\r
- MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask))\r
- and r0, r0, r1\r
- MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore))\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ASM_FUNC(ArmPlatformGetCorePosition)\r
- and r0, r0, #ARM_CORE_MASK\r
- bx lr\r
-\r
-ASM_FUNC(ArmPlatformPeiBootAction)\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Library/ArmLib.h>\r
-\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformPeiBootAction\r
- EXPORT ArmPlatformIsPrimaryCore\r
- EXPORT ArmPlatformGetPrimaryCoreMpId\r
- EXPORT ArmPlatformGetCorePosition\r
-\r
- AREA CTA9x4Helper, CODE, READONLY\r
-\r
-//UINTN\r
-//ArmPlatformGetPrimaryCoreMpId (\r
-// VOID\r
-// );\r
-ArmPlatformGetPrimaryCoreMpId FUNCTION\r
- mov32 r0, FixedPcdGet32(PcdArmPrimaryCore)\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformIsPrimaryCore (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformIsPrimaryCore FUNCTION\r
- mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask)\r
- and r0, r0, r1\r
- mov32 r1, FixedPcdGet32(PcdArmPrimaryCore)\r
- cmp r0, r1\r
- moveq r0, #1\r
- movne r0, #0\r
- bx lr\r
- ENDFUNC\r
-\r
-//UINTN\r
-//ArmPlatformGetCorePosition (\r
-// IN UINTN MpId\r
-// );\r
-ArmPlatformGetCorePosition FUNCTION\r
- and r0, r0, #ARM_CORE_MASK\r
- bx lr\r
- ENDFUNC\r
-\r
-ArmPlatformPeiBootAction FUNCTION\r
- bx lr\r
- ENDFUNC\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-// Number of Virtual Memory Map Descriptors without a Logic Tile\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6\r
-\r
-// DDR attributes\r
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
-\r
-/**\r
- Return the Virtual Memory Map of your platform\r
-\r
- This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
-\r
- @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
- Virtual Memory mapping. This array must be ended by a zero-filled\r
- entry\r
-\r
-**/\r
-VOID\r
-ArmPlatformGetVirtualMemoryMap (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
- )\r
-{\r
- ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
- UINTN Index = 0;\r
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
-\r
- ASSERT(VirtualMemoryMap != NULL);\r
-\r
- VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
- if (VirtualMemoryTable == NULL) {\r
- return;\r
- }\r
-\r
- if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
- CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
- } else {\r
- CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
- }\r
-\r
- if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {\r
- // ReMap (Either NOR Flash or DRAM)\r
- VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
- }\r
-\r
- // DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // SMC CS7\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS0-CS1 - NOR Flash 1 & 2\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // SMB CS2 - SRAM\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
- VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
-\r
- // SMB CS3-CS6 - Motherboard Peripherals\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- // If a Logic Tile is connected to The ARM Versatile Express Motherboard\r
- if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {\r
- VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;\r
- VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;\r
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
-\r
- ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));\r
- } else {\r
- ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
- }\r
-\r
- // End of Table\r
- VirtualMemoryTable[++Index].PhysicalBase = 0;\r
- VirtualMemoryTable[Index].VirtualBase = 0;\r
- VirtualMemoryTable[Index].Length = 0;\r
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
-\r
- *VirtualMemoryMap = VirtualMemoryTable;\r
-}\r
projects / mirror_edk2.git / commitdiff