ArmPlaformPkg/ArmVExpressPkg: Move initialization of SP810 at the early stage of...

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12644 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
index 8aeedda92963aec63a2b975786cf597b3917dd96..6cb5501ae7ebb9da1f28a244a82a9260860fafe3 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
@@ -17,8 +17,6 @@
 #include <Library/DebugLib.h>
 #include <Library/PcdLib.h>
 
-#include <Drivers/SP804Timer.h>
-
 #include <Ppi/ArmMpCoreInfo.h>
 
 #include <ArmPlatform.h>
@@ -114,14 +112,7 @@ ArmPlatformInitializeSystemMemory (
   VOID
   )
 {
-  // Configure periodic timer (TIMER0) for 1MHz operation
-  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
-  // Configure 1MHz clock
-  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
-  // configure SP810 to use 1MHz clock and disable
-  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
-  // Configure SP810 to use 1MHz clock and disable
-  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+  // Nothing to do here
 }
 
 EFI_STATUS

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c
index 76a8bc1ba080dee97fe2452fb7f587c80fad2fd2..a4eee5ca0cde6da585a8553931a008157862b8c4 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c
@@ -18,6 +18,8 @@
 #include <Library/DebugLib.h>
 #include <Library/PcdLib.h>
 #include <Drivers/PL310L2Cache.h>
+#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
 
 /**
   Initialize the Secure peripherals and memory regions
@@ -46,6 +48,14 @@ ArmPlatformSecInitialize (
   VOID
   )
 {
+  // Configure periodic timer (TIMER0) for 1MHz operation
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+  // Configure 1MHz clock
+  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+  // Configure SP810 to use 1MHz clock and disable
+  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 }
 
 /**