MdePkg: MmConfiguration: Added definition of MM Configuration PPI

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3440

MM Configuration PPI was defined in PI Specification since v1.5. This
change added definition of such PPI and related GUIDs into MdePkg.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

diff --git a/MdePkg/Include/Ppi/MmConfiguration.h b/MdePkg/Include/Ppi/MmConfiguration.h
new file mode 100644 (file)
index 0000000..862a80e
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmConfiguration.h
@@ -0,0 +1,62 @@
+/** @file\r
+  EFI MM Configuration PPI as defined in PI 1.5 specification.\r
+\r
+  This PPI is used to:\r
+  1) report the portions of MMRAM regions which cannot be used for the MMRAM heap.\r
+  2) register the MM Foundation entry point with the processor code. The entry\r
+     point will be invoked by the MM processor entry code.\r
+\r
+  Copyright (c) Microsoft Corporation.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef MM_CONFIGURATION_PPI_H_\r
+#define MM_CONFIGURATION_PPI_H_\r
+\r
+#include <Pi/PiMultiPhase.h>\r
+\r
+#define EFI_PEI_MM_CONFIGURATION_PPI_GUID \\r
+  { \\r
+    0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 }  \\r
+  }\r
+\r
+typedef struct _EFI_PEI_MM_CONFIGURATION_PPI  EFI_PEI_MM_CONFIGURATION_PPI;\r
+\r
+/**\r
+  This function registers the MM Foundation entry point with the processor code. This entry point will be\r
+  invoked by the MM Processor entry code as defined in PI specification.\r
+\r
+  @param[in]  This            The EFI_PEI_MM_CONFIGURATION_PPI instance.\r
+  @param[in]  MmEntryPoint    MM Foundation entry point.\r
+\r
+  @retval EFI_SUCCESS         The entry-point was successfully registered.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) (\r
+  IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This,\r
+  IN EFI_MM_ENTRY_POINT                 MmEntryPoint\r
+  );\r
+\r
+///\r
+/// This PPI is a PPI published by a CPU PEIM to indicate which areas within MMRAM are reserved for use by\r
+/// the CPU for any purpose, such as stack, save state or MM entry point. If a platform chooses to let a CPU\r
+/// PEIM do MMRAM relocation, this PPI must be produced by this CPU PEIM.\r
+///\r
+/// The MmramReservedRegions points to an array of one or more EFI_MM_RESERVED_MMRAM_REGION structures, with\r
+/// the last structure having the MmramReservedSize set to 0. An empty array would contain only the last\r
+/// structure.\r
+///\r
+/// The RegisterMmEntry() function allows the MM IPL PEIM to register the MM Foundation entry point with the\r
+/// MM entry vector code.\r
+///\r
+struct _EFI_PEI_MM_CONFIGURATION_PPI {\r
+  EFI_MM_RESERVED_MMRAM_REGION  *MmramReservedRegions;\r
+  EFI_PEI_MM_REGISTER_MM_ENTRY  RegisterMmEntry;\r
+};\r
+\r
+extern EFI_GUID gEfiPeiMmConfigurationPpi;\r
+\r
+#endif\r

diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index b49f88d8e18f8a5fc4c25277763b4bf4c43f2463..c5319fdd71ca1c105abf199233c35c95c0bc7c31 100644 (file)
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -983,6 +983,9 @@
   ## Include/Ppi/MmControl.h\r
   gEfiPeiMmControlPpiGuid         =  { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}\r
 \r
+  ## Include/Ppi/MmConfiguration.h\r
+  gEfiPeiMmConfigurationPpi       =  { 0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } }\r
+\r
   #\r
   # PPIs defined in PI 1.7.\r
   #\r