UefiCpuPkg: SmmCpuFeaturesLib: Add MSR_SMM_FEATURE_CONTROL support

Add support for the reading and writing MSR_SMM_FEATURE_CONTROL
through the SmmCpuFeaturesIsSmmRegisterSupported(),
SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister()
functions.  This MSR is supported if the Family/Model is 06_3C,
06_45, or 06_46.

Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18690 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 4f2f9b65fa375523475b62c76b3fce952d6efd6e..0c1610d9777cf2bc3bbbfda015130fb959e587e3 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -33,12 +33,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define  SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK  0x0A1\r
 #define    EFI_MSR_SMRR_MASK                       0xFFFFF000\r
 #define    EFI_MSR_SMRR_PHYS_MASK_VALID            BIT11\r
+#define  SMM_FEATURES_LIB_SMM_FEATURE_CONTROL      0x4E0\r
 \r
 //\r
 // Set default value to assume SMRR is not supported\r
 //\r
 BOOLEAN  mSmrrSupported = FALSE;\r
 \r
+//\r
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported\r
+//\r
+BOOLEAN  mSmmFeatureControlSupported = FALSE;\r
+\r
 //\r
 // Set default value to assume IA-32 Architectural MSRs are used\r
 //\r
@@ -125,6 +131,20 @@ SmmCpuFeaturesLibConstructor (
     }\r
   }\r
 \r
+  //\r
+  // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+  // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
+  // Processor Family\r
+  //\r
+  // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
+  // Intel(R) Core(TM) Processor Family MSRs\r
+  //\r
+  if (FamilyId == 0x06) {\r
+    if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
+      mSmmFeatureControlSupported = TRUE;\r
+    }\r
+  }\r
+\r
   //\r
   // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
   // Volume 3C, Section 34.4.2 SMRAM Caching\r
@@ -457,6 +477,9 @@ SmmCpuFeaturesIsSmmRegisterSupported (
   IN SMM_REG_NAME  RegName\r
   )\r
 {\r
+  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+    return TRUE;\r
+  }\r
   return FALSE;\r
 }\r
 \r
@@ -479,6 +502,9 @@ SmmCpuFeaturesGetSmmRegister (
   IN SMM_REG_NAME  RegName\r
   )\r
 {\r
+  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+    return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
+  }\r
   return 0;\r
 }\r
 \r
@@ -501,6 +527,9 @@ SmmCpuFeaturesSetSmmRegister (
   IN UINT64        Value\r
   )\r
 {\r
+  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+    AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
+  }\r
 }\r
 \r
 /**\r