MdePkg/DebugAgent: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESS

Avoid use of Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS) if there is only 1 CPU present.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17218 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
index 6ae9deef10c78cc3662c2e19b0890abc4be78bf1..bdb6742811ea03f47ffea623b8480f1ef9f800eb 100644 (file)
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
@@ -1,7 +1,7 @@
 /** @file\r
   Multi-Processor support functions implementation.\r
 \r
 /** @file\r
   Multi-Processor support functions implementation.\r
 \r

-  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -138,9 +138,18 @@ GetProcessorIndex (
 **/\r
 BOOLEAN\r
 IsBsp (\r
 **/\r
 BOOLEAN\r
 IsBsp (\r

-  IN UINT32             ProcessorIndex\r
+  IN UINT32  ProcessorIndex\r

   )\r
 {\r
   )\r
 {\r

+  //\r
+  // If there are less than 2 CPUs detected, then the currently executing CPU\r
+  // must be the BSP.  This avoids an access to an MSR that may not be supported \r
+  // on single core CPUs.\r
+  //\r
+  if (mDebugCpuData.CpuCount < 2) {\r
+    return TRUE;\r
+  }\r
+\r

   if (AsmMsrBitFieldRead64 (MSR_IA32_APIC_BASE_ADDRESS, 8, 8) == 1) {\r
     if (mDebugMpContext.BspIndex != ProcessorIndex) {\r
       AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock);\r
   if (AsmMsrBitFieldRead64 (MSR_IA32_APIC_BASE_ADDRESS, 8, 8) == 1) {\r
     if (mDebugMpContext.BspIndex != ProcessorIndex) {\r
       AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock);\r