Factor out the expression that is currently the basis of the address width
calculation into a standalone function. In the next patches we'll raise
the return value under certain circumstances.
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Thomas Lamprecht <t.lamprecht@proxmox.com>
Ref: https://github.com/tianocore/edk2/issues/59
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
}\r
\r
\r
+/**\r
+ Return the highest address that DXE could possibly use, plus one.\r
+**/\r
+STATIC\r
+UINT64\r
+GetFirstNonAddress (\r
+ VOID\r
+ )\r
+{\r
+ UINT64 FirstNonAddress;\r
+\r
+ FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
+ return FirstNonAddress;\r
+}\r
+\r
+\r
/**\r
Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
**/\r
// The DXL IPL keys off of the physical address bits advertized in the CPU\r
// HOB. To conserve memory, we calculate the minimum address width here.\r
//\r
- FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
+ FirstNonAddress = GetFirstNonAddress ();\r
mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
\r
//\r