#\r
INF OvmfPkg/Sec/SecMain.inf\r
\r
-INF RuleOverride=RESET_VECTOR OvmfPkg/ResetVector/Bin/ResetVector.inf\r
+INF RuleOverride=RESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf\r
\r
################################################################################\r
[FV.MAINFV]\r
INF OvmfPkg/Sec/SecMain.inf\r
\r
FILE RAW = 1BA0062E-C779-4582-8566-336AE8F78F09 {\r
- SECTION RAW = OvmfPkg/ResetVector/Bin/ResetVector.ia32.raw\r
+ SECTION RAW = UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.ia32.raw\r
}\r
\r
################################################################################\r
+++ /dev/null
-#/** @file\r
-# Reset Vector binary\r
-#\r
-# Copyright (c) 2006 - 2009, Intel Corporation.\r
-#\r
-# All rights reserved. This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ResetVector\r
- FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.1\r
- EDK_RELEASE_VERSION = 0x00020000\r
- EFI_SPECIFICATION_VERSION = 0x00020000\r
-\r
-#\r
-# The following information is for reference only and not required by the build tools.\r
-#\r
-# VALID_ARCHITECTURES = IA32 X64\r
-#\r
-\r
-[Binaries.Ia32]\r
- RAW|ResetVector.ia32.raw|*\r
-\r
-[Binaries.X64]\r
- RAW|ResetVector.x64.raw|*\r
-\r
+++ /dev/null
-## @file
-# Automate the process of building the various reset vector types
-#
-# Copyright (c) 2009, Intel Corporation
-#
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-import glob
-import os
-import subprocess
-import sys
-
-def RunCommand(commandLine):
- #print ' '.join(commandLine)
- return subprocess.call(commandLine)
-
-for filename in glob.glob(os.path.join('Bin', '*.raw')):
- os.remove(filename)
-
-for arch in ('ia32', 'x64'):
- for debugType in (None, 'port80', 'serial'):
- output = os.path.join('Bin', 'ResetVector')
- output += '.' + arch
- if debugType is not None:
- output += '.' + debugType
- output += '.raw'
- commandLine = (
- 'nasm',
- '-D', 'ARCH_%s' % arch.upper(),
- '-D', 'DEBUG_%s' % str(debugType).upper(),
- '-o', output,
- 'ResetVectorCode.asm',
- )
- ret = RunCommand(commandLine)
- print '\tASM\t' + output
- if ret != 0: sys.exit(ret)
-
- commandLine = (
- 'python',
- 'Tools/FixupForRawSection.py',
- output,
- )
- print '\tFIXUP\t' + output
- ret = RunCommand(commandLine)
- if ret != 0: sys.exit(ret)
-
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Common macros used in the ResetVector VTF module.\r
-;\r
-; Copyright (c) 2008, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)\r
-%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)\r
-\r
-%macro OneTimeCall 1\r
- jmp %1\r
-%1 %+ OneTimerCallReturn:\r
-%endmacro\r
-\r
-%macro OneTimeCallRet 1\r
- jmp %1 %+ OneTimerCallReturn\r
-%endmacro\r
-\r
-StartOfResetVectorCode:\r
-\r
-%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode)\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Debug disabled\r
-;\r
-; Copyright (c) 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 16\r
-\r
-%macro debugInitialize 0\r
- ;\r
- ; No initialization is required\r
- ;\r
-%endmacro\r
-\r
-%macro debugShowPostCode 1\r
-%endmacro\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Transition from 16 bit real mode into 32 bit flat protected mode\r
-;\r
-; Copyright (c) 2008 - 2010, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-%define SEC_DEFAULT_CR0 0x40000023\r
-%define SEC_DEFAULT_CR4 0x640\r
-\r
-BITS 16\r
-\r
-;\r
-; Modified: EAX, EBX\r
-;\r
-TransitionFromReal16To32BitFlat:\r
-\r
- debugShowPostCode POSTCODE_16BIT_MODE\r
-\r
- cli\r
-\r
- mov bx, 0xf000\r
- mov ds, bx\r
-\r
- mov bx, ADDR16_OF(gdtr)\r
-\r
-o32 lgdt [cs:bx]\r
-\r
- mov eax, SEC_DEFAULT_CR0\r
- mov cr0, eax\r
-\r
- jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere)\r
-BITS 32\r
-jumpTo32BitAndLandHere:\r
-\r
- mov eax, SEC_DEFAULT_CR4\r
- mov cr4, eax\r
-\r
- debugShowPostCode POSTCODE_32BIT_MODE\r
-\r
- mov ax, LINEAR_SEL\r
- mov ds, ax\r
- mov es, ax\r
- mov fs, ax\r
- mov gs, ax\r
- mov ss, ax\r
-\r
- OneTimeCallRet TransitionFromReal16To32BitFlat\r
-\r
-ALIGN 2\r
-\r
-gdtr:\r
- dw GDT_END - GDT_BASE - 1 ; GDT limit\r
- dd ADDR_OF(GDT_BASE)\r
-\r
-ALIGN 16\r
-\r
-;\r
-; Macros for GDT entries\r
-;\r
-\r
-%define PRESENT_FLAG(p) (p << 7)\r
-%define DPL(dpl) (dpl << 5)\r
-%define SYSTEM_FLAG(s) (s << 4)\r
-%define DESC_TYPE(t) (t)\r
-\r
-; Type: data, expand-up, writable, accessed\r
-%define DATA32_TYPE 3\r
-\r
-; Type: execute, readable, expand-up, accessed\r
-%define CODE32_TYPE 0xb\r
-\r
-; Type: execute, readable, expand-up, accessed\r
-%define CODE64_TYPE 0xb\r
-\r
-%define GRANULARITY_FLAG(g) (g << 7)\r
-%define DEFAULT_SIZE32(d) (d << 6)\r
-%define CODE64_FLAG(l) (l << 5)\r
-%define UPPER_LIMIT(l) (l)\r
-\r
-;\r
-; The Global Descriptor Table (GDT)\r
-;\r
-\r
-GDT_BASE:\r
-; null descriptor\r
-NULL_SEL equ $-GDT_BASE\r
- DW 0 ; limit 15:0\r
- DW 0 ; base 15:0\r
- DB 0 ; base 23:16\r
- DB 0 ; sys flag, dpl, type\r
- DB 0 ; limit 19:16, flags\r
- DB 0 ; base 31:24\r
-\r
-; linear data segment descriptor\r
-LINEAR_SEL equ $-GDT_BASE\r
- DW 0xffff ; limit 15:0\r
- DW 0 ; base 15:0\r
- DB 0 ; base 23:16\r
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE)\r
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)\r
- DB 0 ; base 31:24\r
-\r
-; linear code segment descriptor\r
-LINEAR_CODE_SEL equ $-GDT_BASE\r
- DW 0xffff ; limit 15:0\r
- DW 0 ; base 15:0\r
- DB 0 ; base 23:16\r
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE)\r
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf)\r
- DB 0 ; base 31:24\r
-\r
-%ifdef ARCH_X64\r
-; linear code (64-bit) segment descriptor\r
-LINEAR_CODE64_SEL equ $-GDT_BASE\r
- DW 0xffff ; limit 15:0\r
- DW 0 ; base 15:0\r
- DB 0 ; base 23:16\r
- DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE)\r
- DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf)\r
- DB 0 ; base 31:24\r
-%endif\r
-\r
-GDT_END:\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; 16-bit initialization code\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-\r
-BITS 16\r
-\r
-;\r
-; @param[out] DI 'BP' to indicate boot-strap processor\r
-;\r
-EarlyBspInitReal16:\r
- mov di, 'BP'\r
- jmp short Main16\r
-\r
-;\r
-; @param[out] DI 'AP' to indicate application processor\r
-;\r
-EarlyApInitReal16:\r
- mov di, 'AP'\r
- jmp short Main16\r
-\r
-;\r
-; Modified: EAX\r
-;\r
-; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)\r
-; @param[out] ESP Initial value of the EAX register (BIST: Built-in Self Test)\r
-;\r
-EarlyInit16:\r
- ;\r
- ; ESP - Initial value of the EAX register (BIST: Built-in Self Test)\r
- ;\r
- mov esp, eax\r
-\r
- debugInitialize\r
-\r
- OneTimeCallRet EarlyInit16\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; First code exectuted by processor after resetting.\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 16\r
-\r
-ALIGN 16\r
-\r
-applicationProcessorEntryPoint:\r
-;\r
-; Application Processors entry point\r
-;\r
-; GenFv generates code aligned on a 4k boundary which will jump to this\r
-; location. (0xffffffe0) This allows the Local APIC Startup IPI to be\r
-; used to wake up the application processors.\r
-;\r
- jmp short EarlyApInitReal16\r
-\r
-ALIGN 8\r
-\r
- DD 0\r
-\r
-;\r
-; The VTF signature\r
-;\r
-; VTF-0 means that the VTF (Volume Top File) code does not require\r
-; any fixups.\r
-;\r
-vtfSignature:\r
- DB 'V', 'T', 'F', 0\r
-\r
-ALIGN 16\r
-\r
-resetVector:\r
-;\r
-; Reset Vector\r
-;\r
-; This is where the processor will begin execution\r
-;\r
- wbinvd\r
- jmp short EarlyBspInitReal16\r
-\r
-ALIGN 16\r
-\r
-fourGigabytes:\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Transition from 32 bit flat protected mode into 64 bit flat protected mode\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 32\r
-\r
-;\r
-; Modified: EAX\r
-;\r
-Transition32FlatTo64Flat:\r
-\r
- mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)\r
- mov cr3, eax\r
-\r
- mov eax, cr4\r
- bts eax, 5 ; enable PAE\r
- mov cr4, eax \r
-\r
- mov ecx, 0xc0000080\r
- rdmsr\r
- bts eax, 8 ; set LME\r
- wrmsr\r
-\r
- mov eax, cr0\r
- bts eax, 31 ; set PG\r
- mov cr0, eax ; enable paging\r
-\r
- jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)\r
-BITS 64\r
-jumpTo64BitAndLandHere:\r
-\r
- debugShowPostCode POSTCODE_64BIT_MODE\r
-\r
- OneTimeCallRet Transition32FlatTo64Flat\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Search for the Boot Firmware Volume (BFV) base address\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \\r
-; { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }\r
-%define FFS_GUID_DWORD0 0x8c8ce578\r
-%define FFS_GUID_DWORD1 0x4f1c8a3d\r
-%define FFS_GUID_DWORD2 0x61893599\r
-%define FFS_GUID_DWORD3 0xd32dc385\r
-\r
-BITS 32\r
-\r
-;\r
-; Modified: EAX, EBX\r
-; Preserved: EDI, ESP\r
-;\r
-; @param[out] EBP Address of Boot Firmware Volume (BFV)\r
-;\r
-Flat32SearchForBfvBase:\r
-\r
- xor eax, eax\r
-searchingForBfvHeaderLoop:\r
- ;\r
- ; We check for a firmware volume at every 4KB address in the top 16MB\r
- ; just below 4GB. (Addresses at 0xffHHH000 where H is any hex digit.)\r
- ;\r
- sub eax, 0x1000\r
- cmp eax, 0xff000000\r
- jb searchedForBfvHeaderButNotFound\r
-\r
- ;\r
- ; Check FFS GUID\r
- ;\r
- cmp dword [eax + 0x10], FFS_GUID_DWORD0\r
- jne searchingForBfvHeaderLoop\r
- cmp dword [eax + 0x14], FFS_GUID_DWORD1\r
- jne searchingForBfvHeaderLoop\r
- cmp dword [eax + 0x18], FFS_GUID_DWORD2\r
- jne searchingForBfvHeaderLoop\r
- cmp dword [eax + 0x1c], FFS_GUID_DWORD3\r
- jne searchingForBfvHeaderLoop\r
-\r
- ;\r
- ; Check FV Length\r
- ;\r
- cmp dword [eax + 0x24], 0\r
- jne searchingForBfvHeaderLoop\r
- mov ebx, eax\r
- add ebx, dword [eax + 0x20]\r
- jnz searchingForBfvHeaderLoop\r
-\r
- jmp searchedForBfvHeaderAndItWasFound\r
-\r
-searchedForBfvHeaderButNotFound:\r
- ;\r
- ; Hang if the SEC entry point was not found\r
- ;\r
- debugShowPostCode POSTCODE_BFV_NOT_FOUND\r
-\r
- ;\r
- ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed\r
- ; for debugging purposes.\r
- ;\r
- mov eax, 0xBFBFBFBF\r
- mov ebp, eax\r
- jmp $\r
-\r
-searchedForBfvHeaderAndItWasFound:\r
- mov ebp, eax\r
-\r
- debugShowPostCode POSTCODE_BFV_FOUND\r
-\r
- OneTimeCallRet Flat32SearchForBfvBase\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Search for the SEC Core entry point\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 32\r
-\r
-%define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
-\r
-;\r
-; Modified: EAX, EBX, ECX, EDX\r
-; Preserved: EDI, EBP, ESP\r
-;\r
-; @param[in] EBP Address of Boot Firmware Volume (BFV)\r
-; @param[out] ESI SEC Core Entry Point Address\r
-;\r
-Flat32SearchForSecEntryPoint:\r
-\r
- ;\r
- ; Initialize EBP and ESI to 0\r
- ;\r
- xor ebx, ebx\r
- mov esi, ebx\r
-\r
- ;\r
- ; Pass over the BFV header\r
- ;\r
- mov eax, ebp\r
- mov bx, [ebp + 0x30]\r
- add eax, ebx\r
- jc secEntryPointWasNotFound\r
-\r
- jmp searchingForFfsFileHeaderLoop\r
-\r
-moveForwardWhileSearchingForFfsFileHeaderLoop:\r
- ;\r
- ; Make forward progress in the search\r
- ;\r
- inc eax\r
- jc secEntryPointWasNotFound\r
-\r
-searchingForFfsFileHeaderLoop:\r
- test eax, eax\r
- jz secEntryPointWasNotFound\r
-\r
- ;\r
- ; Ensure 8 byte alignment\r
- ;\r
- add eax, 7\r
- jc secEntryPointWasNotFound\r
- and al, 0xf8\r
-\r
- ;\r
- ; Look to see if there is an FFS file at eax\r
- ;\r
- mov bl, [eax + 0x17]\r
- test bl, 0x20\r
- jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
- mov ecx, [eax + 0x14]\r
- and ecx, 0x00ffffff\r
- or ecx, ecx\r
- jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
- add ecx, eax\r
- jz jumpSinceWeFoundTheLastFfsFile\r
- jc moveForwardWhileSearchingForFfsFileHeaderLoop\r
-jumpSinceWeFoundTheLastFfsFile:\r
-\r
- ;\r
- ; There seems to be a valid file at eax\r
- ;\r
- cmp byte [eax + 0x12], EFI_FV_FILETYPE_SECURITY_CORE ; Check File Type\r
- jne readyToTryFfsFileAtEcx\r
-\r
-fileTypeIsSecCore:\r
- OneTimeCall GetEntryPointOfFfsFile\r
- test eax, eax\r
- jnz doneSeachingForSecEntryPoint\r
-\r
-readyToTryFfsFileAtEcx:\r
- ;\r
- ; Try the next FFS file at ECX\r
- ;\r
- mov eax, ecx\r
- jmp searchingForFfsFileHeaderLoop\r
-\r
-secEntryPointWasNotFound:\r
- xor eax, eax\r
-\r
-doneSeachingForSecEntryPoint:\r
- mov esi, eax\r
-\r
- test esi, esi\r
- jnz secCoreEntryPointWasFound\r
-\r
-secCoreEntryPointWasNotFound:\r
- ;\r
- ; Hang if the SEC entry point was not found\r
- ;\r
- debugShowPostCode POSTCODE_SEC_NOT_FOUND\r
- jz $\r
-\r
-secCoreEntryPointWasFound:\r
- debugShowPostCode POSTCODE_SEC_FOUND\r
-\r
- OneTimeCallRet Flat32SearchForSecEntryPoint\r
-\r
-%define EFI_SECTION_PE32 0x10\r
-\r
-;\r
-; Input:\r
-; EAX - Start of FFS file\r
-; ECX - End of FFS file\r
-;\r
-; Output:\r
-; EAX - Entry point of PE32 (or 0 if not found)\r
-;\r
-; Modified:\r
-; EBX\r
-;\r
-GetEntryPointOfFfsFile:\r
- test eax, eax\r
- jz getEntryPointOfFfsFileErrorReturn\r
- add eax, 0x18 ; EAX = Start of section\r
-\r
-getEntryPointOfFfsFileLoopForSections:\r
- cmp eax, ecx\r
- jae getEntryPointOfFfsFileErrorReturn\r
-\r
- cmp byte [eax + 3], EFI_SECTION_PE32\r
- je getEntryPointOfFfsFileFoundPe32Section\r
-\r
- ;\r
- ; The section type was not PE32, so move to next section\r
- ;\r
- mov ebx, dword [eax]\r
- and ebx, 0x00ffffff\r
- add eax, ebx\r
- jc getEntryPointOfFfsFileErrorReturn\r
-\r
- ;\r
- ; Ensure that FFS section is 32-bit aligned\r
- ;\r
- add eax, 3\r
- jc getEntryPointOfFfsFileErrorReturn\r
- and al, 0xfc\r
- jmp getEntryPointOfFfsFileLoopForSections\r
-\r
-getEntryPointOfFfsFileFoundPe32Section:\r
- add eax, 4 ; EAX = Start of PE32 image\r
-\r
- mov ebx, eax\r
- cmp word [eax], 'MZ'\r
- jne thereIsNotAnMzSignature\r
- movzx ebx, word [eax + 0x3c]\r
- add ebx, eax\r
-thereIsNotAnMzSignature:\r
-\r
- ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)\r
- cmp word [ebx], 'VZ'\r
- jne thereIsNoVzSignature\r
- ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
- ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +\r
- ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
- add eax, [ebx + 0x8]\r
- add eax, 0x28\r
- movzx ebx, word [ebx + 0x6]\r
- sub eax, ebx\r
- jmp getEntryPointOfFfsFileReturn\r
-\r
-thereIsNoVzSignature:\r
-\r
- ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)\r
- cmp dword [ebx], `PE\x00\x00`\r
- jne getEntryPointOfFfsFileErrorReturn\r
-\r
- ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
- ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));\r
- add eax, [ebx + 0x4 + 0x14 + 0x10]\r
- jmp getEntryPointOfFfsFileReturn\r
-\r
-getEntryPointOfFfsFileErrorReturn:\r
- mov eax, 0\r
-\r
-getEntryPointOfFfsFileReturn:\r
- OneTimeCallRet GetEntryPointOfFfsFile\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Main routine of the pre-SEC code up through the jump into SEC\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-\r
-BITS 16\r
-\r
-;\r
-; Modified: EBX, ECX, EDX, EBP\r
-;\r
-; @param[in,out] RAX/EAX Initial value of the EAX register\r
-; (BIST: Built-in Self Test)\r
-; @param[in,out] DI 'BP': boot-strap processor, or\r
-; 'AP': application processor\r
-; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV)\r
-;\r
-; @return None This routine jumps to SEC and does not return\r
-;\r
-Main16:\r
- OneTimeCall EarlyInit16\r
-\r
- ;\r
- ; Transition the processor from 16-bit real mode to 32-bit flat mode\r
- ;\r
- OneTimeCall TransitionFromReal16To32BitFlat\r
-\r
-BITS 32\r
-\r
- ;\r
- ; Search for the Boot Firmware Volume (BFV)\r
- ;\r
- OneTimeCall Flat32SearchForBfvBase\r
-\r
- ;\r
- ; EBP - Start of BFV\r
- ;\r
-\r
- ;\r
- ; Search for the SEC entry point\r
- ;\r
- OneTimeCall Flat32SearchForSecEntryPoint\r
-\r
- ;\r
- ; ESI - SEC Core entry point\r
- ; EBP - Start of BFV\r
- ;\r
-\r
-%ifdef ARCH_IA32\r
-\r
- ;\r
- ; Restore initial EAX value into the EAX register\r
- ;\r
- mov eax, esp\r
-\r
- ;\r
- ; Jump to the 32-bit SEC entry point\r
- ;\r
- jmp esi\r
-\r
-%else\r
-\r
- ;\r
- ; Transition the processor from 32-bit flat mode to 64-bit flat mode\r
- ;\r
- OneTimeCall Transition32FlatTo64Flat\r
-\r
-BITS 64\r
-\r
- ;\r
- ; Some values were calculated in 32-bit mode. Make sure the upper\r
- ; 32-bits of 64-bit registers are zero for these values.\r
- ;\r
- mov rax, 0x00000000ffffffff\r
- and rsi, rax\r
- and rbp, rax\r
- and rsp, rax\r
-\r
- ;\r
- ; RSI - SEC Core entry point\r
- ; RBP - Start of BFV\r
- ;\r
-\r
- ;\r
- ; Restore initial EAX value into the RAX register\r
- ;\r
- mov rax, rsp\r
-\r
- ;\r
- ; Jump to the 64-bit SEC entry point\r
- ;\r
- jmp rsi\r
-\r
-%endif\r
-\r
-\r
+++ /dev/null
-## @file
-# Makefile to create FFS Raw sections for VTF images.
-#
-# Copyright (c) 2008, Intel Corporation
-#
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-TARGETS = Bin/ResetVector.ia32.raw Bin/ResetVector.x64.raw
-ASM = nasm
-
-COMMON_DEPS = \
- Ia16/16RealTo32Flat.asm \
- Ia32/32FlatTo64Flat.asm \
- JumpToSec.asm \
- Ia16/ResetVectorVtf0.asm \
- Ia32/SearchForBfvBase.asm \
- Ia32/SearchForSecAndPeiEntries.asm \
- SerialDebug.asm \
- Makefile \
- Tools/FixupForRawSection.py
-
-.PHONY: all
-all: $(TARGETS)
-
-Bin/ResetVector.ia32.raw: $(COMMON_DEPS) ResetVectorCode.asm
- nasm -D ARCH_IA32 -o $@ ResetVectorCode.asm
- python Tools/FixupForRawSection.py $@
-
-Bin/ResetVector.x64.raw: $(COMMON_DEPS) ResetVectorCode.asm
- nasm -D ARCH_X64 -o $@ ResetVectorCode.asm
- python Tools/FixupForRawSection.py $@
-
-clean:
- -rm $(TARGETS)
-
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Port 0x80 debug support macros\r
-;\r
-; Copyright (c) 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-BITS 16\r
-\r
-%macro debugInitialize 0\r
- ;\r
- ; No initialization is required\r
- ;\r
-%endmacro\r
-\r
-%macro debugShowPostCode 1\r
- mov al, %1\r
- out 0x80, al\r
-%endmacro\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Definitions of POST CODES for the reset vector module\r
-;\r
-; Copyright (c) 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-%define POSTCODE_16BIT_MODE 0x16\r
-%define POSTCODE_32BIT_MODE 0x32\r
-%define POSTCODE_64BIT_MODE 0x64\r
-\r
-%define POSTCODE_BFV_NOT_FOUND 0xb0\r
-%define POSTCODE_BFV_FOUND 0xb1\r
-\r
-%define POSTCODE_SEC_NOT_FOUND 0xf0\r
-%define POSTCODE_SEC_FOUND 0xf1\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; This file includes all other code files to assemble the reset vector code\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-%ifdef ARCH_IA32\r
- %ifdef ARCH_X64\r
- %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."\r
- %endif\r
-%elifdef ARCH_X64\r
-%else\r
- %error "Either ARCH_IA32 or ARCH_X64 must be defined."\r
-%endif\r
-\r
-%include "CommonMacros.inc"\r
-\r
-%include "PostCodes.inc"\r
-\r
-%ifdef DEBUG_NONE\r
- %include "DebugDisabled.asm"\r
-%elifdef DEBUG_PORT80\r
- %include "Port80Debug.asm"\r
-%elifdef DEBUG_SERIAL\r
- %include "SerialDebug.asm"\r
-%else\r
- %error "No debug type was specified."\r
-%endif\r
-\r
-%include "Ia32/SearchForBfvBase.asm"\r
-%include "Ia32/SearchForSecEntry.asm"\r
-\r
-%ifdef ARCH_X64\r
-%include "Ia32/32FlatTo64Flat.asm"\r
-%endif\r
-\r
-%include "Ia16/16RealTo32Flat.asm"\r
-%include "Ia16/Init16.asm"\r
-\r
-%include "Main.asm"\r
-\r
-%include "Ia16/ResetVectorVtf0.asm"\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------\r
-; @file\r
-; Serial port debug support macros\r
-;\r
-; Copyright (c) 2008 - 2009, Intel Corporation\r
-; All rights reserved. This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-;//---------------------------------------------\r
-;// UART Register Offsets\r
-;//---------------------------------------------\r
-%define BAUD_LOW_OFFSET 0x00\r
-%define BAUD_HIGH_OFFSET 0x01\r
-%define IER_OFFSET 0x01\r
-%define LCR_SHADOW_OFFSET 0x01\r
-%define FCR_SHADOW_OFFSET 0x02\r
-%define IR_CONTROL_OFFSET 0x02\r
-%define FCR_OFFSET 0x02\r
-%define EIR_OFFSET 0x02\r
-%define BSR_OFFSET 0x03\r
-%define LCR_OFFSET 0x03\r
-%define MCR_OFFSET 0x04\r
-%define LSR_OFFSET 0x05\r
-%define MSR_OFFSET 0x06\r
-\r
-;//---------------------------------------------\r
-;// UART Register Bit Defines\r
-;//---------------------------------------------\r
-%define LSR_TXRDY 0x20\r
-%define LSR_RXDA 0x01\r
-%define DLAB 0x01\r
-\r
-; UINT16 gComBase = 0x3f8;\r
-; UINTN gBps = 115200;\r
-; UINT8 gData = 8;\r
-; UINT8 gStop = 1;\r
-; UINT8 gParity = 0;\r
-; UINT8 gBreakSet = 0;\r
-\r
-%define DEFAULT_COM_BASE 0x3f8\r
-%define DEFAULT_BPS 115200\r
-%define DEFAULT_DATA 8\r
-%define DEFAULT_STOP 1\r
-%define DEFAULT_PARITY 0\r
-%define DEFAULT_BREAK_SET 0\r
-\r
-%define SERIAL_DEFAULT_LCR ( \\r
- (DEFAULT_BREAK_SET << 6) | \\r
- (DEFAULT_PARITY << 3) | \\r
- (DEFAULT_STOP << 2) | \\r
- (DEFAULT_DATA - 5) \\r
- )\r
-\r
-%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE\r
-\r
-%macro inFromSerialPort 1\r
- mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
- in al, dx\r
-%endmacro\r
-\r
-%macro waitForSerialTxReady 0\r
-\r
-%%waitingForTx:\r
- inFromSerialPort LSR_OFFSET\r
- test al, LSR_TXRDY\r
- jz %%waitingForTx\r
-\r
-%endmacro\r
-\r
-%macro outToSerialPort 2\r
- mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
- mov al, %2\r
- out dx, al\r
-%endmacro\r
-\r
-%macro debugShowCharacter 1\r
- waitForSerialTxReady\r
- outToSerialPort 0, %1\r
-%endmacro\r
-\r
-%macro debugShowHexDigit 1\r
- %if (%1 < 0xa)\r
- debugShowCharacter BYTE ('0' + (%1))\r
- %else\r
- debugShowCharacter BYTE ('a' + ((%1) - 0xa))\r
- %endif\r
-%endmacro\r
-\r
-%macro debugNewline 0\r
- debugShowCharacter `\r`\r
- debugShowCharacter `\n`\r
-%endmacro\r
-\r
-%macro debugShowPostCode 1\r
- debugShowHexDigit (((%1) >> 4) & 0xf)\r
- debugShowHexDigit ((%1) & 0xf)\r
- debugNewline\r
-%endmacro\r
-\r
-BITS 16\r
-\r
-%macro debugInitialize 0\r
- jmp real16InitDebug\r
-real16InitDebugReturn:\r
-%endmacro\r
-\r
-real16InitDebug:\r
- ;\r
- ; Set communications format\r
- ;\r
- outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)\r
-\r
- ;\r
- ; Configure baud rate\r
- ;\r
- outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)\r
- outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)\r
-\r
- ;\r
- ; Switch back to bank 0\r
- ;\r
- outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r
-\r
- jmp real16InitDebugReturn\r
-\r
+++ /dev/null
-## @file
-# Apply fixup to VTF binary image for FFS Raw section
-#
-# Copyright (c) 2008, Intel Corporation
-#
-# All rights reserved. This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-
-import sys
-
-filename = sys.argv[1]
-
-if filename.lower().find('ia32') >= 0:
- d = open(sys.argv[1], 'rb').read()
- c = ((len(d) + 4 + 7) & ~7) - 4
- if c > len(d):
- c -= len(d)
- f = open(sys.argv[1], 'wb')
- f.write('\x90' * c)
- f.write(d)
- f.close()
-else:
- from struct import pack
-
- PAGE_PRESENT = 0x01
- PAGE_READ_WRITE = 0x02
- PAGE_USER_SUPERVISOR = 0x04
- PAGE_WRITE_THROUGH = 0x08
- PAGE_CACHE_DISABLE = 0x010
- PAGE_ACCESSED = 0x020
- PAGE_DIRTY = 0x040
- PAGE_PAT = 0x080
- PAGE_GLOBAL = 0x0100
- PAGE_2M_MBO = 0x080
- PAGE_2M_PAT = 0x01000
-
- def NopAlign4k(s):
- c = ((len(s) + 0xfff) & ~0xfff) - len(s)
- return ('\x90' * c) + s
-
- def PageDirectoryEntries4GbOf2MbPages(baseAddress):
-
- s = ''
- for i in range(0x800):
- i = (
- baseAddress + long(i << 21) +
- PAGE_2M_MBO +
- PAGE_CACHE_DISABLE +
- PAGE_ACCESSED +
- PAGE_DIRTY +
- PAGE_READ_WRITE +
- PAGE_PRESENT
- )
- s += pack('Q', i)
- return s
-
- def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
- s = ''
- for i in range(0x200):
- i = (
- pdeBase +
- (min(i, 3) << 12) +
- PAGE_CACHE_DISABLE +
- PAGE_ACCESSED +
- PAGE_READ_WRITE +
- PAGE_PRESENT
- )
- s += pack('Q', i)
- return s
-
- def PageMapLevel4Table4GbOf2MbPages(pdptBase):
- s = ''
- for i in range(0x200):
- i = (
- pdptBase +
- (min(i, 0) << 12) +
- PAGE_CACHE_DISABLE +
- PAGE_ACCESSED +
- PAGE_READ_WRITE +
- PAGE_PRESENT
- )
- s += pack('Q', i)
- return s
-
- def First4GbPageEntries(topAddress):
- PDE = PageDirectoryEntries4GbOf2MbPages(0L)
- pml4tBase = topAddress - 0x1000
- pdptBase = pml4tBase - 0x1000
- pdeBase = pdptBase - len(PDE)
- PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
- PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
- return PDE + PDPT + PML4T
-
- def AlignAndAddPageTables():
- d = open(sys.argv[1], 'rb').read()
- code = NopAlign4k(d)
- topAddress = 0x100000000 - len(code)
- d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
- f = open(sys.argv[1], 'wb')
- f.write(d)
- f.close()
-
- AlignAndAddPageTables()
-
projects / mirror_edk2.git / commitdiff