ArmPlatformPkg: move PCI related PCD definitions to ArmPkg

The PCI related PCDs are not platform specific, and architectural
protocols such as CpuIo2 are based on PCI provided MMIO to IO
translation, so these PCDs belong in ArmPkg not ArmPlatformPkg.

NOTE: this *WILL* break some out-of-tree platforms, the fix is changing
all consumers of gArmPlatformTokenSpaceGuid.PcdPci* to
gArmTokenSpaceGuid.PcdPci*

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index e90306653864e0cb4ea7603ab4cc7078b7ecdb08..75c238aa1e3d580318b941dc4d2eb7cbcb537cc2 100644 (file)
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -255,3 +255,65 @@
   gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
   gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+  #\r
+  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+  # Note that "IO" is just another MMIO range that simulates IO space; there\r
+  # are no special instructions to access it.\r
+  #\r
+  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+  # specific to their containing address spaces. In order to get the physical\r
+  # address for the CPU, for a given access, the respective translation value\r
+  # has to be added.\r
+  #\r
+  # The translations always have to be initialized like this, using UINT64:\r
+  #\r
+  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
+  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+  #\r
+  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
+  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+  #\r
+  # because (a) the target address space (ie. the cpu-physical space) is\r
+  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+  # arithmetic.\r
+  #\r
+  # Accordingly, the translation itself needs to be implemented as:\r
+  #\r
+  #   UINT64 UntranslatedIoAddress;     // input parameter\r
+  #   UINT32 UntranslatedMmio32Address; // input parameter\r
+  #   UINT64 UntranslatedMmio64Address; // input parameter\r
+  #\r
+  #   UINT64 TranslatedIoAddress;       // output parameter\r
+  #   UINT64 TranslatedMmio32Address;   // output parameter\r
+  #   UINT64 TranslatedMmio64Address;   // output parameter\r
+  #\r
+  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
+  #                             PcdPciIoTranslation;\r
+  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+  #                             PcdPciMmio32Translation;\r
+  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
+  #                             PcdPciMmio64Translation;\r
+  #\r
+  #  The modular arithmetic performed in UINT64 ensures that the translation\r
+  #  works correctly regardless of the relation between IoCpuBase and\r
+  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+  #  PcdPciMmio64Base.\r
+  #\r
+  gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+  gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+  gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+  gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+  gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+  gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+  gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+  gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+  gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+  #\r
+  # Inclusive range of allowed PCI buses.\r
+  #\r
+  gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+  gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r

diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
index 6ab81e8dd60a6fdf6cf0795306510ac992ec84c8..a2617982b259c06226be82a38577778ab66a0583 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
@@ -80,8 +80,8 @@
 \r
   # PCI Root complex specific PCDs\r
   gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress\r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
+  gArmTokenSpaceGuid.PcdPciBusMin\r
+  gArmTokenSpaceGuid.PcdPciBusMax\r
 \r
 [Pcd]\r
   gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths\r

diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
index 9f526910c48ac696045d4cee0537fe55a2009599..de28c805ae6e1f90e51cc0118745bcfc11c44186 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
@@ -58,14 +58,14 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase\r
   gArmTokenSpaceGuid.PcdSystemMemorySize\r
 \r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMin\r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMax\r
-  gArmPlatformTokenSpaceGuid.PcdPciIoBase\r
-  gArmPlatformTokenSpaceGuid.PcdPciIoSize\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size\r
+  gArmTokenSpaceGuid.PcdPciBusMin\r
+  gArmTokenSpaceGuid.PcdPciBusMax\r
+  gArmTokenSpaceGuid.PcdPciIoBase\r
+  gArmTokenSpaceGuid.PcdPciIoSize\r
+  gArmTokenSpaceGuid.PcdPciMmio32Base\r
+  gArmTokenSpaceGuid.PcdPciMmio32Size\r
+  gArmTokenSpaceGuid.PcdPciMmio64Base\r
+  gArmTokenSpaceGuid.PcdPciMmio64Size\r
 \r
   gArmJunoTokenSpaceGuid.PcdPcieControlBaseAddress\r
   gArmJunoTokenSpaceGuid.PcdPcieRootPortBaseAddress\r

diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
index 530bb1cb9dc0655f8768fe22e932bdac5918963f..8c8b141c35a2693b618c1515cb665b9b1e81cc4e 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
+++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
@@ -58,10 +58,10 @@
   gArmJunoTokenSpaceGuid.PcdPciConfigurationSpaceSize\r
 \r
 [Pcd]\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size\r
+  gArmTokenSpaceGuid.PcdPciMmio32Base\r
+  gArmTokenSpaceGuid.PcdPciMmio32Size\r
+  gArmTokenSpaceGuid.PcdPciMmio64Base\r
+  gArmTokenSpaceGuid.PcdPciMmio64Size\r
 \r
 [Ppis]\r
   gArmMpCoreInfoPpiGuid\r

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 0a7e78443eff6211ed5652e871318a3984195bd8..1c05132cd625be75b0d9d1cd09950af983d1f049 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -125,68 +125,6 @@
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
 \r
-  #\r
-  # Inclusive range of allowed PCI buses.\r
-  #\r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E\r
-  gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F\r
-\r
-  #\r
-  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
-  # Note that "IO" is just another MMIO range that simulates IO space; there\r
-  # are no special instructions to access it.\r
-  #\r
-  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
-  # specific to their containing address spaces. In order to get the physical\r
-  # address for the CPU, for a given access, the respective translation value\r
-  # has to be added.\r
-  #\r
-  # The translations always have to be initialized like this, using UINT64:\r
-  #\r
-  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space\r
-  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
-  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
-  #\r
-  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;\r
-  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
-  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
-  #\r
-  # because (a) the target address space (ie. the cpu-physical space) is\r
-  # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
-  # arithmetic.\r
-  #\r
-  # Accordingly, the translation itself needs to be implemented as:\r
-  #\r
-  #   UINT64 UntranslatedIoAddress;     // input parameter\r
-  #   UINT32 UntranslatedMmio32Address; // input parameter\r
-  #   UINT64 UntranslatedMmio64Address; // input parameter\r
-  #\r
-  #   UINT64 TranslatedIoAddress;       // output parameter\r
-  #   UINT64 TranslatedMmio32Address;   // output parameter\r
-  #   UINT64 TranslatedMmio64Address;   // output parameter\r
-  #\r
-  #   TranslatedIoAddress     = UntranslatedIoAddress +\r
-  #                             PcdPciIoTranslation;\r
-  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
-  #                             PcdPciMmio32Translation;\r
-  #   TranslatedMmio64Address = UntranslatedMmio64Address +\r
-  #                             PcdPciMmio64Translation;\r
-  #\r
-  #  The modular arithmetic performed in UINT64 ensures that the translation\r
-  #  works correctly regardless of the relation between IoCpuBase and\r
-  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
-  #  PcdPciMmio64Base.\r
-  #\r
-  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040\r
-  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041\r
-  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047\r
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048\r
-\r
 [PcdsFixedAtBuild.ARM]\r
   # Stack for CPU Cores in Secure Monitor Mode\r
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r