ArmPkg/ArmPlatformPkg: position vectors relative to base

We currently rely on .align directives to ensure that each exception
vector entry is the appropriate offset from the vector base address.

This is slightly fragile, as were an entry to become too large (greater
than 32 A64 instructions), all following entries would be silently
shifted until they meet the next alignment boundary. Thus we might
execute the wrong code in response to an exception.

To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org
directives to position each entry at the precise required offset from
the base of a vector. A vector entry which is too large will trigger a
build failure rather than a runtime failure which is difficult to debug.

For consistency, the base and end of each vector is similarly annotated,
with VECTOR_BASE and VECTOR_END, which provide the necessary alignment
and symbol exports. The now redundant directives and labels are removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
index ca6c9a15229c0df4656e0dca6c43da1244f8034a..edf9973494922409a5bdf120eea1d1ea20e0b604 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
@@ -12,6 +12,7 @@
 //\r
 //------------------------------------------------------------------------------\r
 \r
+#include <Chipset/AArch64.h>\r
 #include <Library/PcdLib.h>\r
 #include <AsmMacroIoLibV8.h>\r
 \r
@@ -95,14 +96,12 @@
   UINT64  Padding;0x328   // Required for stack alignment\r
 */\r
 \r
-GCC_ASM_EXPORT(ExceptionHandlersStart)\r
 GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
 GCC_ASM_EXPORT(CommonExceptionEntry)\r
 GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
 GCC_ASM_EXPORT(CommonCExceptionHandler)\r
 \r
 .text\r
-.align 11\r
 \r
 #define GP_CONTEXT_SIZE    (32 *  8)\r
 #define FP_CONTEXT_SIZE    (32 * 16)\r
@@ -160,84 +159,85 @@ GCC_ASM_EXPORT(CommonCExceptionHandler)
 // This code gets copied to the ARM vector table\r
 // VectorTableStart - VectorTableEnd gets copied\r
 //\r
-ASM_PFX(ExceptionHandlersStart):\r
+VECTOR_BASE(ExceptionHandlersStart)\r
 \r
 //\r
 // Current EL with SP0 : 0x0 - 0x180\r
 //\r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SYNC)\r
 ASM_PFX(SynchronousExceptionSP0):\r
   b   ASM_PFX(SynchronousExceptionEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_IRQ)\r
 ASM_PFX(IrqSP0):\r
   b   ASM_PFX(IrqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_FIQ)\r
 ASM_PFX(FiqSP0):\r
   b   ASM_PFX(FiqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SP0_SERR)\r
 ASM_PFX(SErrorSP0):\r
   b   ASM_PFX(SErrorEntry)\r
 \r
 //\r
 // Current EL with SPx: 0x200 - 0x380\r
 //\r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)\r
 ASM_PFX(SynchronousExceptionSPx):\r
   b   ASM_PFX(SynchronousExceptionEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)\r
 ASM_PFX(IrqSPx):\r
   b   ASM_PFX(IrqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)\r
 ASM_PFX(FiqSPx):\r
   b   ASM_PFX(FiqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)\r
 ASM_PFX(SErrorSPx):\r
   b   ASM_PFX(SErrorEntry)\r
 \r
 //\r
 // Lower EL using AArch64 : 0x400 - 0x580\r
 //\r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SYNC)\r
 ASM_PFX(SynchronousExceptionA64):\r
   b   ASM_PFX(SynchronousExceptionEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_IRQ)\r
 ASM_PFX(IrqA64):\r
   b   ASM_PFX(IrqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_FIQ)\r
 ASM_PFX(FiqA64):\r
   b   ASM_PFX(FiqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A64_SERR)\r
 ASM_PFX(SErrorA64):\r
   b   ASM_PFX(SErrorEntry)\r
 \r
 //\r
-// Lower EL using AArch32 : 0x0 - 0x180\r
+// Lower EL using AArch32 : 0x600 - 0x780\r
 //\r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SYNC)\r
 ASM_PFX(SynchronousExceptionA32):\r
   b   ASM_PFX(SynchronousExceptionEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_IRQ)\r
 ASM_PFX(IrqA32):\r
   b   ASM_PFX(IrqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_FIQ)\r
 ASM_PFX(FiqA32):\r
   b   ASM_PFX(FiqEntry)\r
 \r
-.align 7\r
+VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_LOW_A32_SERR)\r
 ASM_PFX(SErrorA32):\r
   b   ASM_PFX(SErrorEntry)\r
 \r
+VECTOR_END(ExceptionHandlersStart)\r
 \r
 #undef  REG_PAIR\r
 #undef  REG_ONE\r

diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index f6a89012898cb652322735f5b0767b2549dd53bd..5e1653bcb69d987d5aab026521b573b1bdafa75f 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -97,6 +97,38 @@
 \r
 #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)\r
 \r
+// Vector table offset definitions\r
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000\r
+#define ARM_VECTOR_CUR_SP0_IRQ  0x080\r
+#define ARM_VECTOR_CUR_SP0_FIQ  0x100\r
+#define ARM_VECTOR_CUR_SP0_SERR 0x180\r
+\r
+#define ARM_VECTOR_CUR_SPx_SYNC 0x200\r
+#define ARM_VECTOR_CUR_SPx_IRQ  0x280\r
+#define ARM_VECTOR_CUR_SPx_FIQ  0x300\r
+#define ARM_VECTOR_CUR_SPx_SERR 0x380\r
+\r
+#define ARM_VECTOR_LOW_A64_SYNC 0x400\r
+#define ARM_VECTOR_LOW_A64_IRQ  0x480\r
+#define ARM_VECTOR_LOW_A64_FIQ  0x500\r
+#define ARM_VECTOR_LOW_A64_SERR 0x580\r
+\r
+#define ARM_VECTOR_LOW_A32_SYNC 0x600\r
+#define ARM_VECTOR_LOW_A32_IRQ  0x680\r
+#define ARM_VECTOR_LOW_A32_FIQ  0x700\r
+#define ARM_VECTOR_LOW_A32_SERR 0x780\r
+\r
+#define VECTOR_BASE(tbl)          \\r
+  .align 11;                      \\r
+  GCC_ASM_EXPORT(tbl);            \\r
+  ASM_PFX(tbl):                   \\r
+\r
+#define VECTOR_ENTRY(tbl, off)    \\r
+  .org ASM_PFX(tbl) + off\r
+\r
+#define VECTOR_END(tbl)           \\r
+  .org ASM_PFX(tbl) + 0x800\r
+\r
 VOID\r
 EFIAPI\r
 ArmEnableSWPInstruction (\r

diff --git a/ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAgentException.S b/ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAgentException.S
index 3fc090b2c3a63c6562658910906c7720c9f02150..f33a07a19badde501a1f750cae0e48d234d8e6e3 100644 (file)
--- a/ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAgentException.S
+++ b/ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAgentException.S
@@ -12,82 +12,85 @@
 #\r
 #------------------------------------------------------------------------------\r
 \r
-GCC_ASM_EXPORT(DebugAgentVectorTable)\r
+#include <Chipset/AArch64.h>\r
+\r
 GCC_ASM_IMPORT(DefaultExceptionHandler)\r
 \r
 .text\r
-.align 11\r
-ASM_PFX(DebugAgentVectorTable):\r
+VECTOR_BASE(DebugAgentVectorTable)\r
 \r
 //\r
 // Current EL with SP0 : 0x0 - 0x180\r
 //\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_SYNC)\r
 ASM_PFX(SynchronousExceptionSP0):\r
   b   ASM_PFX(SynchronousExceptionSP0)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_IRQ)\r
 ASM_PFX(IrqSP0):\r
   b   ASM_PFX(IrqSP0)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_FIQ)\r
 ASM_PFX(FiqSP0):\r
   b   ASM_PFX(FiqSP0)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_SERR)\r
 ASM_PFX(SErrorSP0):\r
   b   ASM_PFX(SErrorSP0)\r
 \r
 //\r
 // Current EL with SPx: 0x200 - 0x380\r
 //\r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_SYNC)\r
 ASM_PFX(SynchronousExceptionSPx):\r
   b   ASM_PFX(SynchronousExceptionSPx)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_IRQ)\r
 ASM_PFX(IrqSPx):\r
   b   ASM_PFX(IrqSPx)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_FIQ)\r
 ASM_PFX(FiqSPx):\r
   b   ASM_PFX(FiqSPx)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_SERR)\r
 ASM_PFX(SErrorSPx):\r
   b   ASM_PFX(SErrorSPx)\r
 \r
 /* Lower EL using AArch64 : 0x400 - 0x580 */\r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_SYNC)\r
 ASM_PFX(SynchronousExceptionA64):\r
   b   ASM_PFX(SynchronousExceptionA64)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_IRQ)\r
 ASM_PFX(IrqA64):\r
   b   ASM_PFX(IrqA64)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_FIQ)\r
 ASM_PFX(FiqA64):\r
   b   ASM_PFX(FiqA64)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_SERR)\r
 ASM_PFX(SErrorA64):\r
   b   ASM_PFX(SErrorA64)\r
 \r
 //\r
-// Lower EL using AArch32 : 0x0 - 0x180\r
+// Lower EL using AArch32 : 0x600 - 0x780\r
 //\r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_SYNC)\r
 ASM_PFX(SynchronousExceptionA32):\r
   b   ASM_PFX(SynchronousExceptionA32)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_IRQ)\r
 ASM_PFX(IrqA32):\r
   b   ASM_PFX(IrqA32)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_FIQ)\r
 ASM_PFX(FiqA32):\r
   b   ASM_PFX(FiqA32)\r
 \r
-.align 7\r
+VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_SERR)\r
 ASM_PFX(SErrorA32):\r
   b   ASM_PFX(SErrorA32)\r
+\r
+VECTOR_END(DebugAgentVectorTable)\r

diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
index cdc8d925bc69f370c368778310cec71c497e85d2..b31854ced256c896716fcb4b48d0c289b2a73022 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
+++ b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S
@@ -11,22 +11,17 @@
 #\r
 #\r
 \r
+#include <Chipset/AArch64.h>\r
 #include <AsmMacroIoLibV8.h>\r
 #include <Base.h>\r
 #include <AutoGen.h>\r
 \r
 .text\r
-.align 11\r
-\r
-GCC_ASM_EXPORT(PeiVectorTable)\r
 \r
 //============================================================\r
 //Default Exception Handlers\r
 //============================================================\r
 \r
-ASM_PFX(PeiVectorTable):\r
-\r
-\r
 #define TO_HANDLER                                              \\r
    EL1_OR_EL2(x1)                                               \\r
 1: mrs  x1, elr_el1    /* EL1 Exception Link Register */       ;\\r
@@ -40,42 +35,46 @@ ASM_PFX(PeiVectorTable):
 // No context saving at all.\r
 //\r
 \r
-.align 7\r
+VECTOR_BASE(PeiVectorTable)\r
+\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)\r
 _DefaultSyncExceptHandler_t:\r
   mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)\r
 _DefaultIrq_t:\r
   mov  x0, #EXCEPT_AARCH64_IRQ\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)\r
 _DefaultFiq_t:\r
   mov  x0, #EXCEPT_AARCH64_FIQ\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)\r
 _DefaultSError_t:\r
   mov  x0, #EXCEPT_AARCH64_SERROR\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)\r
 _DefaultSyncExceptHandler_h:\r
   mov  x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)\r
 _DefaultIrq_h:\r
   mov  x0, #EXCEPT_AARCH64_IRQ\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)\r
 _DefaultFiq_h:\r
   mov  x0, #EXCEPT_AARCH64_FIQ\r
   TO_HANDLER\r
 \r
-.align 7\r
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)\r
 _DefaultSError_h:\r
   mov  x0, #EXCEPT_AARCH64_SERROR\r
   TO_HANDLER\r
+\r
+VECTOR_END(PeiVectorTable)\r