Add assembly code for AP reset vector and the definition of MP_CPU_EXCHANGE_INFO
that are used to exchange the data between C code and assembly code when AP wake
up.
v4:
1. Copy MP_CPU_EXCHANGE_INFO from UefiCpuPkg/CpuMpPei/CpuMpPei.h
2. Copy MpEqu.inc and MpFuncs.nasm from UefiCpuPkg/CpuMpPei.
v3:
1. Rename NumApsExecutingLoction to NumApsExecutingLocation
2. Add whitespace after ; in .nasm file
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
# VALID_ARCHITECTURES = IA32 X64\r
#\r
\r
+[Sources.IA32]\r
+ Ia32/MpEqu.inc\r
+ Ia32/MpFuncs.nasm\r
+\r
+[Sources.X64]\r
+ X64/MpEqu.inc\r
+ X64/MpFuncs.nasm\r
+\r
[Sources.common]\r
DxeMpLib.c\r
MpLib.c\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; MpEqu.inc\r
+;\r
+; Abstract:\r
+;\r
+; This is the equates file for Multiple Processor support\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+VacantFlag equ 00h\r
+NotVacantFlag equ 0ffh\r
+\r
+CPU_SWITCH_STATE_IDLE equ 0\r
+CPU_SWITCH_STATE_STORED equ 1\r
+CPU_SWITCH_STATE_LOADED equ 2\r
+\r
+LockLocation equ (RendezvousFunnelProcEnd - RendezvousFunnelProcStart)\r
+StackStartAddressLocation equ LockLocation + 04h\r
+StackSizeLocation equ LockLocation + 08h\r
+ApProcedureLocation equ LockLocation + 0Ch\r
+GdtrLocation equ LockLocation + 10h\r
+IdtrLocation equ LockLocation + 16h\r
+BufferStartLocation equ LockLocation + 1Ch\r
+ModeOffsetLocation equ LockLocation + 20h\r
+NumApsExecutingLoction equ LockLocation + 24h\r
+CodeSegmentLocation equ LockLocation + 28h\r
+DataSegmentLocation equ LockLocation + 2Ch\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; MpFuncs.nasm\r
+;\r
+; Abstract:\r
+;\r
+; This is the assembly code for MP support\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+%include "MpEqu.inc"\r
+extern ASM_PFX(InitializeFloatingPointUnits)\r
+\r
+SECTION .text\r
+\r
+;-------------------------------------------------------------------------------------\r
+;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
+;procedure serializes all the AP processors through an Init sequence. It must be\r
+;noted that APs arrive here very raw...ie: real mode, no stack.\r
+;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
+;IS IN MACHINE CODE.\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(RendezvousFunnelProc)\r
+ASM_PFX(RendezvousFunnelProc):\r
+RendezvousFunnelProcStart:\r
+; At this point CS = 0x(vv00) and ip= 0x0.\r
+BITS 16\r
+ mov ebp, eax ; save BIST information\r
+\r
+ mov ax, cs\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov ss, ax\r
+ xor ax, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+\r
+ mov si, BufferStartLocation\r
+ mov ebx, [si]\r
+\r
+ mov si, ModeOffsetLocation\r
+ mov eax, [si]\r
+ mov si, CodeSegmentLocation\r
+ mov edx, [si]\r
+ mov di, ax\r
+ sub di, 02h\r
+ mov [di], dx\r
+ sub di, 04h\r
+ add eax, ebx\r
+ mov [di],eax\r
+\r
+ mov si, DataSegmentLocation\r
+ mov edx, [si]\r
+\r
+ mov si, GdtrLocation\r
+o32 lgdt [cs:si]\r
+\r
+ mov si, IdtrLocation\r
+o32 lidt [cs:si]\r
+\r
+ xor ax, ax\r
+ mov ds, ax\r
+\r
+ mov eax, cr0 ;Get control register 0\r
+ or eax, 000000003h ;Set PE bit (bit #0) & MP\r
+ mov cr0, eax\r
+\r
+ jmp 0:strict dword 0 ; far jump to protected mode\r
+BITS 32\r
+Flat32Start: ; protected mode entry point\r
+ mov ds, dx\r
+ mov es, dx\r
+ mov fs, dx\r
+ mov gs, dx\r
+ mov ss, dx\r
+\r
+ mov esi, ebx\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ mov eax, NotVacantFlag\r
+\r
+TestLock:\r
+ xchg [edi], eax\r
+ cmp eax, NotVacantFlag\r
+ jz TestLock\r
+\r
+ mov edi, esi\r
+ add edi, NumApsExecutingLoction\r
+ inc dword [edi]\r
+ mov ebx, [edi]\r
+\r
+ProgramStack:\r
+ mov edi, esi\r
+ add edi, StackSizeLocation\r
+ mov eax, [edi]\r
+ mov edi, esi\r
+ add edi, StackStartAddressLocation\r
+ add eax, [edi]\r
+ mov esp, eax\r
+ mov [edi], eax\r
+\r
+Releaselock:\r
+ mov eax, VacantFlag\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ xchg [edi], eax\r
+\r
+CProcedureInvoke:\r
+ push ebp ; push BIST data at top of AP stack\r
+ xor ebp, ebp ; clear ebp for call stack trace\r
+ push ebp\r
+ mov ebp, esp\r
+\r
+ mov eax, ASM_PFX(InitializeFloatingPointUnits)\r
+ call eax ; Call assembly function to initialize FPU per UEFI spec\r
+\r
+ push ebx ; Push NumApsExecuting\r
+ mov eax, esi\r
+ add eax, LockLocation\r
+ push eax ; push address of exchange info data buffer\r
+\r
+ mov edi, esi\r
+ add edi, ApProcedureLocation\r
+ mov eax, [edi]\r
+\r
+ call eax ; invoke C function\r
+\r
+ jmp $ ; never reach here\r
+RendezvousFunnelProcEnd:\r
+\r
+;-------------------------------------------------------------------------------------\r
+; AsmGetAddressMap (&AddressMap);\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(AsmGetAddressMap)\r
+ASM_PFX(AsmGetAddressMap):\r
+ pushad\r
+ mov ebp,esp\r
+\r
+ mov ebx, [ebp + 24h]\r
+ mov dword [ebx], RendezvousFunnelProcStart\r
+ mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart\r
+ mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
+\r
+ popad\r
+ ret\r
+\r
+;-------------------------------------------------------------------------------------\r
+;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
+;about to become an AP. It switches it'stack with the current AP.\r
+;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(AsmExchangeRole)\r
+ASM_PFX(AsmExchangeRole):\r
+ ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
+ ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
+ pushad\r
+ mov ebp,esp\r
+\r
+ ; esi contains MyInfo pointer\r
+ mov esi, [ebp + 24h]\r
+\r
+ ; edi contains OthersInfo pointer\r
+ mov edi, [ebp + 28h]\r
+\r
+ ;Store EFLAGS, GDTR and IDTR register to stack\r
+ pushfd\r
+ mov eax, cr4\r
+ push eax ; push cr4 firstly\r
+ mov eax, cr0\r
+ push eax\r
+\r
+ sgdt [esi + 8]\r
+ sidt [esi + 14]\r
+\r
+ ; Store the its StackPointer\r
+ mov [esi + 4],esp\r
+\r
+ ; update its switch state to STORED\r
+ mov byte [esi], CPU_SWITCH_STATE_STORED\r
+\r
+WaitForOtherStored:\r
+ ; wait until the other CPU finish storing its state\r
+ cmp byte [edi], CPU_SWITCH_STATE_STORED\r
+ jz OtherStored\r
+ pause\r
+ jmp WaitForOtherStored\r
+\r
+OtherStored:\r
+ ; Since another CPU already stored its state, load them\r
+ ; load GDTR value\r
+ lgdt [edi + 8]\r
+\r
+ ; load IDTR value\r
+ lidt [edi + 14]\r
+\r
+ ; load its future StackPointer\r
+ mov esp, [edi + 4]\r
+\r
+ ; update the other CPU's switch state to LOADED\r
+ mov byte [edi], CPU_SWITCH_STATE_LOADED\r
+\r
+WaitForOtherLoaded:\r
+ ; wait until the other CPU finish loading new state,\r
+ ; otherwise the data in stack may corrupt\r
+ cmp byte [esi], CPU_SWITCH_STATE_LOADED\r
+ jz OtherLoaded\r
+ pause\r
+ jmp WaitForOtherLoaded\r
+\r
+OtherLoaded:\r
+ ; since the other CPU already get the data it want, leave this procedure\r
+ pop eax\r
+ mov cr0, eax\r
+ pop eax\r
+ mov cr4, eax\r
+ popfd\r
+\r
+ popad\r
+ ret\r
#include <Library/HobLib.h>\r
\r
\r
+#pragma pack(1)\r
+\r
+//\r
+// MP CPU exchange information for AP reset code\r
+// This structure is required to be packed because fixed field offsets\r
+// into this structure are used in assembly code in this module\r
+//\r
+typedef struct {\r
+ UINTN Lock;\r
+ UINTN StackStart;\r
+ UINTN StackSize;\r
+ UINTN CFunction;\r
+ IA32_DESCRIPTOR GdtrProfile;\r
+ IA32_DESCRIPTOR IdtrProfile;\r
+ UINTN BufferStart;\r
+ UINTN ModeOffset;\r
+ UINTN NumApsExecuting;\r
+ UINTN CodeSegment;\r
+ UINTN DataSegment;\r
+ UINTN Cr3;\r
+ PEI_CPU_MP_DATA *PeiCpuMpData;\r
+} MP_CPU_EXCHANGE_INFO;\r
+\r
+#pragma pack()\r
#endif\r
\r
# VALID_ARCHITECTURES = IA32 X64\r
#\r
\r
+[Sources.IA32]\r
+ Ia32/MpEqu.inc\r
+ Ia32/MpFuncs.nasm\r
+\r
+[Sources.X64]\r
+ X64/MpEqu.inc\r
+ X64/MpFuncs.nasm\r
+\r
[Sources.common]\r
PeiMpLib.c\r
MpLib.c\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; MpEqu.inc\r
+;\r
+; Abstract:\r
+;\r
+; This is the equates file for Multiple Processor support\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+VacantFlag equ 00h\r
+NotVacantFlag equ 0ffh\r
+\r
+CPU_SWITCH_STATE_IDLE equ 0\r
+CPU_SWITCH_STATE_STORED equ 1\r
+CPU_SWITCH_STATE_LOADED equ 2\r
+\r
+LockLocation equ (RendezvousFunnelProcEnd - RendezvousFunnelProcStart)\r
+StackStartAddressLocation equ LockLocation + 08h\r
+StackSizeLocation equ LockLocation + 10h\r
+ApProcedureLocation equ LockLocation + 18h\r
+GdtrLocation equ LockLocation + 20h\r
+IdtrLocation equ LockLocation + 2Ah\r
+BufferStartLocation equ LockLocation + 34h\r
+ModeOffsetLocation equ LockLocation + 3Ch\r
+NumApsExecutingLoction equ LockLocation + 44h\r
+CodeSegmentLocation equ LockLocation + 4Ch\r
+DataSegmentLocation equ LockLocation + 54h\r
+Cr3Location equ LockLocation + 5Ch\r
+\r
+;-------------------------------------------------------------------------------\r
--- /dev/null
+;------------------------------------------------------------------------------ ;\r
+; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; MpFuncs.nasm\r
+;\r
+; Abstract:\r
+;\r
+; This is the assembly code for MP support\r
+;\r
+;-------------------------------------------------------------------------------\r
+\r
+%include "MpEqu.inc"\r
+extern ASM_PFX(InitializeFloatingPointUnits)\r
+\r
+DEFAULT REL\r
+\r
+SECTION .text\r
+\r
+;-------------------------------------------------------------------------------------\r
+;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
+;procedure serializes all the AP processors through an Init sequence. It must be\r
+;noted that APs arrive here very raw...ie: real mode, no stack.\r
+;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
+;IS IN MACHINE CODE.\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(RendezvousFunnelProc)\r
+ASM_PFX(RendezvousFunnelProc):\r
+RendezvousFunnelProcStart:\r
+; At this point CS = 0x(vv00) and ip= 0x0.\r
+; Save BIST information to ebp firstly\r
+\r
+BITS 16\r
+ mov ebp, eax ; Save BIST information\r
+\r
+ mov ax, cs\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov ss, ax\r
+ xor ax, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+\r
+ mov si, BufferStartLocation\r
+ mov ebx, [si]\r
+\r
+ mov di, ModeOffsetLocation\r
+ mov eax, [di]\r
+ mov di, CodeSegmentLocation\r
+ mov edx, [di]\r
+ mov di, ax\r
+ sub di, 02h \r
+ mov [di],dx ; Patch long mode CS\r
+ sub di, 04h\r
+ add eax, ebx\r
+ mov [di],eax ; Patch address\r
+\r
+ mov si, GdtrLocation\r
+o32 lgdt [cs:si]\r
+\r
+ mov si, IdtrLocation\r
+o32 lidt [cs:si]\r
+\r
+\r
+ mov di, DataSegmentLocation\r
+ mov edi, [di] ; Save long mode DS in edi\r
+\r
+ mov si, Cr3Location ; Save CR3 in ecx\r
+ mov ecx, [si]\r
+\r
+ xor ax, ax\r
+ mov ds, ax ; Clear data segment\r
+\r
+ mov eax, cr0 ; Get control register 0\r
+ or eax, 000000003h ; Set PE bit (bit #0) & MP\r
+ mov cr0, eax\r
+\r
+ mov eax, cr4\r
+ bts eax, 5\r
+ mov cr4, eax\r
+\r
+ mov cr3, ecx ; Load CR3\r
+\r
+ mov ecx, 0c0000080h ; EFER MSR number\r
+ rdmsr ; Read EFER\r
+ bts eax, 8 ; Set LME=1\r
+ wrmsr ; Write EFER\r
+\r
+ mov eax, cr0 ; Read CR0\r
+ bts eax, 31 ; Set PG=1\r
+ mov cr0, eax ; Write CR0\r
+\r
+ jmp 0:strict dword 0 ; far jump to long mode\r
+BITS 64\r
+LongModeStart:\r
+ mov eax, edi\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov ss, ax\r
+\r
+ mov esi, ebx\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ mov rax, NotVacantFlag\r
+\r
+TestLock:\r
+ xchg qword [edi], rax\r
+ cmp rax, NotVacantFlag\r
+ jz TestLock\r
+\r
+ mov edi, esi\r
+ add edi, NumApsExecutingLoction\r
+ inc dword [edi]\r
+ mov ebx, [edi]\r
+\r
+ProgramStack:\r
+ mov edi, esi\r
+ add edi, StackSizeLocation\r
+ mov rax, qword [edi]\r
+ mov edi, esi\r
+ add edi, StackStartAddressLocation\r
+ add rax, qword [edi]\r
+ mov rsp, rax\r
+ mov qword [edi], rax\r
+\r
+Releaselock:\r
+ mov rax, VacantFlag\r
+ mov edi, esi\r
+ add edi, LockLocation\r
+ xchg qword [edi], rax\r
+\r
+CProcedureInvoke:\r
+ push rbp ; push BIST data at top of AP stack\r
+ xor rbp, rbp ; clear ebp for call stack trace\r
+ push rbp\r
+ mov rbp, rsp\r
+\r
+ mov rax, ASM_PFX(InitializeFloatingPointUnits)\r
+ sub rsp, 20h\r
+ call rax ; Call assembly function to initialize FPU per UEFI spec\r
+ add rsp, 20h\r
+\r
+ mov edx, ebx ; edx is NumApsExecuting\r
+ mov ecx, esi\r
+ add ecx, LockLocation ; rcx is address of exchange info data buffer\r
+\r
+ mov edi, esi\r
+ add edi, ApProcedureLocation\r
+ mov rax, qword [edi]\r
+\r
+ sub rsp, 20h\r
+ call rax ; invoke C function\r
+ add rsp, 20h\r
+ jmp $\r
+\r
+RendezvousFunnelProcEnd:\r
+\r
+;-------------------------------------------------------------------------------------\r
+; AsmGetAddressMap (&AddressMap);\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(AsmGetAddressMap)\r
+ASM_PFX(AsmGetAddressMap):\r
+ mov rax, ASM_PFX(RendezvousFunnelProc)\r
+ mov qword [rcx], rax\r
+ mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
+ mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
+ ret\r
+\r
+;-------------------------------------------------------------------------------------\r
+;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
+;about to become an AP. It switches it'stack with the current AP.\r
+;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
+;-------------------------------------------------------------------------------------\r
+global ASM_PFX(AsmExchangeRole)\r
+ASM_PFX(AsmExchangeRole):\r
+ ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
+ ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
+\r
+ push rax\r
+ push rbx\r
+ push rcx\r
+ push rdx\r
+ push rsi\r
+ push rdi\r
+ push rbp\r
+ push r8\r
+ push r9\r
+ push r10\r
+ push r11\r
+ push r12\r
+ push r13\r
+ push r14\r
+ push r15\r
+\r
+ mov rax, cr0\r
+ push rax\r
+\r
+ mov rax, cr4\r
+ push rax\r
+\r
+ ; rsi contains MyInfo pointer\r
+ mov rsi, rcx\r
+\r
+ ; rdi contains OthersInfo pointer\r
+ mov rdi, rdx\r
+\r
+ ;Store EFLAGS, GDTR and IDTR regiter to stack\r
+ pushfq\r
+ sgdt [rsi + 16]\r
+ sidt [rsi + 26]\r
+\r
+ ; Store the its StackPointer\r
+ mov [rsi + 8], rsp\r
+\r
+ ; update its switch state to STORED\r
+ mov byte [rsi], CPU_SWITCH_STATE_STORED\r
+\r
+WaitForOtherStored:\r
+ ; wait until the other CPU finish storing its state\r
+ cmp byte [rdi], CPU_SWITCH_STATE_STORED\r
+ jz OtherStored\r
+ pause\r
+ jmp WaitForOtherStored\r
+\r
+OtherStored:\r
+ ; Since another CPU already stored its state, load them\r
+ ; load GDTR value\r
+ lgdt [rdi + 16]\r
+\r
+ ; load IDTR value\r
+ lidt [rdi + 26]\r
+\r
+ ; load its future StackPointer\r
+ mov rsp, [rdi + 8]\r
+\r
+ ; update the other CPU's switch state to LOADED\r
+ mov byte [rdi], CPU_SWITCH_STATE_LOADED\r
+\r
+WaitForOtherLoaded:\r
+ ; wait until the other CPU finish loading new state,\r
+ ; otherwise the data in stack may corrupt\r
+ cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r
+ jz OtherLoaded\r
+ pause\r
+ jmp WaitForOtherLoaded\r
+\r
+OtherLoaded:\r
+ ; since the other CPU already get the data it want, leave this procedure\r
+ popfq\r
+\r
+ pop rax\r
+ mov cr4, rax\r
+\r
+ pop rax\r
+ mov cr0, rax\r
+\r
+ pop r15\r
+ pop r14\r
+ pop r13\r
+ pop r12\r
+ pop r11\r
+ pop r10\r
+ pop r9\r
+ pop r8\r
+ pop rbp\r
+ pop rdi\r
+ pop rsi\r
+ pop rdx\r
+ pop rcx\r
+ pop rbx\r
+ pop rax\r
+\r
+ ret\r
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