Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared
as PcdsDynamic by the platform, so virtual machines can set these
properties during boot. As the PcdGet32() calls now call into the
PCD database, cache the values that are required during the handling
of interrupts.
Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16072
6f19259b-4bc3-4df7-8a09-
765794883524
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
- #\r
- # ARM Generic Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
- gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
-\r
#\r
# ARM Secure Firmware PCDs\r
#\r
#\r
# ARM Secure Firmware PCDs\r
#\r
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' to be redefined when using UEFI in a\r
+# context of virtual machine.\r
+#\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036\r
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040\r
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041\r
+\r
+ #\r
+ # ARM Generic Interrupt Controller\r
+ #\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
MemoryAllocationLib\r
UefiDriverEntryPoint\r
IoLib\r
MemoryAllocationLib\r
UefiDriverEntryPoint\r
IoLib\r
\r
[Protocols]\r
gHardwareInterruptProtocolGuid\r
gEfiCpuArchProtocolGuid\r
\r
\r
[Protocols]\r
gHardwareInterruptProtocolGuid\r
gEfiCpuArchProtocolGuid\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
\r
\r
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;\r
\r
\r
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;\r
\r
+UINT32 mGicInterruptInterfaceBase;\r
+UINT32 mGicDistributorBase;\r
+\r
/**\r
Enable interrupt source Source.\r
\r
/**\r
Enable interrupt source Source.\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
- ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);\r
+ ArmGicEnableInterrupt (mGicDistributorBase, Source);\r
\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
- ArmGicDisableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);\r
+ ArmGicDisableInterrupt (mGicDistributorBase, Source);\r
\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
- *InterruptState = ArmGicIsInterruptEnabled (FixedPcdGet32 (PcdGicDistributorBase), Source);\r
+ *InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, Source);\r
\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
return EFI_UNSUPPORTED;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
- ArmGicV2EndOfInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase), Source);\r
+ ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);\r
return EFI_SUCCESS;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
UINT32 GicInterrupt;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
UINT32 GicInterrupt;\r
HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));\r
+ GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
\r
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {\r
\r
// Acknowledge all pending interrupts\r
do {\r
\r
// Acknowledge all pending interrupts\r
do {\r
- GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));\r
+ GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);\r
\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {\r
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
\r
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {\r
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);\r
} while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));\r
\r
// Disable Gic Interface\r
} while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));\r
\r
// Disable Gic Interface\r
- ArmGicV2DisableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));\r
+ ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);\r
\r
// Disable Gic Distributor\r
\r
// Disable Gic Distributor\r
- ArmGicDisableDistributor (FixedPcdGet32 (PcdGicDistributorBase));\r
+ ArmGicDisableDistributor (mGicDistributorBase);\r
// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (FixedPcdGet32 (PcdGicDistributorBase));\r
+ mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);\r
+ mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);\r
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);\r
\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);\r
\r
for (Index = 0; Index < mGicNumInterrupts; Index++) {\r
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);\r
RegOffset = Index / 4;\r
RegShift = (Index % 4) * 8;\r
MmioAndThenOr32 (\r
RegOffset = Index / 4;\r
RegShift = (Index % 4) * 8;\r
MmioAndThenOr32 (\r
- FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4 * RegOffset),\r
+ mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),\r
~(0xff << RegShift),\r
ARM_GIC_DEFAULT_PRIORITY << RegShift\r
);\r
~(0xff << RegShift),\r
ARM_GIC_DEFAULT_PRIORITY << RegShift\r
);\r
//\r
// Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
// first SGIs)\r
//\r
// Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
// first SGIs)\r
- CpuTarget = MmioRead32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
+ CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);\r
\r
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
// is 0 when we run on a uniprocessor platform.\r
if (CpuTarget != 0) {\r
// The 8 first Interrupt Processor Targets Registers are read-only\r
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
\r
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
// is 0 when we run on a uniprocessor platform.\r
if (CpuTarget != 0) {\r
// The 8 first Interrupt Processor Targets Registers are read-only\r
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+ MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
}\r
}\r
\r
// Set binary point reg to 0x7 (no preemption)\r
}\r
}\r
\r
// Set binary point reg to 0x7 (no preemption)\r
- MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);\r
+ MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);\r
\r
// Set priority mask reg to 0xff to allow all priorities through\r
\r
// Set priority mask reg to 0xff to allow all priorities through\r
- MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);\r
+ MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);\r
\r
// Enable gic cpu interface\r
\r
// Enable gic cpu interface\r
- ArmGicEnableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));\r
+ ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);\r
\r
// Enable gic distributor\r
\r
// Enable gic distributor\r
- ArmGicEnableDistributor (FixedPcdGet32 (PcdGicDistributorBase));\r
+ ArmGicEnableDistributor (mGicDistributorBase);\r
\r
Status = InstallAndRegisterInterruptService (\r
&gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);\r
\r
Status = InstallAndRegisterInterruptService (\r
&gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);\r
DebugLib\r
DevicePathLib\r
HobLib\r
DebugLib\r
DevicePathLib\r
HobLib\r
PerformanceLib\r
SerialPortLib\r
FdtLib\r
PerformanceLib\r
SerialPortLib\r
FdtLib\r
[FixedPcd.ARM]\r
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset\r
\r
[FixedPcd.ARM]\r
gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicSgiIntId\r
\r
gArmTokenSpaceGuid.PcdGicDistributorBase\r
gArmTokenSpaceGuid.PcdGicSgiIntId\r
\r