MdePkg/Register/Amd: define GHCB macros for SNP AP creation

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled
in the guest VM. See the GHCB specification, Table 5 "List of Supported
Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details.

While at it, define the VMSA state save area that is required for creating
the AP. The save area format is defined in AMD APM volume 2, Table B-4
(there is a mistake in the table that defines the size of the reserved
area at offset 0xc8 as a dword, when it is actually a word). The format of
the save area segment registers is further defined in AMD APM volume 2,
sections 10 and 15.5.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com>
[lersek@redhat.com: fix typo in BZ reference]

diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h
index 029904b1c63afd119f3842fd576529d0b9a651f2..8c5f46e4bb537a31ed0142fd69ff44c84b53d426 100644 (file)
--- a/MdePkg/Include/Register/Amd/Ghcb.h
+++ b/MdePkg/Include/Register/Amd/Ghcb.h
@@ -55,6 +55,7 @@
 #define SVM_EXIT_AP_RESET_HOLD                  0x80000004ULL\r
 #define SVM_EXIT_AP_JUMP_TABLE                  0x80000005ULL\r
 #define SVM_EXIT_SNP_PAGE_STATE_CHANGE          0x80000010ULL\r
+#define SVM_EXIT_SNP_AP_CREATION                0x80000013ULL\r
 #define SVM_EXIT_HYPERVISOR_FEATURES            0x8000FFFDULL\r
 #define SVM_EXIT_UNSUPPORTED                    0x8000FFFFULL\r
 \r
@@ -83,6 +84,12 @@
 #define IOIO_SEG_ES         0\r
 #define IOIO_SEG_DS         (BIT11 | BIT10)\r
 \r
+//\r
+// AP Creation Information\r
+//\r
+#define SVM_VMGEXIT_SNP_AP_CREATE_ON_INIT  0\r
+#define SVM_VMGEXIT_SNP_AP_CREATE          1\r
+#define SVM_VMGEXIT_SNP_AP_DESTROY         2\r
 \r
 typedef PACKED struct {\r
   UINT8                  Reserved1[203];\r
@@ -195,4 +202,81 @@ typedef struct {
   SNP_PAGE_STATE_ENTRY   Entry[SNP_PAGE_STATE_MAX_ENTRY];\r
 } SNP_PAGE_STATE_CHANGE_INFO;\r
 \r
+//\r
+// SEV-ES save area mapping structures used for SEV-SNP AP Creation.\r
+// Only the fields required to be set to a non-zero value are defined.\r
+//\r
+// The segment register definition is defined for processor reset/real mode\r
+// (as when an INIT of the vCPU is requested). Should other modes (long mode,\r
+// etc.) be required, then the definitions can be enhanced.\r
+//\r
+\r
+//\r
+// Segment types at processor reset, See AMD APM Volume 2, Table 14-2.\r
+//\r
+#define SEV_ES_RESET_CODE_SEGMENT_TYPE  0xA\r
+#define SEV_ES_RESET_DATA_SEGMENT_TYPE  0x2\r
+\r
+#define SEV_ES_RESET_LDT_TYPE           0x2\r
+#define SEV_ES_RESET_TSS_TYPE           0x3\r
+\r
+#pragma pack (1)\r
+typedef union {\r
+    struct {\r
+      UINT16  Type:4;\r
+      UINT16  Sbit:1;\r
+      UINT16  Dpl:2;\r
+      UINT16  Present:1;\r
+      UINT16  Avl:1;\r
+      UINT16  Reserved1:1;\r
+      UINT16  Db:1;\r
+      UINT16  Granularity:1;\r
+    } Bits;\r
+    UINT16  Uint16;\r
+} SEV_ES_SEGMENT_REGISTER_ATTRIBUTES;\r
+\r
+typedef struct {\r
+  UINT16                                Selector;\r
+  SEV_ES_SEGMENT_REGISTER_ATTRIBUTES    Attributes;\r
+  UINT32                                Limit;\r
+  UINT64                                Base;\r
+} SEV_ES_SEGMENT_REGISTER;\r
+\r
+typedef struct {\r
+  SEV_ES_SEGMENT_REGISTER  Es;\r
+  SEV_ES_SEGMENT_REGISTER  Cs;\r
+  SEV_ES_SEGMENT_REGISTER  Ss;\r
+  SEV_ES_SEGMENT_REGISTER  Ds;\r
+  SEV_ES_SEGMENT_REGISTER  Fs;\r
+  SEV_ES_SEGMENT_REGISTER  Gs;\r
+  SEV_ES_SEGMENT_REGISTER  Gdtr;\r
+  SEV_ES_SEGMENT_REGISTER  Ldtr;\r
+  SEV_ES_SEGMENT_REGISTER  Idtr;\r
+  SEV_ES_SEGMENT_REGISTER  Tr;\r
+  UINT8                    Reserved1[42];\r
+  UINT8                    Vmpl;\r
+  UINT8                    Reserved2[5];\r
+  UINT64                   Efer;\r
+  UINT8                    Reserved3[112];\r
+  UINT64                   Cr4;\r
+  UINT8                    Reserved4[8];\r
+  UINT64                   Cr0;\r
+  UINT64                   Dr7;\r
+  UINT64                   Dr6;\r
+  UINT64                   Rflags;\r
+  UINT64                   Rip;\r
+  UINT8                    Reserved5[232];\r
+  UINT64                   GPat;\r
+  UINT8                    Reserved6[320];\r
+  UINT64                   SevFeatures;\r
+  UINT8                    Reserved7[48];\r
+  UINT64                   XCr0;\r
+  UINT8                    Reserved8[24];\r
+  UINT32                   Mxcsr;\r
+  UINT16                   X87Ftw;\r
+  UINT8                    Reserved9[2];\r
+  UINT16                   X87Fcw;\r
+} SEV_ES_SAVE_AREA;\r
+#pragma pack ()\r
+\r
 #endif\r