Before adding another SMM-related, and therefore Q35-only, dynamically
detectable feature, extract the current board type check from
Q35TsegMbytesInitialization() to a standalone function.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Message-Id: <
20200129214412.2361-5-lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
UINT16 ExtendedTsegMbytes;\r
RETURN_STATUS PcdStatus;\r
\r
- if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
- DEBUG ((\r
- DEBUG_ERROR,\r
- "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
- "only DID=0x%04x (Q35) is supported\n",\r
- __FUNCTION__,\r
- mHostBridgeDevId,\r
- INTEL_Q35_MCH_DEVICE_ID\r
- ));\r
- ASSERT (FALSE);\r
- CpuDeadLoop ();\r
- }\r
+ ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r
\r
//\r
// Check if QEMU offers an extended TSEG.\r
}\r
\r
\r
+VOID\r
+Q35BoardVerification (\r
+ VOID\r
+ )\r
+{\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ return;\r
+ }\r
+\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
+ "only DID=0x%04x (Q35) is supported\n",\r
+ __FUNCTION__,\r
+ mHostBridgeDevId,\r
+ INTEL_Q35_MCH_DEVICE_ID\r
+ ));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+}\r
+\r
+\r
/**\r
Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r
MaxCpuCountInitialization ();\r
\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ Q35BoardVerification ();\r
Q35TsegMbytesInitialization ();\r
}\r
\r