--- /dev/null
+## @file\r
+# SecCoreNative module that implements the SEC phase.\r
+#\r
+# This is the first module taking control after the reset vector.\r
+# The entry point function is _ModuleEntryPoint in PlatformSecLib.\r
+# The entry point function starts in 32bit protected mode or 64bit\r
+# mode depending on how resetvector is implemented, enables\r
+# temporary memory and calls into SecStartup().\r
+#\r
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SecCoreNative\r
+ MODULE_UNI_FILE = SecCore.uni\r
+ FILE_GUID = 43CA74CA-7D29-49A0-B3B9-20F84015B27D\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ SecMain.c\r
+ SecMain.h\r
+ FindPeiCore.c\r
+ SecBist.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseMemoryLib\r
+ DebugLib\r
+ PlatformSecLib\r
+ PcdLib\r
+ DebugAgentLib\r
+ UefiCpuLib\r
+ PeCoffGetEntryPointLib\r
+ PeCoffExtraActionLib\r
+ CpuExceptionHandlerLib\r
+ ReportStatusCodeLib\r
+ PeiServicesLib\r
+ PeiServicesTablePointerLib\r
+ HobLib\r
+\r
+[Ppis]\r
+ ## SOMETIMES_CONSUMES\r
+ ## PRODUCES\r
+ gEfiSecPlatformInformationPpiGuid\r
+ ## SOMETIMES_CONSUMES\r
+ ## SOMETIMES_PRODUCES\r
+ gEfiSecPlatformInformation2PpiGuid\r
+ gEfiTemporaryRamDonePpiGuid ## PRODUCES\r
+ ## NOTIFY\r
+ ## SOMETIMES_CONSUMES\r
+ gPeiSecPerformancePpiGuid\r
+ gEfiPeiCoreFvLocationPpiGuid\r
+ ## CONSUMES\r
+ gRepublishSecPpiPpiGuid\r
+\r
+[Guids]\r
+ ## SOMETIMES_PRODUCES ## HOB\r
+ gEfiFirmwarePerformanceGuid\r
+\r
+[Pcd]\r
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes ## CONSUMES\r
+\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+ SecCoreExtra.uni\r
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf\r
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf\r
UefiCpuPkg/SecCore/SecCore.inf\r
+ UefiCpuPkg/SecCore/SecCoreNative.inf\r
UefiCpuPkg/SecMigrationPei/SecMigrationPei.inf\r
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf\r
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {\r