BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Add RISC-V architecture on RISC-V EDK2 CI testing.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
# @file\r
#\r
# Copyright (c) Microsoft Corporation.\r
# @file\r
#\r
# Copyright (c) Microsoft Corporation.\r
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
##\r
import os\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
##\r
import os\r
\r
def GetArchitecturesSupported(self):\r
''' return iterable of edk2 architectures supported by this build '''\r
\r
def GetArchitecturesSupported(self):\r
''' return iterable of edk2 architectures supported by this build '''\r
+ "AARCH64",\r
+ "RISCV64")\r
\r
def GetTargetsSupported(self):\r
''' return iterable of edk2 target tags supported by this build '''\r
\r
def GetTargetsSupported(self):\r
''' return iterable of edk2 target tags supported by this build '''\r
scopes += ("gcc_aarch64_linux",)\r
if "ARM" in self.ActualArchitectures:\r
scopes += ("gcc_arm_linux",)\r
scopes += ("gcc_aarch64_linux",)\r
if "ARM" in self.ActualArchitectures:\r
scopes += ("gcc_arm_linux",)\r
+ if "RISCV64" in self.ActualArchitectures:\r
+ scopes += ("gcc_riscv64_unknown",)\r