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IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit
authorStar Zeng <star.zeng@intel.com>
Tue, 16 Jan 2018 08:41:42 +0000 (16:41 +0800)
committerStar Zeng <star.zeng@intel.com>
Wed, 17 Jan 2018 02:34:22 +0000 (10:34 +0800)
According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.

"Bits N:0 of the limit register are
decoded by hardware as all 1s."

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>

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