EmbeddedPkg: MmcDxe: declare ECSD structure
authorHaojian Zhuang <haojian.zhuang@linaro.org>
Sun, 13 Nov 2016 06:47:52 +0000 (14:47 +0800)
committerLeif Lindholm <leif.lindholm@linaro.org>
Mon, 14 Nov 2016 15:45:42 +0000 (15:45 +0000)
Declare fields in ECSD structure. And drop the original 128 words
arrary.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
EmbeddedPkg/Universal/MmcDxe/Mmc.h
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c

index f4e0aa0..3e11666 100644 (file)
@@ -132,13 +132,168 @@ typedef struct {
   UINT8   CSD_STRUCTURE:      2; // CSD structure [127:126]\r
 } CSD;\r
 \r
+typedef struct {\r
+  UINT8   RESERVED_1[16];                     // Reserved [15:0]\r
+  UINT8   SECURE_REMOVAL_TYPE;                // Secure Removal Type [16:16]\r
+  UINT8   PRODUCT_STATE_AWARENESS_ENABLEMENT; // Product state awareness enablement [17:17]\r
+  UINT8   MAX_PRE_LOADING_DATA_SIZE[4];       // MAX pre loading data size [21:18]\r
+  UINT8   PRE_LOADING_DATA_SIZE[4];           // Pre loading data size [25:22]\r
+  UINT8   FFU_STATUS;                         // FFU Status [26:26]\r
+  UINT8   RESERVED_2[2];                      // Reserved [28:27]\r
+  UINT8   MODE_OPERATION_CODES;               // Mode operation codes [29:29]\r
+  UINT8   MODE_CONFIG;                        // Mode config [30:30]\r
+  UINT8   RESERVED_3;                         // Reserved [31:31]\r
+  UINT8   FLUSH_CACHE;                        // Flushing of the cache [32:32]\r
+  UINT8   CACHE_CTRL;                         // Control to turn the cache ON/OFF [33:33]\r
+  UINT8   POWER_OFF_NOTIFICATION;             // Power Off Notification [34:34]\r
+  UINT8   PACKED_FAILURE_INDEX;               // Packed command failure index [35:35]\r
+  UINT8   PACKED_COMMAND_STATUS;              // Packed command status [36:36]\r
+  UINT8   CONTEXT_CONF[15];                   // Context configuration [51:37]\r
+  UINT8   EXT_PARTITIONS_ATTRIBUTE[2];        // Extended partitions attribute [53:52]\r
+  UINT8   EXCEPTION_EVENTS_STATUS[2];         // Exception events status [55:54]\r
+  UINT8   EXCEPTION_EVENTS_CTRL[2];           // Exception events control [57:56]\r
+  UINT8   DYNCAP_NEEDED;                      // Number of addressed group to be released [58:58]\r
+  UINT8   CLASS_6_CTRL;                       // Class 6 commands control [59:59]\r
+  UINT8   INI_TIMEOUT_EMU;                    // 1st initialization after disabling sector size emulation [60:60]\r
+  UINT8   DATA_SECTOR_SIZE;                   // Sector size [61:61]\r
+  UINT8   USE_NATIVE_SECTOR;                  // Sector size emulation [62:62]\r
+  UINT8   NATIVE_SECTOR_SIZE;                 // Native sector size [63:63]\r
+  UINT8   VENDOR_SPECIFIC_FIELD[64];          // Vendor specific fields [127:64]\r
+  UINT8   RESERVED_4[2];                      // Reserved [129:128]\r
+  UINT8   PROGRAM_CID_CSD_DDR_SUPPORT;        // Program CID/CSD in DDR mode support [130:130]\r
+  UINT8   PERIODIC_WAKEUP;                    // Periodic wake-up [131:131]\r
+  UINT8   TCASE_SUPPORT;                      // Package case temperature is controlled [132:132]\r
+  UINT8   PRODUCTION_STATE_AWARENESS;         // Production state awareness [133:133]\r
+  UINT8   SECTOR_BAD_BLK_MGMNT;               // Bad block management mode [134:134]\r
+  UINT8   RESERVED_5;                         // Reserved [135:135]\r
+  UINT8   ENH_START_ADDR[4];                  // Enhanced user data start address [139:136]\r
+  UINT8   ENH_SIZE_MULT[3];                   // Enhanced user data area size [142:140]\r
+  UINT8   GP_SIZE_MULT[12];                   // General purpose partition size [154:143]\r
+  UINT8   PARTITION_SETTING_COMPLETED;        // Partitioning setting [155:155]\r
+  UINT8   PARTITIONS_ATTRIBUTE;               // Partitions attribute [156:156]\r
+  UINT8   MAX_ENH_SIZE_MULT[3];               // Max enhanced area size [159:157]\r
+  UINT8   PARTITIONING_SUPPORT;               // Partitioning [160:160]\r
+  UINT8   HPI_MGMT;                           // HPI management [161:161]\r
+  UINT8   RST_N_FUNCTION;                     // H/W reset function [162:162]\r
+  UINT8   BKOPS_EN;                           // Enable background operations handshake [163:163]\r
+  UINT8   BKOPS_START;                        // Manually start background operations [164:164]\r
+  UINT8   SANITIZE_START;                     // Start sanitize operation [165:165]\r
+  UINT8   WR_REL_PARAM;                       // Write reliability parameter register [166:166]\r
+  UINT8   WR_REL_SET;                         // Write reliability setting register [167:167]\r
+  UINT8   RPMB_SIZE_MULT;                     // RPMB size [168:168]\r
+  UINT8   FW_CONFIG;                          // FW configuration [169:169]\r
+  UINT8   RESERVED_6;                         // Reserved [170:170]\r
+  UINT8   USER_WP;                            // User area write protection register [171:171]\r
+  UINT8   RESERVED_7;                         // Reserved [172:172]\r
+  UINT8   BOOT_WP;                            // Boot area write protection register [173:173]\r
+  UINT8   BOOT_WP_STATUS;                     // Boot write protection register [174:174]\r
+  UINT8   ERASE_GROUP_DEF;                    // High-density erase group definition [175:175]\r
+  UINT8   RESERVED_8;                         // Reserved [176:176]\r
+  UINT8   BOOT_BUS_CONDITIONS;                // Boot bus conditions [177:177]\r
+  UINT8   BOOT_CONFIG_PROT;                   // Boot config protection [178:178]\r
+  UINT8   PARTITION_CONFIG;                   // Partition config [179:179]\r
+  UINT8   RESERVED_9;                         // Reserved [180:180]\r
+  UINT8   ERASED_MEM_CONT;                    // Erased memory content [181:181]\r
+  UINT8   RESERVED_10;                        // Reserved [182:182]\r
+  UINT8   BUS_WIDTH;                          // Bus width mode [183:183]\r
+  UINT8   RESERVED_11;                        // Reserved [184:184]\r
+  UINT8   HS_TIMING;                          // High-speed interface timing [185:185]\r
+  UINT8   RESERVED_12;                        // Reserved [186:186]\r
+  UINT8   POWER_CLASS;                        // Power class [187:187]\r
+  UINT8   RESERVED_13;                        // Reserved [188:188]\r
+  UINT8   CMD_SET_REV;                        // Command set revision [189:189]\r
+  UINT8   RESERVED_14;                        // Reserved [190:190]\r
+  UINT8   CMD_SET;                            // Command set [191:191]\r
+  UINT8   EXT_CSD_REV;                        // Extended CSD revision [192:192]\r
+  UINT8   RESERVED_15;                        // Reserved [193:193]\r
+  UINT8   CSD_STRUCTURE;                      // CSD Structure [194:194]\r
+  UINT8   RESERVED_16;                        // Reserved [195:195]\r
+  UINT8   DEVICE_TYPE;                        // Device type [196:196]\r
+  UINT8   DRIVER_STRENGTH;                    // I/O Driver strength [197:197]\r
+  UINT8   OUT_OF_INTERRUPT_TIME;              // Out-of-interrupt busy timing [198:198]\r
+  UINT8   PARTITION_SWITCH_TIME;              // Partition switching timing [199:199]\r
+  UINT8   PWR_CL_52_195;                      // Power class for 52MHz at 1.95V 1 R [200:200]\r
+  UINT8   PWR_CL_26_195;                      // Power class for 26MHz at 1.95V 1 R [201:201]\r
+  UINT8   PWR_CL_52_360;                      // Power class for 52MHz at 3.6V 1 R [202:202]\r
+  UINT8   PWR_CL_26_360;                      // Power class for 26MHz at 3.6V 1 R [203:203]\r
+  UINT8   RESERVED_17;                        // Reserved [204:204]\r
+  UINT8   MIN_PERF_R_4_26;                    // Minimum read performance for 4bit at 26MHz [205:205]\r
+  UINT8   MIN_PERF_W_4_26;                    // Minimum write performance for 4bit at 26MHz [206:206]\r
+  UINT8   MIN_PERF_R_8_26_4_52;               // Minimum read performance for 8bit at 26MHz, for 4bit at 52MHz [207:207]\r
+  UINT8   MIN_PERF_W_8_26_4_52;               // Minimum write performance for 8bit at 26MHz, for 4bit at 52MHz [208:208]\r
+  UINT8   MIN_PERF_R_8_52;                    // Minimum read performance for 8bit at 52MHz [209:209]\r
+  UINT8   MIN_PERF_W_8_52;                    // Minimum write performance for 8bit at 52MHz [210:210]\r
+  UINT8   RESERVED_18;                        // Reserved [211:211]\r
+  UINT32  SECTOR_COUNT;                       // Sector count [215:212]\r
+  UINT8   SLEEP_NOTIFICATION_TIME;            // Sleep notification timout [216:216]\r
+  UINT8   S_A_TIMEOUT;                        // Sleep/awake timeout [217:217]\r
+  UINT8   PRODUCTION_STATE_AWARENESS_TIMEOUT; // Production state awareness timeout [218:218]\r
+  UINT8   S_C_VCCQ;                           // Sleep current (VCCQ) [219:219]\r
+  UINT8   S_C_VCC;                            // Sleep current (VCC) [220:220]\r
+  UINT8   HC_WP_GRP_SIZE;                     // High-capacity write protect group size [221:221]\r
+  UINT8   REL_WR_SECTOR_C;                    // Reliable write sector count [222:222]\r
+  UINT8   ERASE_TIMEOUT_MULT;                 // High-capacity erase timeout [223:223]\r
+  UINT8   HC_ERASE_GRP_SIZE;                  // High-capacity erase unit size [224:224]\r
+  UINT8   ACC_SIZE;                           // Access size [225:225]\r
+  UINT8   BOOT_SIZE_MULTI;                    // Boot partition size [226:226]\r
+  UINT8   RESERVED_19;                        // Reserved [227:227]\r
+  UINT8   BOOT_INFO;                          // Boot information [228:228]\r
+  UINT8   SECURE_TRIM_MULT;                   // Secure TRIM Multiplier [229:229]\r
+  UINT8   SECURE_ERASE_MULT;                  // Secure Erase Multiplier [230:230]\r
+  UINT8   SECURE_FEATURE_SUPPORT;             // Secure Feature Support [231:231]\r
+  UINT8   TRIM_MULT;                          // TRIM Multiplier [232:232]\r
+  UINT8   RESERVED_20;                        // Reserved [233:233]\r
+  UINT8   MIN_PREF_DDR_R_8_52;                // Minimum read performance for 8bit at 52MHz in DDR mode [234:234]\r
+  UINT8   MIN_PREF_DDR_W_8_52;                // Minimum write performance for 8bit at 52MHz in DDR mode [235:235]\r
+  UINT8   PWR_CL_200_130;                     // Power class for 200MHz at VCCQ=1.3V, VCC=3.6V [236:236]\r
+  UINT8   PWR_CL_200_195;                     // Power class for 200MHz at VCCQ=1.95V, VCC=3.6V [237:237]\r
+  UINT8   PWR_CL_DDR_52_195;                  // Power class for 52MHz, DDR at 1.95V [238:238]\r
+  UINT8   PWR_CL_DDR_52_360;                  // Power class for 52Mhz, DDR at 3.6V [239:239]\r
+  UINT8   RESERVED_21;                        // Reserved [240:240]\r
+  UINT8   INI_TIMEOUT_AP;                     // 1st initialization time after partitioning [241:241]\r
+  UINT8   CORRECTLY_PRG_SECTORS_NUM[4];       // Number of correctly programmed sectors [245:242]\r
+  UINT8   BKOPS_STATUS;                       // Background operations status [246:246]\r
+  UINT8   POWER_OFF_LONG_TIME;                // Power off notification (long) timeout [247:247]\r
+  UINT8   GENERIC_CMD6_TIME;                  // Generic CMD6 timeout [248:248]\r
+  UINT8   CACHE_SIZE[4];                      // Cache size [252:249]\r
+  UINT8   PWR_CL_DDR_200_360;                 // Power class for 200MHz, DDR at VCC=3.6V [253:253]\r
+  UINT8   FIRMWARE_VERSION[8];                // Firmware version [261:254]\r
+  UINT8   DEVICE_VERSION[2];                  // Device version [263:262]\r
+  UINT8   OPTIMAL_TRIM_UNIT_SIZE;             // Optimal trim unit size [264:264]\r
+  UINT8   OPTIMAL_WRITE_SIZE;                 // Optimal write size [265:265]\r
+  UINT8   OPTIMAL_READ_SIZE;                  // Optimal read size [266:266]\r
+  UINT8   PRE_EOL_INFO;                       // Pre EOL information [267:267]\r
+  UINT8   DEVICE_LIFE_TIME_EST_TYP_A;         // Device life time estimation type A [268:268]\r
+  UINT8   DEVICE_LIFE_TIME_EST_TYP_B;         // Device life time estimation type B [269:269]\r
+  UINT8   VENDOR_PROPRIETARY_HEALTH_REPORT[32];         // Vendor proprietary health report [301:270]\r
+  UINT8   NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED[4]; // Number of FW sectors correctly programmed [305:302]\r
+  UINT8   RESERVED_22[181];                   // Reserved [486:306]\r
+  UINT8   FFU_ARG[4];                         // FFU argument [490:487]\r
+  UINT8   OPERATION_CODE_TIMEOUT;             // Operation codes timeout [491:491]\r
+  UINT8   FFU_FEATURES;                       // FFU features [492:492]\r
+  UINT8   SUPPORTED_MODES;                    // Supported modes [493:493]\r
+  UINT8   EXT_SUPPORT;                        // Extended partitions attribute support [494:494]\r
+  UINT8   LARGE_UNIT_SIZE_M1;                 // Large unit size [495:495]\r
+  UINT8   CONTEXT_CAPABILITIES;               // Context management capabilities [496:496]\r
+  UINT8   TAG_RES_SIZE;                       // Tag resource size [497:497]\r
+  UINT8   TAG_UNIT_SIZE;                      // Tag unit size [498:498]\r
+  UINT8   DATA_TAG_SUPPORT;                   // Data tag support [499:499]\r
+  UINT8   MAX_PACKED_WRITES;                  // Max packed write commands [500:500]\r
+  UINT8   MAX_PACKED_READS;                   // Max packed read commands [501:501]\r
+  UINT8   BKOPS_SUPPORT;                      // Background operations support [502:502]\r
+  UINT8   HPI_FEATURES;                       // HPI features [503:503]\r
+  UINT8   S_CMD_SET;                          // Supported command sets [504:504]\r
+  UINT8   EXT_SECURITY_ERR;                   // Extended security commands error [505:505]\r
+  UINT8   RESERVED_23[6];                     // Reserved [511:506]\r
+} ECSD;\r
+\r
 typedef struct  {\r
   UINT16    RCA;\r
   CARD_TYPE CardType;\r
   OCR       OCRData;\r
   CID       CIDData;\r
   CSD       CSDData;\r
-  UINT32    ECSD[128];      // MMC V4 extended card specific\r
+  ECSD      ECSDData;                         // MMC V4 extended card specific\r
 } CARD_INFO;\r
 \r
 typedef struct _MMC_HOST_INSTANCE {\r
index 3531fb4..9aefb26 100644 (file)
@@ -90,7 +90,7 @@ EmmcIdentificationMode (
     DEBUG ((EFI_D_ERROR, "EmmcIdentificationMode(): ECSD fetch error, Status=%r.\n", Status));\r
   }\r
 \r
-  Status = Host->ReadBlockData (Host, 0, 512, (UINT32 *)&(MmcHostInstance->CardInfo.ECSD));\r
+  Status = Host->ReadBlockData (Host, 0, 512, (UINT32 *)&(MmcHostInstance->CardInfo.ECSDData));\r
   if (EFI_ERROR (Status)) {\r
     DEBUG ((EFI_D_ERROR, "EmmcIdentificationMode(): ECSD read error, Status=%r.\n", Status));\r
     return Status;\r
@@ -103,7 +103,7 @@ EmmcIdentificationMode (
   Media->LogicalBlocksPerPhysicalBlock = 1;\r
   Media->IoAlign = 4;\r
   // Compute last block using bits [215:212] of the ECSD\r
-  Media->LastBlock = MmcHostInstance->CardInfo.ECSD[EMMC_ECSD_SIZE_OFFSET] - 1; // eMMC isn't supposed to report this for\r
+  Media->LastBlock = MmcHostInstance->CardInfo.ECSDData.SECTOR_COUNT - 1; // eMMC isn't supposed to report this for\r
   // Cards <2GB in size, but the model does.\r
 \r
   // Setup card type\r