]> git.proxmox.com Git - mirror_edk2.git/commitdiff
UefiCpuPkg/SecCore: Add debug messages to illuminate data flow
authorOram, Isaac W <isaac.w.oram@intel.com>
Mon, 27 Jun 2022 22:48:51 +0000 (06:48 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Fri, 8 Jul 2022 04:04:22 +0000 (04:04 +0000)
Add debug messages to make it easier to verify PlatformSecLib
is passing the data properly.

Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Harry Han <harry.han@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Isaac Oram <isaac.w.oram@intel.com>
UefiCpuPkg/SecCore/SecMain.c

index a7526be9dd6eaf76b09d8fe0db5ee3321501e229..4edf0ce9725eed3c4063d776d86b36b88f3d9218 100644 (file)
@@ -167,6 +167,15 @@ SecStartup (
     EFI_SOFTWARE_SEC | EFI_SW_SEC_PC_ENTRY_POINT\r
     );\r
 \r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a() TempRAM Base: 0x%x, TempRAM Size: 0x%x, BootFirmwareVolume 0x%x\n",\r
+    __FUNCTION__,\r
+    TempRamBase,\r
+    SizeOfRam,\r
+    BootFirmwareVolume\r
+    ));\r
+\r
   PeiStackSize = PcdGet32 (PcdPeiTemporaryRamStackSize);\r
   if (PeiStackSize == 0) {\r
     PeiStackSize = (SizeOfRam >> 1);\r
@@ -229,6 +238,20 @@ SecStartup (
   SecCoreData.StackBase              = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
   SecCoreData.StackSize              = PeiStackSize;\r
 \r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a() BFV Base: 0x%x, BFV Size: 0x%x, TempRAM Base: 0x%x, TempRAM Size: 0x%x, PeiTempRamBase: 0x%x, PeiTempRamSize: 0x%x, StackBase: 0x%x, StackSize: 0x%x\n",\r
+    __FUNCTION__,\r
+    SecCoreData.BootFirmwareVolumeBase,\r
+    SecCoreData.BootFirmwareVolumeSize,\r
+    SecCoreData.TemporaryRamBase,\r
+    SecCoreData.TemporaryRamSize,\r
+    SecCoreData.PeiTemporaryRamBase,\r
+    SecCoreData.PeiTemporaryRamSize,\r
+    SecCoreData.StackBase,\r
+    SecCoreData.StackSize\r
+    ));\r
+\r
   //\r
   // Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.\r
   //\r
@@ -318,6 +341,13 @@ SecStartupPhase2 (
     }\r
   }\r
 \r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a() PeiCoreEntryPoint: 0x%x\n",\r
+    __FUNCTION__,\r
+    PeiCoreEntryPoint\r
+    ));\r
+\r
   if (PpiList != NULL) {\r
     AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase;\r
 \r
@@ -360,6 +390,13 @@ SecStartupPhase2 (
     //\r
     SecCoreData->PeiTemporaryRamBase  = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
     SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "%a() PeiTemporaryRamBase: 0x%x, PeiTemporaryRamSize: 0x%x\n",\r
+      __FUNCTION__,\r
+      SecCoreData->PeiTemporaryRamBase,\r
+      SecCoreData->PeiTemporaryRamSize\r
+      ));\r
   } else {\r
     //\r
     // No addition PPI, PpiList directly point to the common PPI list.\r