ArmPlatformPkg/LcdGraphicsOutputDxe: move headers into driver directory

The HdLcd.h and PL111Lcd.h header files are internal headers that should
not be used by other drivers. So move them from Include/Drivers into the
driver directory instead.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
index 2bfe2c0fe2dcd05f4983eea57542cfe3d30bf1ce..f5d7b53905fba8268bf49b16a9763cf63eb8770b 100644 (file)
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
@@ -18,8 +18,7 @@
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
-#include <Drivers/HdLcd.h>\r
-\r
+#include "HdLcd.h"\r
 #include "LcdGraphicsOutputDxe.h"\r
 \r
 /**********************************************************************\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
new file mode 100644 (file)
index 0000000..6df97a9
--- /dev/null
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
@@ -0,0 +1,89 @@
+/** @file  HDLcd.h\r
+\r
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution.  The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ **/\r
+\r
+#ifndef _HDLCD_H_\r
+#define _HDLCD_H_\r
+\r
+//\r
+// HDLCD Controller Register Offsets\r
+//\r
+\r
+#define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
+#define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
+#define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
+#define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
+#define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
+#define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
+#define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
+#define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
+#define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
+#define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
+#define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
+#define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
+#define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
+#define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
+#define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
+#define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
+#define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
+#define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
+#define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
+#define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
+#define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
+#define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
+#define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
+#define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
+\r
+\r
+//\r
+// HDLCD Values of registers\r
+//\r
+\r
+// HDLCD Interrupt mask, clear and status register\r
+#define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */\r
+#define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */\r
+#define HDLCD_SYNC                        BIT2    /* Vertical sync */\r
+#define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */\r
+\r
+// CLCD_CONTROL Control register\r
+#define HDLCD_DISABLE                     0\r
+#define HDLCD_ENABLE                      BIT0\r
+\r
+// Bus Options\r
+#define HDLCD_BURST_1                     BIT0\r
+#define HDLCD_BURST_2                     BIT1\r
+#define HDLCD_BURST_4                     BIT2\r
+#define HDLCD_BURST_8                     BIT3\r
+#define HDLCD_BURST_16                    BIT4\r
+\r
+// Polarities - HIGH\r
+#define HDLCD_VSYNC_HIGH                  BIT0\r
+#define HDLCD_HSYNC_HIGH                  BIT1\r
+#define HDLCD_DATEN_HIGH                  BIT2\r
+#define HDLCD_DATA_HIGH                   BIT3\r
+#define HDLCD_PXCLK_HIGH                  BIT4\r
+// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
+#define HDLCD_VSYNC_LOW                   0\r
+#define HDLCD_HSYNC_LOW                   0\r
+#define HDLCD_DATEN_LOW                   0\r
+#define HDLCD_DATA_LOW                    0\r
+#define HDLCD_PXCLK_LOW                   0\r
+\r
+// Pixel Format\r
+#define HDLCD_LITTLE_ENDIAN              (0 << 31)\r
+#define HDLCD_BIG_ENDIAN                 (1 << 31)\r
+\r
+// Number of bytes per pixel\r
+#define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)\r
+\r
+#endif /* _HDLCD_H_ */\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c
index b5e113b844d4e4df2e35ccd880c01344b4b8b9d7..a9ce60c5b0a6d3ef13e4f59dd4d0909347840a9d 100644 (file)
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c
@@ -15,9 +15,8 @@
 #include <Library/IoLib.h>\r
 #include <Library/MemoryAllocationLib.h>\r
 \r
-#include <Drivers/PL111Lcd.h>\r
-\r
 #include "LcdGraphicsOutputDxe.h"\r
+#include "PL111Lcd.h"\r
 \r
 /**********************************************************************\r
  *\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
new file mode 100644 (file)
index 0000000..18e28af
--- /dev/null
+++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
@@ -0,0 +1,149 @@
+/** @file  PL111Lcd.h\r
+\r
+ Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution.  The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ **/\r
+\r
+#ifndef _PL111LCD_H__\r
+#define _PL111LCD_H__\r
+\r
+/**********************************************************************\r
+ *\r
+ *  This header file contains all the bits of the PL111 that are\r
+ *  platform independent.\r
+ *\r
+ **********************************************************************/\r
+\r
+// Controller Register Offsets\r
+#define PL111_REG_LCD_TIMING_0            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)\r
+#define PL111_REG_LCD_TIMING_1            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)\r
+#define PL111_REG_LCD_TIMING_2            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)\r
+#define PL111_REG_LCD_TIMING_3            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)\r
+#define PL111_REG_LCD_UP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)\r
+#define PL111_REG_LCD_LP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)\r
+#define PL111_REG_LCD_CONTROL             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)\r
+#define PL111_REG_LCD_IMSC                ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)\r
+#define PL111_REG_LCD_RIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)\r
+#define PL111_REG_LCD_MIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)\r
+#define PL111_REG_LCD_ICR                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)\r
+#define PL111_REG_LCD_UP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)\r
+#define PL111_REG_LCD_LP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)\r
+#define PL111_REG_LCD_PALETTE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)\r
+\r
+// Identification Register Offsets\r
+#define PL111_REG_CLCD_PERIPH_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)\r
+#define PL111_REG_CLCD_PERIPH_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)\r
+#define PL111_REG_CLCD_PERIPH_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)\r
+#define PL111_REG_CLCD_PERIPH_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)\r
+#define PL111_REG_CLCD_P_CELL_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)\r
+#define PL111_REG_CLCD_P_CELL_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)\r
+#define PL111_REG_CLCD_P_CELL_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)\r
+#define PL111_REG_CLCD_P_CELL_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)\r
+\r
+#define PL111_CLCD_PERIPH_ID_0            0x11\r
+#define PL111_CLCD_PERIPH_ID_1            0x11\r
+#define PL111_CLCD_PERIPH_ID_2            0x04\r
+#define PL111_CLCD_PERIPH_ID_3            0x00\r
+#define PL111_CLCD_P_CELL_ID_0            0x0D\r
+#define PL111_CLCD_P_CELL_ID_1            0xF0\r
+#define PL111_CLCD_P_CELL_ID_2            0x05\r
+#define PL111_CLCD_P_CELL_ID_3            0xB1\r
+\r
+/**********************************************************************/\r
+\r
+// Register components (register bits)\r
+\r
+// This should make life easier to program specific settings in the different registers\r
+// by simplifying the setting up of the individual bits of each register\r
+// and then assembling the final register value.\r
+\r
+/**********************************************************************/\r
+\r
+// Register: PL111_REG_LCD_TIMING_0\r
+#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))\r
+\r
+// Register: PL111_REG_LCD_TIMING_1\r
+#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))\r
+\r
+// Register: PL111_REG_LCD_TIMING_2\r
+#define PL111_BIT_SHIFT_PCD_HI            27\r
+#define PL111_BIT_SHIFT_BCD               26\r
+#define PL111_BIT_SHIFT_CPL               16\r
+#define PL111_BIT_SHIFT_IOE               14\r
+#define PL111_BIT_SHIFT_IPC               13\r
+#define PL111_BIT_SHIFT_IHS               12\r
+#define PL111_BIT_SHIFT_IVS               11\r
+#define PL111_BIT_SHIFT_ACB               6\r
+#define PL111_BIT_SHIFT_CLKSEL            5\r
+#define PL111_BIT_SHIFT_PCD_LO            0\r
+\r
+#define PL111_BCD                         (1 << 26)\r
+#define PL111_IPC                         (1 << 13)\r
+#define PL111_IHS                         (1 << 12)\r
+#define PL111_IVS                         (1 << 11)\r
+\r
+#define CLK_SIG_POLARITY(hor_res)         (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))\r
+\r
+// Register: PL111_REG_LCD_TIMING_3\r
+#define PL111_BIT_SHIFT_LEE               16\r
+#define PL111_BIT_SHIFT_LED               0\r
+\r
+#define PL111_CTRL_WATERMARK              (1 << 16)\r
+#define PL111_CTRL_LCD_V_COMP             (1 << 12)\r
+#define PL111_CTRL_LCD_PWR                (1 << 11)\r
+#define PL111_CTRL_BEPO                   (1 << 10)\r
+#define PL111_CTRL_BEBO                   (1 << 9)\r
+#define PL111_CTRL_BGR                    (1 << 8)\r
+#define PL111_CTRL_LCD_DUAL               (1 << 7)\r
+#define PL111_CTRL_LCD_MONO_8             (1 << 6)\r
+#define PL111_CTRL_LCD_TFT                (1 << 5)\r
+#define PL111_CTRL_LCD_BW                 (1 << 4)\r
+#define PL111_CTRL_LCD_1BPP               (0 << 1)\r
+#define PL111_CTRL_LCD_2BPP               (1 << 1)\r
+#define PL111_CTRL_LCD_4BPP               (2 << 1)\r
+#define PL111_CTRL_LCD_8BPP               (3 << 1)\r
+#define PL111_CTRL_LCD_16BPP              (4 << 1)\r
+#define PL111_CTRL_LCD_24BPP              (5 << 1)\r
+#define PL111_CTRL_LCD_16BPP_565          (6 << 1)\r
+#define PL111_CTRL_LCD_12BPP_444          (7 << 1)\r
+#define PL111_CTRL_LCD_BPP(Bpp)           ((Bpp) << 1)\r
+#define PL111_CTRL_LCD_EN                 1\r
+\r
+/**********************************************************************/\r
+\r
+// Register: PL111_REG_LCD_TIMING_0\r
+#define PL111_LCD_TIMING_0_HBP(hbp)       (((hbp) & 0xFF) << 24)\r
+#define PL111_LCD_TIMING_0_HFP(hfp)       (((hfp) & 0xFF) << 16)\r
+#define PL111_LCD_TIMING_0_HSW(hsw)       (((hsw) & 0xFF) << 8)\r
+#define PL111_LCD_TIMING_0_PPL(ppl)       (((hsw) & 0x3F) << 2)\r
+\r
+// Register: PL111_REG_LCD_TIMING_1\r
+#define PL111_LCD_TIMING_1_VBP(vbp)       (((vbp) & 0xFF) << 24)\r
+#define PL111_LCD_TIMING_1_VFP(vfp)       (((vfp) & 0xFF) << 16)\r
+#define PL111_LCD_TIMING_1_VSW(vsw)       (((vsw) & 0x3F) << 10)\r
+#define PL111_LCD_TIMING_1_LPP(lpp)        ((lpp) & 0xFC)\r
+\r
+// Register: PL111_REG_LCD_TIMING_2\r
+#define PL111_BIT_MASK_PCD_HI             0xF8000000\r
+#define PL111_BIT_MASK_BCD                0x04000000\r
+#define PL111_BIT_MASK_CPL                0x03FF0000\r
+#define PL111_BIT_MASK_IOE                0x00004000\r
+#define PL111_BIT_MASK_IPC                0x00002000\r
+#define PL111_BIT_MASK_IHS                0x00001000\r
+#define PL111_BIT_MASK_IVS                0x00000800\r
+#define PL111_BIT_MASK_ACB                0x000007C0\r
+#define PL111_BIT_MASK_CLKSEL             0x00000020\r
+#define PL111_BIT_MASK_PCD_LO             0x0000001F\r
+\r
+// Register: PL111_REG_LCD_TIMING_3\r
+#define PL111_BIT_MASK_LEE                0x00010000\r
+#define PL111_BIT_MASK_LED                0x0000007F\r
+\r
+#endif /* _PL111LCD_H__ */\r

diff --git a/ArmPlatformPkg/Include/Drivers/HdLcd.h b/ArmPlatformPkg/Include/Drivers/HdLcd.h
deleted file mode 100644 (file)
index 6df97a9..0000000
--- a/ArmPlatformPkg/Include/Drivers/HdLcd.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/** @file  HDLcd.h\r
-\r
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution.  The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#ifndef _HDLCD_H_\r
-#define _HDLCD_H_\r
-\r
-//\r
-// HDLCD Controller Register Offsets\r
-//\r
-\r
-#define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
-#define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
-#define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
-#define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
-#define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
-#define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
-#define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
-#define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
-#define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
-#define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
-#define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
-#define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
-#define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
-#define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
-#define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
-#define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
-#define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
-#define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
-#define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
-#define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
-#define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
-#define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
-#define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
-#define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
-\r
-\r
-//\r
-// HDLCD Values of registers\r
-//\r
-\r
-// HDLCD Interrupt mask, clear and status register\r
-#define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */\r
-#define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */\r
-#define HDLCD_SYNC                        BIT2    /* Vertical sync */\r
-#define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */\r
-\r
-// CLCD_CONTROL Control register\r
-#define HDLCD_DISABLE                     0\r
-#define HDLCD_ENABLE                      BIT0\r
-\r
-// Bus Options\r
-#define HDLCD_BURST_1                     BIT0\r
-#define HDLCD_BURST_2                     BIT1\r
-#define HDLCD_BURST_4                     BIT2\r
-#define HDLCD_BURST_8                     BIT3\r
-#define HDLCD_BURST_16                    BIT4\r
-\r
-// Polarities - HIGH\r
-#define HDLCD_VSYNC_HIGH                  BIT0\r
-#define HDLCD_HSYNC_HIGH                  BIT1\r
-#define HDLCD_DATEN_HIGH                  BIT2\r
-#define HDLCD_DATA_HIGH                   BIT3\r
-#define HDLCD_PXCLK_HIGH                  BIT4\r
-// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
-#define HDLCD_VSYNC_LOW                   0\r
-#define HDLCD_HSYNC_LOW                   0\r
-#define HDLCD_DATEN_LOW                   0\r
-#define HDLCD_DATA_LOW                    0\r
-#define HDLCD_PXCLK_LOW                   0\r
-\r
-// Pixel Format\r
-#define HDLCD_LITTLE_ENDIAN              (0 << 31)\r
-#define HDLCD_BIG_ENDIAN                 (1 << 31)\r
-\r
-// Number of bytes per pixel\r
-#define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)\r
-\r
-#endif /* _HDLCD_H_ */\r

diff --git a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h b/ArmPlatformPkg/Include/Drivers/PL111Lcd.h
deleted file mode 100644 (file)
index 18e28af..0000000
--- a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/** @file  PL111Lcd.h\r
-\r
- Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution.  The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#ifndef _PL111LCD_H__\r
-#define _PL111LCD_H__\r
-\r
-/**********************************************************************\r
- *\r
- *  This header file contains all the bits of the PL111 that are\r
- *  platform independent.\r
- *\r
- **********************************************************************/\r
-\r
-// Controller Register Offsets\r
-#define PL111_REG_LCD_TIMING_0            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)\r
-#define PL111_REG_LCD_TIMING_1            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)\r
-#define PL111_REG_LCD_TIMING_2            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)\r
-#define PL111_REG_LCD_TIMING_3            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)\r
-#define PL111_REG_LCD_UP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)\r
-#define PL111_REG_LCD_LP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)\r
-#define PL111_REG_LCD_CONTROL             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)\r
-#define PL111_REG_LCD_IMSC                ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)\r
-#define PL111_REG_LCD_RIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)\r
-#define PL111_REG_LCD_MIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)\r
-#define PL111_REG_LCD_ICR                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)\r
-#define PL111_REG_LCD_UP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)\r
-#define PL111_REG_LCD_LP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)\r
-#define PL111_REG_LCD_PALETTE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)\r
-\r
-// Identification Register Offsets\r
-#define PL111_REG_CLCD_PERIPH_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)\r
-#define PL111_REG_CLCD_PERIPH_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)\r
-#define PL111_REG_CLCD_PERIPH_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)\r
-#define PL111_REG_CLCD_PERIPH_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)\r
-#define PL111_REG_CLCD_P_CELL_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)\r
-#define PL111_REG_CLCD_P_CELL_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)\r
-#define PL111_REG_CLCD_P_CELL_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)\r
-#define PL111_REG_CLCD_P_CELL_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)\r
-\r
-#define PL111_CLCD_PERIPH_ID_0            0x11\r
-#define PL111_CLCD_PERIPH_ID_1            0x11\r
-#define PL111_CLCD_PERIPH_ID_2            0x04\r
-#define PL111_CLCD_PERIPH_ID_3            0x00\r
-#define PL111_CLCD_P_CELL_ID_0            0x0D\r
-#define PL111_CLCD_P_CELL_ID_1            0xF0\r
-#define PL111_CLCD_P_CELL_ID_2            0x05\r
-#define PL111_CLCD_P_CELL_ID_3            0xB1\r
-\r
-/**********************************************************************/\r
-\r
-// Register components (register bits)\r
-\r
-// This should make life easier to program specific settings in the different registers\r
-// by simplifying the setting up of the individual bits of each register\r
-// and then assembling the final register value.\r
-\r
-/**********************************************************************/\r
-\r
-// Register: PL111_REG_LCD_TIMING_0\r
-#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))\r
-\r
-// Register: PL111_REG_LCD_TIMING_1\r
-#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))\r
-\r
-// Register: PL111_REG_LCD_TIMING_2\r
-#define PL111_BIT_SHIFT_PCD_HI            27\r
-#define PL111_BIT_SHIFT_BCD               26\r
-#define PL111_BIT_SHIFT_CPL               16\r
-#define PL111_BIT_SHIFT_IOE               14\r
-#define PL111_BIT_SHIFT_IPC               13\r
-#define PL111_BIT_SHIFT_IHS               12\r
-#define PL111_BIT_SHIFT_IVS               11\r
-#define PL111_BIT_SHIFT_ACB               6\r
-#define PL111_BIT_SHIFT_CLKSEL            5\r
-#define PL111_BIT_SHIFT_PCD_LO            0\r
-\r
-#define PL111_BCD                         (1 << 26)\r
-#define PL111_IPC                         (1 << 13)\r
-#define PL111_IHS                         (1 << 12)\r
-#define PL111_IVS                         (1 << 11)\r
-\r
-#define CLK_SIG_POLARITY(hor_res)         (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))\r
-\r
-// Register: PL111_REG_LCD_TIMING_3\r
-#define PL111_BIT_SHIFT_LEE               16\r
-#define PL111_BIT_SHIFT_LED               0\r
-\r
-#define PL111_CTRL_WATERMARK              (1 << 16)\r
-#define PL111_CTRL_LCD_V_COMP             (1 << 12)\r
-#define PL111_CTRL_LCD_PWR                (1 << 11)\r
-#define PL111_CTRL_BEPO                   (1 << 10)\r
-#define PL111_CTRL_BEBO                   (1 << 9)\r
-#define PL111_CTRL_BGR                    (1 << 8)\r
-#define PL111_CTRL_LCD_DUAL               (1 << 7)\r
-#define PL111_CTRL_LCD_MONO_8             (1 << 6)\r
-#define PL111_CTRL_LCD_TFT                (1 << 5)\r
-#define PL111_CTRL_LCD_BW                 (1 << 4)\r
-#define PL111_CTRL_LCD_1BPP               (0 << 1)\r
-#define PL111_CTRL_LCD_2BPP               (1 << 1)\r
-#define PL111_CTRL_LCD_4BPP               (2 << 1)\r
-#define PL111_CTRL_LCD_8BPP               (3 << 1)\r
-#define PL111_CTRL_LCD_16BPP              (4 << 1)\r
-#define PL111_CTRL_LCD_24BPP              (5 << 1)\r
-#define PL111_CTRL_LCD_16BPP_565          (6 << 1)\r
-#define PL111_CTRL_LCD_12BPP_444          (7 << 1)\r
-#define PL111_CTRL_LCD_BPP(Bpp)           ((Bpp) << 1)\r
-#define PL111_CTRL_LCD_EN                 1\r
-\r
-/**********************************************************************/\r
-\r
-// Register: PL111_REG_LCD_TIMING_0\r
-#define PL111_LCD_TIMING_0_HBP(hbp)       (((hbp) & 0xFF) << 24)\r
-#define PL111_LCD_TIMING_0_HFP(hfp)       (((hfp) & 0xFF) << 16)\r
-#define PL111_LCD_TIMING_0_HSW(hsw)       (((hsw) & 0xFF) << 8)\r
-#define PL111_LCD_TIMING_0_PPL(ppl)       (((hsw) & 0x3F) << 2)\r
-\r
-// Register: PL111_REG_LCD_TIMING_1\r
-#define PL111_LCD_TIMING_1_VBP(vbp)       (((vbp) & 0xFF) << 24)\r
-#define PL111_LCD_TIMING_1_VFP(vfp)       (((vfp) & 0xFF) << 16)\r
-#define PL111_LCD_TIMING_1_VSW(vsw)       (((vsw) & 0x3F) << 10)\r
-#define PL111_LCD_TIMING_1_LPP(lpp)        ((lpp) & 0xFC)\r
-\r
-// Register: PL111_REG_LCD_TIMING_2\r
-#define PL111_BIT_MASK_PCD_HI             0xF8000000\r
-#define PL111_BIT_MASK_BCD                0x04000000\r
-#define PL111_BIT_MASK_CPL                0x03FF0000\r
-#define PL111_BIT_MASK_IOE                0x00004000\r
-#define PL111_BIT_MASK_IPC                0x00002000\r
-#define PL111_BIT_MASK_IHS                0x00001000\r
-#define PL111_BIT_MASK_IVS                0x00000800\r
-#define PL111_BIT_MASK_ACB                0x000007C0\r
-#define PL111_BIT_MASK_CLKSEL             0x00000020\r
-#define PL111_BIT_MASK_PCD_LO             0x0000001F\r
-\r
-// Register: PL111_REG_LCD_TIMING_3\r
-#define PL111_BIT_MASK_LEE                0x00010000\r
-#define PL111_BIT_MASK_LED                0x0000007F\r
-\r
-#endif /* _PL111LCD_H__ */\r