--- /dev/null
+/** @file\r
+Implementation shared across all library instances.\r
+\r
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) Microsoft Corporation.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <PiMm.h>\r
+#include <Library/SmmCpuFeaturesLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/MtrrLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Register/Intel/Cpuid.h>\r
+#include <Register/Intel/SmramSaveStateMap.h>\r
+#include "CpuFeaturesLib.h"\r
+\r
+//\r
+// Machine Specific Registers (MSRs)\r
+//\r
+#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE\r
+#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A\r
+#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2\r
+#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3\r
+#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0\r
+#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1\r
+#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
+#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
+#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
+\r
+//\r
+// MSRs required for configuration of SMM Code Access Check\r
+//\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
+#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
+\r
+//\r
+// Set default value to assume IA-32 Architectural MSRs are used\r
+//\r
+UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;\r
+UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;\r
+\r
+//\r
+// Set default value to assume MTRRs need to be configured on each SMI\r
+//\r
+BOOLEAN mNeedConfigureMtrrs = TRUE;\r
+\r
+//\r
+// Array for state of SMRR enable on all CPUs\r
+//\r
+BOOLEAN *mSmrrEnabled;\r
+\r
+/**\r
+ Performs library initialization.\r
+\r
+ This initialization function contains common functionality shared betwen all\r
+ library instance constructors.\r
+\r
+**/\r
+VOID\r
+CpuFeaturesLibInitialization (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINTN FamilyId;\r
+ UINTN ModelId;\r
+\r
+ //\r
+ // Retrieve CPU Family and Model\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
+ FamilyId = (RegEax >> 8) & 0xf;\r
+ ModelId = (RegEax >> 4) & 0xf;\r
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
+ ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
+ }\r
+\r
+ //\r
+ // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability\r
+ //\r
+ if ((RegEdx & BIT12) != 0) {\r
+ //\r
+ // Check MTRR_CAP MSR bit 11 for SMRR support\r
+ //\r
+ if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {\r
+ ASSERT (FeaturePcdGet (PcdSmrrEnable));\r
+ }\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family\r
+ //\r
+ // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then\r
+ // SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
+ //\r
+ if (FamilyId == 0x06) {\r
+ if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {\r
+ ASSERT (!FeaturePcdGet (PcdSmrrEnable));\r
+ }\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
+ //\r
+ // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2\r
+ // Processor Family MSRs\r
+ //\r
+ if (FamilyId == 0x06) {\r
+ if ((ModelId == 0x17) || (ModelId == 0x0f)) {\r
+ mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
+ mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 34.4.2 SMRAM Caching\r
+ // An IA-32 processor does not automatically write back and invalidate its\r
+ // caches before entering SMM or before exiting SMM. Because of this behavior,\r
+ // care must be taken in the placement of the SMRAM in system memory and in\r
+ // the caching of the SMRAM to prevent cache incoherence when switching back\r
+ // and forth between SMM and protected mode operation.\r
+ //\r
+ // An IA-32 processor is a processor that does not support the Intel 64\r
+ // Architecture. Support for the Intel 64 Architecture can be detected from\r
+ // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]\r
+ //\r
+ // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,\r
+ // so caches are flushed on SMI entry and SMI exit, the interrupted code\r
+ // MTRRs are saved/restored, and MTRRs for SMM are loaded.\r
+ //\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
+ if ((RegEdx & BIT29) != 0) {\r
+ mNeedConfigureMtrrs = FALSE;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Allocate array for state of SMRR enable on all CPUs\r
+ //\r
+ mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ());\r
+ ASSERT (mSmrrEnabled != NULL);\r
+}\r
+\r
+/**\r
+ Called during the very first SMI into System Management Mode to initialize\r
+ CPU features, including SMBASE, for the currently executing CPU. Since this\r
+ is the first SMI, the SMRAM Save State Map is at the default address of\r
+ SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
+ CPU is specified by CpuIndex and CpuIndex can be used to access information\r
+ about the currently executing CPU in the ProcessorInfo array and the\r
+ HotPlugCpuData data structure.\r
+\r
+ @param[in] CpuIndex The index of the CPU to initialize. The value\r
+ must be between 0 and the NumberOfCpus field in\r
+ the System Management System Table (SMST).\r
+ @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
+ was elected as monarch during System Management\r
+ Mode initialization.\r
+ FALSE if the CpuIndex is not the index of the CPU\r
+ that was elected as monarch during System\r
+ Management Mode initialization.\r
+ @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
+ structures. ProcessorInfo[CpuIndex] contains the\r
+ information for the currently executing CPU.\r
+ @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
+ contains the ApidId and SmBase arrays.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesInitializeProcessor (\r
+ IN UINTN CpuIndex,\r
+ IN BOOLEAN IsMonarch,\r
+ IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
+ IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
+ )\r
+{\r
+ SMRAM_SAVE_STATE_MAP *CpuState;\r
+ UINT64 FeatureControl;\r
+ UINT32 RegEax;\r
+ UINT32 RegEdx;\r
+ UINTN FamilyId;\r
+ UINTN ModelId;\r
+\r
+ //\r
+ // Configure SMBASE.\r
+ //\r
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+ CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
+ //\r
+ // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then\r
+ // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before\r
+ // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
+ // is set, then the MSR is locked and can not be modified.\r
+ //\r
+ if ((FeaturePcdGet (PcdSmrrEnable)) && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {\r
+ FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
+ if ((FeatureControl & BIT3) == 0) {\r
+ ASSERT ((FeatureControl & BIT0) == 0);\r
+ if ((FeatureControl & BIT0) == 0) {\r
+ AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If SMRR is supported, then program SMRR base/mask MSRs.\r
+ // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.\r
+ // The code that initializes SMM environment is running in normal mode\r
+ // from SMRAM region. If SMRR is enabled here, then the SMRAM region\r
+ // is protected and the normal mode code execution will fail.\r
+ //\r
+ if (FeaturePcdGet (PcdSmrrEnable)) {\r
+ //\r
+ // SMRR size cannot be less than 4-KBytes\r
+ // SMRR size must be of length 2^n\r
+ // SMRR base alignment cannot be less than SMRR length\r
+ //\r
+ if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
+ (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))\r
+ {\r
+ //\r
+ // Print message and halt if CPU is Monarch\r
+ //\r
+ if (IsMonarch) {\r
+ DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
+ CpuDeadLoop ();\r
+ }\r
+ } else {\r
+ AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
+ mSmrrEnabled[CpuIndex] = FALSE;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Retrieve CPU Family and Model\r
+ //\r
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
+ FamilyId = (RegEax >> 8) & 0xf;\r
+ ModelId = (RegEax >> 4) & 0xf;\r
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
+ ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
+ }\r
+\r
+ //\r
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
+ // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
+ // Processor Family.\r
+ //\r
+ // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
+ // Intel(R) Core(TM) Processor Family MSRs.\r
+ //\r
+ if (FamilyId == 0x06) {\r
+ if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||\r
+ (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||\r
+ (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||\r
+ (ModelId == 0x8C))\r
+ {\r
+ //\r
+ // Check to see if the CPU supports the SMM Code Access Check feature\r
+ // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
+ //\r
+ if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
+ ASSERT (FeaturePcdGet (PcdSmmFeatureControlEnable));\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Call internal worker function that completes the CPU initialization\r
+ //\r
+ FinishSmmCpuFeaturesInitializeProcessor ();\r
+}\r
+\r
+/**\r
+ This function updates the SMRAM save state on the currently executing CPU\r
+ to resume execution at a specific address after an RSM instruction. This\r
+ function must evaluate the SMRAM save state to determine the execution mode\r
+ the RSM instruction resumes and update the resume execution address with\r
+ either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
+ flag in the SMRAM save state must always be cleared. This function returns\r
+ the value of the instruction pointer from the SMRAM save state that was\r
+ replaced. If this function returns 0, then the SMRAM save state was not\r
+ modified.\r
+\r
+ This function is called during the very first SMI on each CPU after\r
+ SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
+ to signal that the SMBASE of each CPU has been updated before the default\r
+ SMBASE address is used for the first SMI to the next CPU.\r
+\r
+ @param[in] CpuIndex The index of the CPU to hook. The value\r
+ must be between 0 and the NumberOfCpus\r
+ field in the System Management System Table\r
+ (SMST).\r
+ @param[in] CpuState Pointer to SMRAM Save State Map for the\r
+ currently executing CPU.\r
+ @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
+ 32-bit execution mode from 64-bit SMM.\r
+ @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
+ same execution mode as SMM.\r
+\r
+ @retval 0 This function did modify the SMRAM save state.\r
+ @retval > 0 The original instruction pointer value from the SMRAM save state\r
+ before it was replaced.\r
+**/\r
+UINT64\r
+EFIAPI\r
+SmmCpuFeaturesHookReturnFromSmm (\r
+ IN UINTN CpuIndex,\r
+ IN SMRAM_SAVE_STATE_MAP *CpuState,\r
+ IN UINT64 NewInstructionPointer32,\r
+ IN UINT64 NewInstructionPointer\r
+ )\r
+{\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Hook point in normal execution mode that allows the one CPU that was elected\r
+ as monarch during System Management Mode initialization to perform additional\r
+ initialization actions immediately after all of the CPUs have processed their\r
+ first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
+ into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesSmmRelocationComplete (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Determines if MTRR registers must be configured to set SMRAM cache-ability\r
+ when executing in System Management Mode.\r
+\r
+ @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
+ @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
+ cache-ability.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SmmCpuFeaturesNeedConfigureMtrrs (\r
+ VOID\r
+ )\r
+{\r
+ return mNeedConfigureMtrrs;\r
+}\r
+\r
+/**\r
+ Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
+ returns TRUE.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesDisableSmrr (\r
+ VOID\r
+ )\r
+{\r
+ if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+ }\r
+}\r
+\r
+/**\r
+ Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
+ returns TRUE.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesReenableSmrr (\r
+ VOID\r
+ )\r
+{\r
+ if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+ }\r
+}\r
+\r
+/**\r
+ Processor specific hook point each time a CPU enters System Management Mode.\r
+\r
+ @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
+ must be between 0 and the NumberOfCpus field in the\r
+ System Management System Table (SMST).\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesRendezvousEntry (\r
+ IN UINTN CpuIndex\r
+ )\r
+{\r
+ //\r
+ // If SMRR is supported and this is the first normal SMI, then enable SMRR\r
+ //\r
+ if (FeaturePcdGet (PcdSmrrEnable) && !mSmrrEnabled[CpuIndex]) {\r
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+ mSmrrEnabled[CpuIndex] = TRUE;\r
+ }\r
+}\r
+\r
+/**\r
+ Processor specific hook point each time a CPU exits System Management Mode.\r
+\r
+ @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
+ be between 0 and the NumberOfCpus field in the System\r
+ Management System Table (SMST).\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesRendezvousExit (\r
+ IN UINTN CpuIndex\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ Check to see if an SMM register is supported by a specified CPU.\r
+\r
+ @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
+ The value must be between 0 and the NumberOfCpus field\r
+ in the System Management System Table (SMST).\r
+ @param[in] RegName Identifies the SMM register to check for support.\r
+\r
+ @retval TRUE The SMM register specified by RegName is supported by the CPU\r
+ specified by CpuIndex.\r
+ @retval FALSE The SMM register specified by RegName is not supported by the\r
+ CPU specified by CpuIndex.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SmmCpuFeaturesIsSmmRegisterSupported (\r
+ IN UINTN CpuIndex,\r
+ IN SMM_REG_NAME RegName\r
+ )\r
+{\r
+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
+ return TRUE;\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Returns the current value of the SMM register for the specified CPU.\r
+ If the SMM register is not supported, then 0 is returned.\r
+\r
+ @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
+ value must be between 0 and the NumberOfCpus field in\r
+ the System Management System Table (SMST).\r
+ @param[in] RegName Identifies the SMM register to read.\r
+\r
+ @return The value of the SMM register specified by RegName from the CPU\r
+ specified by CpuIndex.\r
+**/\r
+UINT64\r
+EFIAPI\r
+SmmCpuFeaturesGetSmmRegister (\r
+ IN UINTN CpuIndex,\r
+ IN SMM_REG_NAME RegName\r
+ )\r
+{\r
+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
+ return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ Sets the value of an SMM register on a specified CPU.\r
+ If the SMM register is not supported, then no action is performed.\r
+\r
+ @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
+ value must be between 0 and the NumberOfCpus field in\r
+ the System Management System Table (SMST).\r
+ @param[in] RegName Identifies the SMM register to write.\r
+ registers are read-only.\r
+ @param[in] Value The value to write to the SMM register.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesSetSmmRegister (\r
+ IN UINTN CpuIndex,\r
+ IN SMM_REG_NAME RegName,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
+ AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
+ }\r
+}\r
+\r
+/**\r
+ Read an SMM Save State register on the target processor. If this function\r
+ returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
+ SMM Save Sate register.\r
+\r
+ @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
+ value must be between 0 and the NumberOfCpus field in\r
+ the System Management System Table (SMST).\r
+ @param[in] Register The SMM Save State register to read.\r
+ @param[in] Width The number of bytes to read from the CPU save state.\r
+ @param[out] Buffer Upon return, this holds the CPU register value read\r
+ from the save state.\r
+\r
+ @retval EFI_SUCCESS The register was read from Save State.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED This function does not support reading Register.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmCpuFeaturesReadSaveStateRegister (\r
+ IN UINTN CpuIndex,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN Width,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ Writes an SMM Save State register on the target processor. If this function\r
+ returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
+ SMM Save Sate register.\r
+\r
+ @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
+ value must be between 0 and the NumberOfCpus field in\r
+ the System Management System Table (SMST).\r
+ @param[in] Register The SMM Save State register to write.\r
+ @param[in] Width The number of bytes to write to the CPU save state.\r
+ @param[in] Buffer Upon entry, this holds the new CPU register value.\r
+\r
+ @retval EFI_SUCCESS The register was written to Save State.\r
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
+ @retval EFI_UNSUPPORTED This function does not support writing Register.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmCpuFeaturesWriteSaveStateRegister (\r
+ IN UINTN CpuIndex,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN Width,\r
+ IN CONST VOID *Buffer\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+ This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
+ notification is completely processed.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmCpuFeaturesCompleteSmmReadyToLock (\r
+ VOID\r
+ )\r
+{\r
+}\r
+\r
+/**\r
+ This API provides a method for a CPU to allocate a specific region for storing page tables.\r
+\r
+ This API can be called more once to allocate memory for page tables.\r
+\r
+ Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
+ allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
+ is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
+ returned.\r
+\r
+ This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+ @param Pages The number of 4 KB pages to allocate.\r
+\r
+ @return A pointer to the allocated buffer for page tables.\r
+ @retval NULL Fail to allocate a specific region for storing page tables,\r
+ Or there is no preference on where the page tables are allocated in SMRAM.\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+SmmCpuFeaturesAllocatePageTableMemory (\r
+ IN UINTN Pages\r
+ )\r
+{\r
+ return NULL;\r
+}\r
\r
[Sources]\r
CpuFeaturesLib.h\r
+ IntelSmmCpuFeaturesLib.c\r
SmmCpuFeaturesLib.c\r
- SmmCpuFeaturesLibCommon.c\r
SmmCpuFeaturesLibNoStm.c\r
TraditionalMmCpuFeaturesLib.c\r
\r
+++ /dev/null
-/** @file\r
-Implementation shared across all library instances.\r
-\r
-Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
-Copyright (c) Microsoft Corporation.<BR>\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#include <PiMm.h>\r
-#include <Library/SmmCpuFeaturesLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/MtrrLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Register/Intel/Cpuid.h>\r
-#include <Register/Intel/SmramSaveStateMap.h>\r
-#include "CpuFeaturesLib.h"\r
-\r
-//\r
-// Machine Specific Registers (MSRs)\r
-//\r
-#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE\r
-#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A\r
-#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2\r
-#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3\r
-#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0\r
-#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1\r
-#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
-#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
-#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
-\r
-//\r
-// MSRs required for configuration of SMM Code Access Check\r
-//\r
-#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
-#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
-\r
-//\r
-// Set default value to assume IA-32 Architectural MSRs are used\r
-//\r
-UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;\r
-UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;\r
-\r
-//\r
-// Set default value to assume MTRRs need to be configured on each SMI\r
-//\r
-BOOLEAN mNeedConfigureMtrrs = TRUE;\r
-\r
-//\r
-// Array for state of SMRR enable on all CPUs\r
-//\r
-BOOLEAN *mSmrrEnabled;\r
-\r
-/**\r
- Performs library initialization.\r
-\r
- This initialization function contains common functionality shared betwen all\r
- library instance constructors.\r
-\r
-**/\r
-VOID\r
-CpuFeaturesLibInitialization (\r
- VOID\r
- )\r
-{\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINTN FamilyId;\r
- UINTN ModelId;\r
-\r
- //\r
- // Retrieve CPU Family and Model\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
- FamilyId = (RegEax >> 8) & 0xf;\r
- ModelId = (RegEax >> 4) & 0xf;\r
- if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
- ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
- }\r
-\r
- //\r
- // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability\r
- //\r
- if ((RegEdx & BIT12) != 0) {\r
- //\r
- // Check MTRR_CAP MSR bit 11 for SMRR support\r
- //\r
- if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {\r
- ASSERT (FeaturePcdGet (PcdSmrrEnable));\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family\r
- //\r
- // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then\r
- // SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
- //\r
- if (FamilyId == 0x06) {\r
- if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {\r
- ASSERT (!FeaturePcdGet (PcdSmrrEnable));\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
- //\r
- // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2\r
- // Processor Family MSRs\r
- //\r
- if (FamilyId == 0x06) {\r
- if ((ModelId == 0x17) || (ModelId == 0x0f)) {\r
- mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
- mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 34.4.2 SMRAM Caching\r
- // An IA-32 processor does not automatically write back and invalidate its\r
- // caches before entering SMM or before exiting SMM. Because of this behavior,\r
- // care must be taken in the placement of the SMRAM in system memory and in\r
- // the caching of the SMRAM to prevent cache incoherence when switching back\r
- // and forth between SMM and protected mode operation.\r
- //\r
- // An IA-32 processor is a processor that does not support the Intel 64\r
- // Architecture. Support for the Intel 64 Architecture can be detected from\r
- // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]\r
- //\r
- // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,\r
- // so caches are flushed on SMI entry and SMI exit, the interrupted code\r
- // MTRRs are saved/restored, and MTRRs for SMM are loaded.\r
- //\r
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
- if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
- AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT29) != 0) {\r
- mNeedConfigureMtrrs = FALSE;\r
- }\r
- }\r
-\r
- //\r
- // Allocate array for state of SMRR enable on all CPUs\r
- //\r
- mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ());\r
- ASSERT (mSmrrEnabled != NULL);\r
-}\r
-\r
-/**\r
- Called during the very first SMI into System Management Mode to initialize\r
- CPU features, including SMBASE, for the currently executing CPU. Since this\r
- is the first SMI, the SMRAM Save State Map is at the default address of\r
- SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing\r
- CPU is specified by CpuIndex and CpuIndex can be used to access information\r
- about the currently executing CPU in the ProcessorInfo array and the\r
- HotPlugCpuData data structure.\r
-\r
- @param[in] CpuIndex The index of the CPU to initialize. The value\r
- must be between 0 and the NumberOfCpus field in\r
- the System Management System Table (SMST).\r
- @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that\r
- was elected as monarch during System Management\r
- Mode initialization.\r
- FALSE if the CpuIndex is not the index of the CPU\r
- that was elected as monarch during System\r
- Management Mode initialization.\r
- @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION\r
- structures. ProcessorInfo[CpuIndex] contains the\r
- information for the currently executing CPU.\r
- @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that\r
- contains the ApidId and SmBase arrays.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesInitializeProcessor (\r
- IN UINTN CpuIndex,\r
- IN BOOLEAN IsMonarch,\r
- IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,\r
- IN CPU_HOT_PLUG_DATA *CpuHotPlugData\r
- )\r
-{\r
- SMRAM_SAVE_STATE_MAP *CpuState;\r
- UINT64 FeatureControl;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINTN FamilyId;\r
- UINTN ModelId;\r
-\r
- //\r
- // Configure SMBASE.\r
- //\r
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
- CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
- //\r
- // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then\r
- // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before\r
- // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
- // is set, then the MSR is locked and can not be modified.\r
- //\r
- if ((FeaturePcdGet (PcdSmrrEnable)) && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {\r
- FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
- if ((FeatureControl & BIT3) == 0) {\r
- ASSERT ((FeatureControl & BIT0) == 0);\r
- if ((FeatureControl & BIT0) == 0) {\r
- AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);\r
- }\r
- }\r
- }\r
-\r
- //\r
- // If SMRR is supported, then program SMRR base/mask MSRs.\r
- // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.\r
- // The code that initializes SMM environment is running in normal mode\r
- // from SMRAM region. If SMRR is enabled here, then the SMRAM region\r
- // is protected and the normal mode code execution will fail.\r
- //\r
- if (FeaturePcdGet (PcdSmrrEnable)) {\r
- //\r
- // SMRR size cannot be less than 4-KBytes\r
- // SMRR size must be of length 2^n\r
- // SMRR base alignment cannot be less than SMRR length\r
- //\r
- if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
- (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
- ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))\r
- {\r
- //\r
- // Print message and halt if CPU is Monarch\r
- //\r
- if (IsMonarch) {\r
- DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));\r
- CpuDeadLoop ();\r
- }\r
- } else {\r
- AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
- mSmrrEnabled[CpuIndex] = FALSE;\r
- }\r
- }\r
-\r
- //\r
- // Retrieve CPU Family and Model\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
- FamilyId = (RegEax >> 8) & 0xf;\r
- ModelId = (RegEax >> 4) & 0xf;\r
- if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
- ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
- // Processor Family.\r
- //\r
- // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
- // Intel(R) Core(TM) Processor Family MSRs.\r
- //\r
- if (FamilyId == 0x06) {\r
- if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||\r
- (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||\r
- (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||\r
- (ModelId == 0x8C))\r
- {\r
- //\r
- // Check to see if the CPU supports the SMM Code Access Check feature\r
- // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
- //\r
- if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
- ASSERT (FeaturePcdGet (PcdSmmFeatureControlEnable));\r
- }\r
- }\r
- }\r
-\r
- //\r
- // Call internal worker function that completes the CPU initialization\r
- //\r
- FinishSmmCpuFeaturesInitializeProcessor ();\r
-}\r
-\r
-/**\r
- This function updates the SMRAM save state on the currently executing CPU\r
- to resume execution at a specific address after an RSM instruction. This\r
- function must evaluate the SMRAM save state to determine the execution mode\r
- the RSM instruction resumes and update the resume execution address with\r
- either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart\r
- flag in the SMRAM save state must always be cleared. This function returns\r
- the value of the instruction pointer from the SMRAM save state that was\r
- replaced. If this function returns 0, then the SMRAM save state was not\r
- modified.\r
-\r
- This function is called during the very first SMI on each CPU after\r
- SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode\r
- to signal that the SMBASE of each CPU has been updated before the default\r
- SMBASE address is used for the first SMI to the next CPU.\r
-\r
- @param[in] CpuIndex The index of the CPU to hook. The value\r
- must be between 0 and the NumberOfCpus\r
- field in the System Management System Table\r
- (SMST).\r
- @param[in] CpuState Pointer to SMRAM Save State Map for the\r
- currently executing CPU.\r
- @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to\r
- 32-bit execution mode from 64-bit SMM.\r
- @param[in] NewInstructionPointer Instruction pointer to use if resuming to\r
- same execution mode as SMM.\r
-\r
- @retval 0 This function did modify the SMRAM save state.\r
- @retval > 0 The original instruction pointer value from the SMRAM save state\r
- before it was replaced.\r
-**/\r
-UINT64\r
-EFIAPI\r
-SmmCpuFeaturesHookReturnFromSmm (\r
- IN UINTN CpuIndex,\r
- IN SMRAM_SAVE_STATE_MAP *CpuState,\r
- IN UINT64 NewInstructionPointer32,\r
- IN UINT64 NewInstructionPointer\r
- )\r
-{\r
- return 0;\r
-}\r
-\r
-/**\r
- Hook point in normal execution mode that allows the one CPU that was elected\r
- as monarch during System Management Mode initialization to perform additional\r
- initialization actions immediately after all of the CPUs have processed their\r
- first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE\r
- into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesSmmRelocationComplete (\r
- VOID\r
- )\r
-{\r
-}\r
-\r
-/**\r
- Determines if MTRR registers must be configured to set SMRAM cache-ability\r
- when executing in System Management Mode.\r
-\r
- @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.\r
- @retval FALSE MTRR registers do not need to be configured to set SMRAM\r
- cache-ability.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-SmmCpuFeaturesNeedConfigureMtrrs (\r
- VOID\r
- )\r
-{\r
- return mNeedConfigureMtrrs;\r
-}\r
-\r
-/**\r
- Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
- returns TRUE.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesDisableSmrr (\r
- VOID\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- }\r
-}\r
-\r
-/**\r
- Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()\r
- returns TRUE.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesReenableSmrr (\r
- VOID\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmrrEnable) && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- }\r
-}\r
-\r
-/**\r
- Processor specific hook point each time a CPU enters System Management Mode.\r
-\r
- @param[in] CpuIndex The index of the CPU that has entered SMM. The value\r
- must be between 0 and the NumberOfCpus field in the\r
- System Management System Table (SMST).\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesRendezvousEntry (\r
- IN UINTN CpuIndex\r
- )\r
-{\r
- //\r
- // If SMRR is supported and this is the first normal SMI, then enable SMRR\r
- //\r
- if (FeaturePcdGet (PcdSmrrEnable) && !mSmrrEnabled[CpuIndex]) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- mSmrrEnabled[CpuIndex] = TRUE;\r
- }\r
-}\r
-\r
-/**\r
- Processor specific hook point each time a CPU exits System Management Mode.\r
-\r
- @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must\r
- be between 0 and the NumberOfCpus field in the System\r
- Management System Table (SMST).\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesRendezvousExit (\r
- IN UINTN CpuIndex\r
- )\r
-{\r
-}\r
-\r
-/**\r
- Check to see if an SMM register is supported by a specified CPU.\r
-\r
- @param[in] CpuIndex The index of the CPU to check for SMM register support.\r
- The value must be between 0 and the NumberOfCpus field\r
- in the System Management System Table (SMST).\r
- @param[in] RegName Identifies the SMM register to check for support.\r
-\r
- @retval TRUE The SMM register specified by RegName is supported by the CPU\r
- specified by CpuIndex.\r
- @retval FALSE The SMM register specified by RegName is not supported by the\r
- CPU specified by CpuIndex.\r
-**/\r
-BOOLEAN\r
-EFIAPI\r
-SmmCpuFeaturesIsSmmRegisterSupported (\r
- IN UINTN CpuIndex,\r
- IN SMM_REG_NAME RegName\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
- return TRUE;\r
- }\r
-\r
- return FALSE;\r
-}\r
-\r
-/**\r
- Returns the current value of the SMM register for the specified CPU.\r
- If the SMM register is not supported, then 0 is returned.\r
-\r
- @param[in] CpuIndex The index of the CPU to read the SMM register. The\r
- value must be between 0 and the NumberOfCpus field in\r
- the System Management System Table (SMST).\r
- @param[in] RegName Identifies the SMM register to read.\r
-\r
- @return The value of the SMM register specified by RegName from the CPU\r
- specified by CpuIndex.\r
-**/\r
-UINT64\r
-EFIAPI\r
-SmmCpuFeaturesGetSmmRegister (\r
- IN UINTN CpuIndex,\r
- IN SMM_REG_NAME RegName\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
- return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
- }\r
-\r
- return 0;\r
-}\r
-\r
-/**\r
- Sets the value of an SMM register on a specified CPU.\r
- If the SMM register is not supported, then no action is performed.\r
-\r
- @param[in] CpuIndex The index of the CPU to write the SMM register. The\r
- value must be between 0 and the NumberOfCpus field in\r
- the System Management System Table (SMST).\r
- @param[in] RegName Identifies the SMM register to write.\r
- registers are read-only.\r
- @param[in] Value The value to write to the SMM register.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesSetSmmRegister (\r
- IN UINTN CpuIndex,\r
- IN SMM_REG_NAME RegName,\r
- IN UINT64 Value\r
- )\r
-{\r
- if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {\r
- AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
- }\r
-}\r
-\r
-/**\r
- Read an SMM Save State register on the target processor. If this function\r
- returns EFI_UNSUPPORTED, then the caller is responsible for reading the\r
- SMM Save Sate register.\r
-\r
- @param[in] CpuIndex The index of the CPU to read the SMM Save State. The\r
- value must be between 0 and the NumberOfCpus field in\r
- the System Management System Table (SMST).\r
- @param[in] Register The SMM Save State register to read.\r
- @param[in] Width The number of bytes to read from the CPU save state.\r
- @param[out] Buffer Upon return, this holds the CPU register value read\r
- from the save state.\r
-\r
- @retval EFI_SUCCESS The register was read from Save State.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED This function does not support reading Register.\r
-\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SmmCpuFeaturesReadSaveStateRegister (\r
- IN UINTN CpuIndex,\r
- IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
- IN UINTN Width,\r
- OUT VOID *Buffer\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- Writes an SMM Save State register on the target processor. If this function\r
- returns EFI_UNSUPPORTED, then the caller is responsible for writing the\r
- SMM Save Sate register.\r
-\r
- @param[in] CpuIndex The index of the CPU to write the SMM Save State. The\r
- value must be between 0 and the NumberOfCpus field in\r
- the System Management System Table (SMST).\r
- @param[in] Register The SMM Save State register to write.\r
- @param[in] Width The number of bytes to write to the CPU save state.\r
- @param[in] Buffer Upon entry, this holds the new CPU register value.\r
-\r
- @retval EFI_SUCCESS The register was written to Save State.\r
- @retval EFI_INVALID_PARAMETER Buffer is NULL.\r
- @retval EFI_UNSUPPORTED This function does not support writing Register.\r
-**/\r
-EFI_STATUS\r
-EFIAPI\r
-SmmCpuFeaturesWriteSaveStateRegister (\r
- IN UINTN CpuIndex,\r
- IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
- IN UINTN Width,\r
- IN CONST VOID *Buffer\r
- )\r
-{\r
- return EFI_UNSUPPORTED;\r
-}\r
-\r
-/**\r
- This function is hook point called after the gEfiSmmReadyToLockProtocolGuid\r
- notification is completely processed.\r
-**/\r
-VOID\r
-EFIAPI\r
-SmmCpuFeaturesCompleteSmmReadyToLock (\r
- VOID\r
- )\r
-{\r
-}\r
-\r
-/**\r
- This API provides a method for a CPU to allocate a specific region for storing page tables.\r
-\r
- This API can be called more once to allocate memory for page tables.\r
-\r
- Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r
- allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r
- is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r
- returned.\r
-\r
- This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.\r
-\r
- @param Pages The number of 4 KB pages to allocate.\r
-\r
- @return A pointer to the allocated buffer for page tables.\r
- @retval NULL Fail to allocate a specific region for storing page tables,\r
- Or there is no preference on where the page tables are allocated in SMRAM.\r
-\r
-**/\r
-VOID *\r
-EFIAPI\r
-SmmCpuFeaturesAllocatePageTableMemory (\r
- IN UINTN Pages\r
- )\r
-{\r
- return NULL;\r
-}\r
\r
[Sources]\r
CpuFeaturesLib.h\r
- SmmCpuFeaturesLibCommon.c\r
+ IntelSmmCpuFeaturesLib.c\r
SmmStm.c\r
SmmStm.h\r
TraditionalMmCpuFeaturesLib.c\r
\r
[Sources]\r
CpuFeaturesLib.h\r
+ IntelSmmCpuFeaturesLib.c\r
StandaloneMmCpuFeaturesLib.c\r
- SmmCpuFeaturesLibCommon.c\r
SmmCpuFeaturesLibNoStm.c\r
\r
[Packages]\r
projects / mirror_edk2.git / commitdiff