IN UINTN NumberOfProcessors\r
);\r
\r
+/**\r
+ Detects if Protected Processor Inventory Number feature supported on current \r
+ processor.\r
+\r
+ @param[in] ProcessorNumber The index of the CPU executing this function.\r
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
+ structure for the CPU executing this function.\r
+ @param[in] ConfigData A pointer to the configuration buffer returned\r
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
+ RegisterCpuFeature().\r
+\r
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.\r
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.\r
+\r
+ @note This service could be called by BSP/APs.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PpinSupport (\r
+ IN UINTN ProcessorNumber,\r
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
+ IN VOID *ConfigData OPTIONAL\r
+ );\r
+\r
+/**\r
+ Initializes Protected Processor Inventory Number feature to specific state.\r
+\r
+ @param[in] ProcessorNumber The index of the CPU executing this function.\r
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
+ structure for the CPU executing this function.\r
+ @param[in] ConfigData A pointer to the configuration buffer returned\r
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
+ RegisterCpuFeature().\r
+ @param[in] State If TRUE, then the Protected Processor Inventory \r
+ Number feature must be enabled.\r
+ If FALSE, then the Protected Processor Inventory \r
+ Number feature must be disabled.\r
+\r
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is \r
+ initialized.\r
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been \r
+ locked.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PpinInitialize (\r
+ IN UINTN ProcessorNumber,\r
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
+ IN VOID *ConfigData, OPTIONAL\r
+ IN BOOLEAN State\r
+ );\r
+\r
#endif\r
--- /dev/null
+/** @file\r
+ Protected Processor Inventory Number(PPIN) feature.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CpuCommonFeatures.h"\r
+\r
+/**\r
+ Detects if Protected Processor Inventory Number feature supported on current \r
+ processor.\r
+\r
+ @param[in] ProcessorNumber The index of the CPU executing this function.\r
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
+ structure for the CPU executing this function.\r
+ @param[in] ConfigData A pointer to the configuration buffer returned\r
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
+ RegisterCpuFeature().\r
+\r
+ @retval TRUE Enhanced Intel SpeedStep feature is supported.\r
+ @retval FALSE Enhanced Intel SpeedStep feature is not supported.\r
+\r
+ @note This service could be called by BSP/APs.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PpinSupport (\r
+ IN UINTN ProcessorNumber,\r
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
+ IN VOID *ConfigData OPTIONAL\r
+ )\r
+{\r
+ MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;\r
+\r
+ if ((CpuInfo->DisplayFamily == 0x06) && \r
+ ((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2\r
+ (CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product\r
+ (CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4\r
+ (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable\r
+ (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.\r
+ (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor \r
+ )) {\r
+ //\r
+ // Check whether platform support this feature.\r
+ //\r
+ PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
+ return (PlatformInfo.Bits.PPIN_CAP != 0);\r
+ }\r
+\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Initializes Protected Processor Inventory Number feature to specific state.\r
+\r
+ @param[in] ProcessorNumber The index of the CPU executing this function.\r
+ @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r
+ structure for the CPU executing this function.\r
+ @param[in] ConfigData A pointer to the configuration buffer returned\r
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in\r
+ RegisterCpuFeature().\r
+ @param[in] State If TRUE, then the Protected Processor Inventory \r
+ Number feature must be enabled.\r
+ If FALSE, then the Protected Processor Inventory \r
+ Number feature must be disabled.\r
+\r
+ @retval RETURN_SUCCESS Protected Processor Inventory Number feature is \r
+ initialized.\r
+ @retval RETURN_DEVICE_ERROR Device can't change state because it has been \r
+ locked.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+PpinInitialize (\r
+ IN UINTN ProcessorNumber,\r
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r
+ IN VOID *ConfigData, OPTIONAL\r
+ IN BOOLEAN State\r
+ )\r
+{\r
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl;\r
+\r
+ //\r
+ // Check whether device already lock this register.\r
+ // If already locked, just base on the request state and\r
+ // the current state to return the status.\r
+ //\r
+ MsrPpinCtrl.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
+ if (MsrPpinCtrl.Bits.LockOut != 0) {\r
+ return MsrPpinCtrl.Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r
+ }\r
+\r
+ CPU_REGISTER_TABLE_WRITE_FIELD (\r
+ ProcessorNumber,\r
+ Msr,\r
+ MSR_IVY_BRIDGE_PPIN_CTL,\r
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER,\r
+ Bits.Enable_PPIN,\r
+ (State) ? 1 : 0\r
+ );\r
+\r
+ return RETURN_SUCCESS;\r
+}\r