ArmPlatformPkg: Juno - add correct SPI interrupt numbers for MSI

The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware
that has some memory mapped locations that can trigger traditional SPI
interrupts. This allows some basic PCIe MSI capabilities.

Setup the SPI range that is mapped by the MSI window. This range is
described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is
described as "GICv2m PCI Express MSI". In the future when these tables
are generated programmatically the information may be found in the
MSI_TYPER register as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18723 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
index d63a19b3904a62a2e460b18944d7c2f637a2f59b..0a167d3ac0183766392fa2d6996ed2667a0e1251 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
+++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
@@ -119,7 +119,8 @@
           0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
     },\r
     EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),\r
-    EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, 0, 0)\r
+    // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)\r
+    EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)\r
   };\r
 #endif\r
 \r

diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
index 9928c5ae7a89ea725895c589b3d5f7f40fc74733..d01d1367f9d3c04b8dd0716ec45e755ac093bd46 100644 (file)
--- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
@@ -40,9 +40,14 @@
 #define ARM_JUNO_PERIPHERALS_BASE             0x20000000\r
 #define ARM_JUNO_PERIPHERALS_SZ               0x0E000000\r
 \r
+// PCIe MSI address window\r
 #define ARM_JUNO_GIV2M_MSI_BASE               0x2c1c0000\r
 #define ARM_JUNO_GIV2M_MSI_SZ                 SIZE_256KB\r
 \r
+// PCIe MSI to SPI mapping range\r
+#define ARM_JUNO_GIV2M_MSI_SPI_BASE           224\r
+#define ARM_JUNO_GIV2M_MSI_SPI_COUNT          127 //TRM says last SPI is 351, 351-224=127\r
+\r
 // On-Chip non-secure SRAM\r
 #define ARM_JUNO_NON_SECURE_SRAM_BASE         0x2E000000\r
 #define ARM_JUNO_NON_SECURE_SRAM_SZ           SIZE_16MB\r