REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537
Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register
accesses from being split up into 8-bit accesses.
The SDHCI specification states that the registers shall be accessible in
byte, word, and double word accesses. (SD Host Controller Simplified
Specification 4.20 Section 1.2)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
)\r
{\r
EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL_WIDTH Width;\r
\r
if ((PciIo == NULL) || (Data == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r
- return EFI_INVALID_PARAMETER;\r
+ switch (Count) {\r
+ case 1:\r
+ Width = EfiPciIoWidthUint8;\r
+ break;\r
+ case 2:\r
+ Width = EfiPciIoWidthUint16;\r
+ Count = 1;\r
+ break;\r
+ case 4:\r
+ Width = EfiPciIoWidthUint32;\r
+ Count = 1;\r
+ break;\r
+ case 8:\r
+ Width = EfiPciIoWidthUint32;\r
+ Count = 2;\r
+ break;\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
if (Read) {\r
Status = PciIo->Mem.Read (\r
PciIo,\r
- EfiPciIoWidthUint8,\r
+ Width,\r
BarIndex,\r
(UINT64) Offset,\r
Count,\r
} else {\r
Status = PciIo->Mem.Write (\r
PciIo,\r
- EfiPciIoWidthUint8,\r
+ Width,\r
BarIndex,\r
(UINT64) Offset,\r
Count,\r