- @todo function comment is missing 'Routine Description:'\r
- @todo function comment is missing 'Arguments:'\r
- @todo function comment is missing 'Returns:'\r
- @todo Packet - add argument and description to function comment\r
- @todo EFI_INVALID_PARAMETER - add return value to function comment\r
- @todo EFI_INVALID_PARAMETER - add return value to function comment\r
- @todo EFI_INVALID_PARAMETER - add return value to function comment\r
- @todo EFI_UNSUPPORTED - add return value to function comment\r
- @todo EFI_SUCCESS - add return value to function comment\r
-**/\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0,\r
+ sizeof (PciData),\r
+ &PciData\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((PciData.Hdr.ClassCode[0] & IDE_PRIMARY_OPERATING_MODE) == 0) {\r
+ IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr = 0x1f0;\r
+ IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr = 0x3f6;\r
+ } else {\r
+ //\r
+ // The BARs should be of IO type\r
+ //\r
+ if ((PciData.Device.Bar[0] & BIT0) == 0 || \r
+ (PciData.Device.Bar[1] & BIT0) == 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ IdeRegsBaseAddr[IdePrimary].CommandBlockBaseAddr =\r
+ (UINT16) (PciData.Device.Bar[0] & 0x0000fff8);\r
+ IdeRegsBaseAddr[IdePrimary].ControlBlockBaseAddr =\r
+ (UINT16) ((PciData.Device.Bar[1] & 0x0000fffc) + 2);\r
+ }\r
+\r
+ if ((PciData.Hdr.ClassCode[0] & IDE_SECONDARY_OPERATING_MODE) == 0) {\r
+ IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr = 0x170;\r
+ IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr = 0x376;\r
+ } else {\r
+ //\r
+ // The BARs should be of IO type\r
+ //\r
+ if ((PciData.Device.Bar[2] & BIT0) == 0 ||\r
+ (PciData.Device.Bar[3] & BIT0) == 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ IdeRegsBaseAddr[IdeSecondary].CommandBlockBaseAddr =\r
+ (UINT16) (PciData.Device.Bar[2] & 0x0000fff8);\r
+ IdeRegsBaseAddr[IdeSecondary].ControlBlockBaseAddr =\r
+ (UINT16) ((PciData.Device.Bar[3] & 0x0000fffc) + 2);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+InitAtapiIoPortRegisters (\r
+ IN ATAPI_SCSI_PASS_THRU_DEV *AtapiScsiPrivate,\r
+ IN IDE_REGISTERS_BASE_ADDR *IdeRegsBaseAddr\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initialize each Channel's Base Address of CommandBlock and ControlBlock.\r
+\r
+Arguments:\r
+ \r
+ AtapiScsiPrivate - The pointer of ATAPI_SCSI_PASS_THRU_DEV\r
+ IdeRegsBaseAddr - The pointer of IDE_REGISTERS_BASE_ADDR\r
+ \r
+Returns:\r
+ \r
+ None\r
+\r
+--*/ \r
+{\r
+ \r
+ UINT8 IdeChannel;\r
+ UINT16 CommandBlockBaseAddr;\r
+ UINT16 ControlBlockBaseAddr;\r
+ IDE_BASE_REGISTERS *RegisterPointer;\r
+\r
+ \r
+ for (IdeChannel = 0; IdeChannel < ATAPI_MAX_CHANNEL; IdeChannel++) {\r
+\r
+ RegisterPointer = &AtapiScsiPrivate->AtapiIoPortRegisters[IdeChannel];\r
+\r
+ //\r
+ // Initialize IDE IO port addresses, including Command Block registers\r
+ // and Control Block registers\r
+ //\r
+ CommandBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].CommandBlockBaseAddr;\r
+ ControlBlockBaseAddr = IdeRegsBaseAddr[IdeChannel].ControlBlockBaseAddr;\r
+ \r
+ RegisterPointer->Data = CommandBlockBaseAddr;\r
+ (*(UINT16 *) &RegisterPointer->Reg1) = (UINT16) (CommandBlockBaseAddr + 0x01);\r
+ RegisterPointer->SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);\r
+ RegisterPointer->SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);\r
+ RegisterPointer->CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);\r
+ RegisterPointer->CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);\r
+ RegisterPointer->Head = (UINT16) (CommandBlockBaseAddr + 0x06);\r
+ (*(UINT16 *) &RegisterPointer->Reg) = (UINT16) (CommandBlockBaseAddr + 0x07);\r
+ \r
+ (*(UINT16 *) &RegisterPointer->Alt) = ControlBlockBaseAddr;\r
+ RegisterPointer->DriveAddress = (UINT16) (ControlBlockBaseAddr + 0x01);\r
+ }\r
+\r
+}\r
+\r
+ \r