The function ArmReadMidr has been recently added, but that functionality was
already present under other names such as Cp15IdCode and ArmMainIdCode. This
change removes redundant code and moves the function to the Common library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276
6f19259b-4bc3-4df7-8a09-
765794883524
-UINT32\r
-EFIAPI\r
-Cp15IdCode (\r
- VOID\r
- );\r
- \r
UINT32\r
EFIAPI\r
Cp15CacheInfo (\r
UINT32\r
EFIAPI\r
Cp15CacheInfo (\r
GCC_ASM_EXPORT (ArmCallWFI)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
GCC_ASM_EXPORT (ArmCallWFI)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
mrs x0, mpidr_el1 // read EL1 MPIDR\r
ret\r
\r
mrs x0, mpidr_el1 // read EL1 MPIDR\r
ret\r
\r
-ASM_PFX(ArmReadMidr):\r
- mrs x0, midr_el1 // Read Main ID Register\r
- ret\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
ASM_PFX(ArmReadTpidrurw):\r
\r
// Keep old function names for C compatibilty for now. Change later?\r
ASM_PFX(ArmReadTpidrurw):\r
GCC_ASM_EXPORT(ArmIsMpCore)\r
GCC_ASM_EXPORT(ArmCallWFI)\r
GCC_ASM_EXPORT(ArmReadMpidr)\r
GCC_ASM_EXPORT(ArmIsMpCore)\r
GCC_ASM_EXPORT(ArmCallWFI)\r
GCC_ASM_EXPORT(ArmReadMpidr)\r
-GCC_ASM_EXPORT(ArmReadMidr)\r
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
GCC_ASM_EXPORT(ArmEnableFiq)\r
GCC_ASM_EXPORT(ArmDisableFiq)\r
GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
GCC_ASM_EXPORT(ArmEnableFiq)\r
GCC_ASM_EXPORT(ArmDisableFiq)\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
\r
-ASM_PFX(ArmReadMpidr):\r
- mrc p15, 0, r0, c0, c0, 0 @ Read Main ID Register\r
- bx lr\r
-\r
ASM_PFX(ArmEnableFiq):\r
mrs R0,CPSR\r
bic R0,R0,#0x40 @Enable FIQ interrupts\r
ASM_PFX(ArmEnableFiq):\r
mrs R0,CPSR\r
bic R0,R0,#0x40 @Enable FIQ interrupts\r
GCC_ASM_EXPORT (ArmReadCbar)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
GCC_ASM_EXPORT (ArmReadCbar)\r
GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
-GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
GCC_ASM_EXPORT (ArmIsArchTimerImplemented)\r
ASM_PFX(ArmReadMpidr):\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
ASM_PFX(ArmReadMpidr):\r
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
bx lr\r
-\r
-ASM_PFX(ArmReadMidr):\r
- mrc p15, 0, r0, c0, c0, 0 @ Read Main ID Register\r
- bx lr\r
-\r
ASM_PFX(ArmReadTpidrurw):\r
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
bx lr\r
ASM_PFX(ArmReadTpidrurw):\r
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW\r
bx lr\r
EXPORT ArmReadCbar\r
EXPORT ArmInvalidateInstructionAndDataTlb\r
EXPORT ArmReadMpidr\r
EXPORT ArmReadCbar\r
EXPORT ArmInvalidateInstructionAndDataTlb\r
EXPORT ArmReadMpidr\r
EXPORT ArmReadTpidrurw\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
EXPORT ArmReadTpidrurw\r
EXPORT ArmWriteTpidrurw\r
EXPORT ArmIsArchTimerImplemented\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
\r
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR\r
bx lr\r
\r
-ArmReadMidr\r
- mrc p15, 0, r0, c0, c0, 0 ; Read Main ID Register\r
- bx lr\r
-\r
ArmReadTpidrurw\r
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
bx lr\r
ArmReadTpidrurw\r
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW\r
bx lr\r
-GCC_ASM_EXPORT (ArmMainIdCode)\r
+GCC_ASM_EXPORT (ArmReadMidr)\r
GCC_ASM_EXPORT (ArmCacheInfo)\r
GCC_ASM_EXPORT (ArmGetInterruptState)\r
GCC_ASM_EXPORT (ArmGetFiqState)\r
GCC_ASM_EXPORT (ArmCacheInfo)\r
GCC_ASM_EXPORT (ArmGetInterruptState)\r
GCC_ASM_EXPORT (ArmGetFiqState)\r
.set DAIF_FIQ_BIT, (1 << 0)\r
.set DAIF_IRQ_BIT, (1 << 1)\r
\r
.set DAIF_FIQ_BIT, (1 << 0)\r
.set DAIF_IRQ_BIT, (1 << 1)\r
\r
-ASM_PFX(ArmiMainIdCode):\r
mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
ret\r
\r
mrs x0, midr_el1 // Read from Main ID Register (MIDR)\r
ret\r
\r
#------------------------------------------------------------------------------ \r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
#------------------------------------------------------------------------------ \r
#\r
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
-GCC_ASM_EXPORT(Cp15IdCode)\r
+GCC_ASM_EXPORT(ArmReadMidr)\r
GCC_ASM_EXPORT(Cp15CacheInfo)\r
GCC_ASM_EXPORT(ArmGetInterruptState)\r
GCC_ASM_EXPORT(ArmGetFiqState)\r
GCC_ASM_EXPORT(Cp15CacheInfo)\r
GCC_ASM_EXPORT(ArmGetInterruptState)\r
GCC_ASM_EXPORT(ArmGetFiqState)\r
\r
#------------------------------------------------------------------------------\r
\r
\r
#------------------------------------------------------------------------------\r
\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
//------------------------------------------------------------------------------ \r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
//------------------------------------------------------------------------------ \r
//\r
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
//\r
// This program and the accompanying materials\r
// are licensed and made available under the terms and conditions of the BSD License\r
#define dsb\r
#endif\r
\r
#define dsb\r
#endif\r
\r
EXPORT Cp15CacheInfo\r
EXPORT ArmGetInterruptState\r
EXPORT ArmGetFiqState\r
EXPORT Cp15CacheInfo\r
EXPORT ArmGetInterruptState\r
EXPORT ArmGetFiqState\r
\r
AREA ArmLibSupport, CODE, READONLY\r
\r
\r
AREA ArmLibSupport, CODE, READONLY\r
\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r
mrc p15,0,R0,c0,c0,0\r
bx LR\r
\r