--- /dev/null
+/** @file Lcd.c\r
+\r
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/LcdPlatformLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include <Drivers/HdLcd.h>\r
+\r
+#include "LcdGraphicsOutputDxe.h"\r
+\r
+/**********************************************************************\r
+ *\r
+ * This file contains all the bits of the Lcd that are\r
+ * platform independent.\r
+ *\r
+ **********************************************************************/\r
+\r
+EFI_STATUS\r
+LcdInitialize (\r
+ IN EFI_PHYSICAL_ADDRESS VramBaseAddress\r
+ )\r
+{\r
+ // Disable the controller\r
+ MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);\r
+\r
+ // Disable all interrupts\r
+ MmioWrite32(HDLCD_REG_INT_MASK, 0);\r
+\r
+ // Define start of the VRAM. This never changes for any graphics mode\r
+ MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);\r
+\r
+ // Setup various registers that never change\r
+ MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);\r
+ MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);\r
+ MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);\r
+ MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));\r
+ MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));\r
+ MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+LcdSetMode (\r
+ IN UINT32 ModeNumber\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 HRes;\r
+ UINT32 HSync;\r
+ UINT32 HBackPorch;\r
+ UINT32 HFrontPorch;\r
+ UINT32 VRes;\r
+ UINT32 VSync;\r
+ UINT32 VBackPorch;\r
+ UINT32 VFrontPorch;\r
+ UINT32 BytesPerPixel;\r
+ LCD_BPP LcdBpp;\r
+\r
+\r
+ // Set the video mode timings and other relevant information\r
+ Status = LcdPlatformGetTimings (ModeNumber,\r
+ &HRes,&HSync,&HBackPorch,&HFrontPorch,\r
+ &VRes,&VSync,&VBackPorch,&VFrontPorch);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (EFI_ERROR( Status )) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (EFI_ERROR( Status )) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ BytesPerPixel = GetBytesPerPixel(LcdBpp);\r
+\r
+ // Disable the controller\r
+ MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);\r
+\r
+ // Update the frame buffer information with the new settings\r
+ MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);\r
+ MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);\r
+ MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);\r
+\r
+ // Set the vertical timing information\r
+ MmioWrite32(HDLCD_REG_V_SYNC, VSync);\r
+ MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);\r
+ MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);\r
+ MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);\r
+\r
+ // Set the horizontal timing information\r
+ MmioWrite32(HDLCD_REG_H_SYNC, HSync);\r
+ MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);\r
+ MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);\r
+ MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);\r
+\r
+ // Enable the controller\r
+ MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+LcdShutdown (\r
+ VOID\r
+ )\r
+{\r
+ // Nothing to do in terms of hardware.\r
+ // We could switch off the monitor display if required\r
+}\r
--- /dev/null
+#/** @file\r
+# \r
+# Component description file for HDLCD module\r
+# \r
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+# \r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = HdLcdGraphicsDxe\r
+ FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = LcdGraphicsOutputDxeInitialize\r
+\r
+[Sources.common]\r
+ LcdGraphicsOutputDxe.c\r
+ LcdGraphicsOutputBlt.c\r
+ HdLcd.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ ArmLib\r
+ UefiLib\r
+ BaseLib\r
+ DebugLib\r
+ TimerLib\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ IoLib\r
+ BaseMemoryLib\r
+ LcdPlatformLib\r
+\r
+[Protocols]\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiGraphicsOutputProtocolGuid # Produced\r
+ gEfiEdidDiscoveredProtocolGuid # Produced\r
+ gEfiEdidActiveProtocolGuid # Produced\r
+ gEfiEdidOverrideProtocolGuid # Produced \r
+\r
+[FixedPcd]\r
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\r
+\r
+[Depex]\r
+ gEfiCpuArchProtocolGuid\r
--- /dev/null
+/** @file HDLcd.h\r
+\r
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ **/\r
+\r
+#ifndef _HDLCD_H_\r
+#define _HDLCD_H_\r
+\r
+//\r
+// HDLCD Controller Register Offsets\r
+//\r
+\r
+#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
+#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
+#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
+#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
+#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
+#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
+#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
+#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
+#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
+#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
+#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
+#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
+#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
+#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
+#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
+#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
+#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
+#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
+#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
+#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
+#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
+#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
+#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
+#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
+\r
+\r
+//\r
+// HDLCD Values of registers\r
+//\r
+\r
+// HDLCD Interrupt mask, clear and status register\r
+#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */\r
+#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */\r
+#define HDLCD_SYNC BIT2 /* Vertical sync */\r
+#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */\r
+\r
+// CLCD_CONTROL Control register\r
+#define HDLCD_DISABLE 0\r
+#define HDLCD_ENABLE BIT0\r
+\r
+// Bus Options\r
+#define HDLCD_BURST_1 BIT0\r
+#define HDLCD_BURST_2 BIT1\r
+#define HDLCD_BURST_4 BIT2\r
+#define HDLCD_BURST_8 BIT3\r
+#define HDLCD_BURST_16 BIT4\r
+\r
+// Polarities - HIGH\r
+#define HDLCD_VSYNC_HIGH BIT0\r
+#define HDLCD_HSYNC_HIGH BIT1\r
+#define HDLCD_DATEN_HIGH BIT2\r
+#define HDLCD_DATA_HIGH BIT3\r
+#define HDLCD_PXCLK_HIGH BIT4\r
+// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
+#define HDLCD_VSYNC_LOW 0\r
+#define HDLCD_HSYNC_LOW 0\r
+#define HDLCD_DATEN_LOW 0\r
+#define HDLCD_DATA_LOW 0\r
+#define HDLCD_PXCLK_LOW 0\r
+\r
+// Pixel Format\r
+#define HDLCD_LITTLE_ENDIAN (0 << 31)\r
+#define HDLCD_BIG_ENDIAN (1 << 31)\r
+\r
+// Number of bytes per pixel\r
+#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)\r
+\r
+#endif /* _HDLCD_H_ */\r
projects / mirror_edk2.git / commitdiff