]> git.proxmox.com Git - mirror_edk2.git/commitdiff
MdeModulePkg/PciHostBridgeDxe: Fix a Base/Limit comparing bug
authorRuiyu Ni <ruiyu.ni@intel.com>
Fri, 29 Apr 2016 09:38:51 +0000 (17:38 +0800)
committerRuiyu Ni <ruiyu.ni@intel.com>
Wed, 11 May 2016 00:53:36 +0000 (08:53 +0800)
When the aperture base equals to aperture limit, the old code treats
the aperture as non-existent. It's not correct because it indicates
a range starting with base and the length is 1.
The new code corrects the comparing bug.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

index 50f1407e7aeac57783a9183e380da08d8a4248bf..07ed54b08e1305d47f85226e1e5f6dd02c0210c8 100644 (file)
@@ -393,7 +393,7 @@ InitializePciHostBridge (
       continue;\r
     }\r
 \r
-    if (RootBridges[Index].Io.Limit > RootBridges[Index].Io.Base) {\r
+    if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) {\r
       Status = AddIoSpace (\r
                  RootBridges[Index].Io.Base,\r
                  RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1\r
@@ -413,7 +413,7 @@ InitializePciHostBridge (
     MemApertures[3] = &RootBridges[Index].PMemAbove4G;\r
 \r
     for (MemApertureIndex = 0; MemApertureIndex < sizeof (MemApertures) / sizeof (MemApertures[0]); MemApertureIndex++) {\r
-      if (MemApertures[MemApertureIndex]->Limit > MemApertures[MemApertureIndex]->Base) {\r
+      if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) {\r
         Status = AddMemoryMappedIoSpace (\r
                    MemApertures[MemApertureIndex]->Base,\r
                    MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,\r
index 9f756e4c56f73532bd589b34d10260567c73456e..dbb415ac2d6e12764c33ffa6af4e78bf68ca8c78 100644 (file)
@@ -95,25 +95,25 @@ CreateRootBridge (
   //\r
   // Make sure Mem and MemAbove4G apertures are valid\r
   //\r
-  if (Bridge->Mem.Base < Bridge->Mem.Limit) {\r
+  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {\r
     ASSERT (Bridge->Mem.Limit < SIZE_4GB);\r
     if (Bridge->Mem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) {\r
+  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {\r
     ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->MemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMem.Base < Bridge->PMem.Limit) {\r
+  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {\r
     ASSERT (Bridge->PMem.Limit < SIZE_4GB);\r
     if (Bridge->PMem.Limit >= SIZE_4GB) {\r
       return NULL;\r
     }\r
   }\r
-  if (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) {\r
+  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {\r
     ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);\r
     if (Bridge->PMemAbove4G.Base < SIZE_4GB) {\r
       return NULL;\r
@@ -126,10 +126,10 @@ CreateRootBridge (
     // support separate windows for Non-prefetchable and Prefetchable\r
     // memory.\r
     //\r
-    ASSERT (Bridge->PMem.Base >= Bridge->PMem.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->PMem.Base < Bridge->PMem.Limit) ||\r
-        (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
+    ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);\r
+    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+    if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||\r
+        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
         ) {\r
       return NULL;\r
     }\r
@@ -140,10 +140,10 @@ CreateRootBridge (
     // If this bit is not set, then the PCI Root Bridge does not support\r
     // 64 bit memory windows.\r
     //\r
-    ASSERT (Bridge->MemAbove4G.Base >= Bridge->MemAbove4G.Limit);\r
-    ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);\r
-    if ((Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) ||\r
-        (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)\r
+    ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);\r
+    ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);\r
+    if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||\r
+        (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)\r
         ) {\r
       return NULL;\r
     }\r