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Commit | Line | Data |
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356b230e SL |
1 | /* |
2 | * ASPEED Ast10x0 SoC | |
3 | * | |
4 | * Copyright (C) 2022 ASPEED Technology Inc. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | * Implementation extracted from the AST2600 and adapted for Ast10x0. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
13 | #include "qapi/error.h" | |
14 | #include "exec/address-spaces.h" | |
15 | #include "sysemu/sysemu.h" | |
16 | #include "hw/qdev-clock.h" | |
17 | #include "hw/misc/unimp.h" | |
356b230e SL |
18 | #include "hw/arm/aspeed_soc.h" |
19 | ||
20 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
21 | ||
22 | static const hwaddr aspeed_soc_ast1030_memmap[] = { | |
23 | [ASPEED_DEV_SRAM] = 0x00000000, | |
6ba3dc25 | 24 | [ASPEED_DEV_SECSRAM] = 0x79000000, |
356b230e SL |
25 | [ASPEED_DEV_IOMEM] = 0x7E600000, |
26 | [ASPEED_DEV_PWM] = 0x7E610000, | |
27 | [ASPEED_DEV_FMC] = 0x7E620000, | |
28 | [ASPEED_DEV_SPI1] = 0x7E630000, | |
29 | [ASPEED_DEV_SPI2] = 0x7E640000, | |
72006c61 | 30 | [ASPEED_DEV_UDC] = 0x7E6A2000, |
98fb9678 | 31 | [ASPEED_DEV_HACE] = 0x7E6D0000, |
356b230e | 32 | [ASPEED_DEV_SCU] = 0x7E6E2000, |
72006c61 PMD |
33 | [ASPEED_DEV_JTAG0] = 0x7E6E4000, |
34 | [ASPEED_DEV_JTAG1] = 0x7E6E4100, | |
356b230e | 35 | [ASPEED_DEV_ADC] = 0x7E6E9000, |
72006c61 | 36 | [ASPEED_DEV_ESPI] = 0x7E6EE000, |
356b230e SL |
37 | [ASPEED_DEV_SBC] = 0x7E6F2000, |
38 | [ASPEED_DEV_GPIO] = 0x7E780000, | |
72006c61 | 39 | [ASPEED_DEV_SGPIOM] = 0x7E780500, |
356b230e | 40 | [ASPEED_DEV_TIMER1] = 0x7E782000, |
ab5e8605 PD |
41 | [ASPEED_DEV_UART1] = 0x7E783000, |
42 | [ASPEED_DEV_UART2] = 0x7E78D000, | |
43 | [ASPEED_DEV_UART3] = 0x7E78E000, | |
44 | [ASPEED_DEV_UART4] = 0x7E78F000, | |
356b230e | 45 | [ASPEED_DEV_UART5] = 0x7E784000, |
ab5e8605 PD |
46 | [ASPEED_DEV_UART6] = 0x7E790000, |
47 | [ASPEED_DEV_UART7] = 0x7E790100, | |
48 | [ASPEED_DEV_UART8] = 0x7E790200, | |
49 | [ASPEED_DEV_UART9] = 0x7E790300, | |
50 | [ASPEED_DEV_UART10] = 0x7E790400, | |
51 | [ASPEED_DEV_UART11] = 0x7E790500, | |
52 | [ASPEED_DEV_UART12] = 0x7E790600, | |
53 | [ASPEED_DEV_UART13] = 0x7E790700, | |
356b230e SL |
54 | [ASPEED_DEV_WDT] = 0x7E785000, |
55 | [ASPEED_DEV_LPC] = 0x7E789000, | |
55c57023 | 56 | [ASPEED_DEV_PECI] = 0x7E78B000, |
29c4f060 | 57 | [ASPEED_DEV_I3C] = 0x7E7A0000, |
356b230e SL |
58 | [ASPEED_DEV_I2C] = 0x7E7B0000, |
59 | }; | |
60 | ||
61 | static const int aspeed_soc_ast1030_irqmap[] = { | |
ab5e8605 PD |
62 | [ASPEED_DEV_UART1] = 47, |
63 | [ASPEED_DEV_UART2] = 48, | |
64 | [ASPEED_DEV_UART3] = 49, | |
65 | [ASPEED_DEV_UART4] = 50, | |
356b230e | 66 | [ASPEED_DEV_UART5] = 8, |
ab5e8605 PD |
67 | [ASPEED_DEV_UART6] = 57, |
68 | [ASPEED_DEV_UART7] = 58, | |
69 | [ASPEED_DEV_UART8] = 59, | |
70 | [ASPEED_DEV_UART9] = 60, | |
71 | [ASPEED_DEV_UART10] = 61, | |
72 | [ASPEED_DEV_UART11] = 62, | |
73 | [ASPEED_DEV_UART12] = 63, | |
74 | [ASPEED_DEV_UART13] = 64, | |
356b230e SL |
75 | [ASPEED_DEV_GPIO] = 11, |
76 | [ASPEED_DEV_TIMER1] = 16, | |
77 | [ASPEED_DEV_TIMER2] = 17, | |
78 | [ASPEED_DEV_TIMER3] = 18, | |
79 | [ASPEED_DEV_TIMER4] = 19, | |
80 | [ASPEED_DEV_TIMER5] = 20, | |
81 | [ASPEED_DEV_TIMER6] = 21, | |
82 | [ASPEED_DEV_TIMER7] = 22, | |
83 | [ASPEED_DEV_TIMER8] = 23, | |
84 | [ASPEED_DEV_WDT] = 24, | |
85 | [ASPEED_DEV_LPC] = 35, | |
55c57023 | 86 | [ASPEED_DEV_PECI] = 38, |
356b230e | 87 | [ASPEED_DEV_FMC] = 39, |
72006c61 | 88 | [ASPEED_DEV_ESPI] = 42, |
356b230e SL |
89 | [ASPEED_DEV_PWM] = 44, |
90 | [ASPEED_DEV_ADC] = 46, | |
91 | [ASPEED_DEV_SPI1] = 65, | |
92 | [ASPEED_DEV_SPI2] = 66, | |
29c4f060 | 93 | [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */ |
356b230e SL |
94 | [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */ |
95 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ | |
72006c61 PMD |
96 | [ASPEED_DEV_UDC] = 9, |
97 | [ASPEED_DEV_SGPIOM] = 51, | |
98 | [ASPEED_DEV_JTAG0] = 27, | |
99 | [ASPEED_DEV_JTAG1] = 53, | |
356b230e SL |
100 | }; |
101 | ||
699db715 | 102 | static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) |
356b230e | 103 | { |
a0c21030 | 104 | Aspeed10x0SoCState *a = ASPEED10X0_SOC(s); |
356b230e SL |
105 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
106 | ||
a0c21030 | 107 | return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); |
356b230e SL |
108 | } |
109 | ||
110 | static void aspeed_soc_ast1030_init(Object *obj) | |
111 | { | |
a0c21030 | 112 | Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj); |
356b230e SL |
113 | AspeedSoCState *s = ASPEED_SOC(obj); |
114 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
115 | char socname[8]; | |
116 | char typename[64]; | |
117 | int i; | |
118 | ||
119 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
120 | g_assert_not_reached(); | |
121 | } | |
122 | ||
a0c21030 | 123 | object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); |
356b230e SL |
124 | |
125 | s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); | |
126 | ||
127 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
128 | object_initialize_child(obj, "scu", &s->scu, typename); | |
129 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); | |
130 | ||
131 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1"); | |
132 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2"); | |
133 | ||
4c70ab16 TL |
134 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
135 | object_initialize_child(obj, "i2c", &s->i2c, typename); | |
136 | ||
29c4f060 PMD |
137 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); |
138 | ||
356b230e SL |
139 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); |
140 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); | |
141 | ||
142 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); | |
143 | object_initialize_child(obj, "adc", &s->adc, typename); | |
144 | ||
145 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
146 | object_initialize_child(obj, "fmc", &s->fmc, typename); | |
147 | ||
148 | for (i = 0; i < sc->spis_num; i++) { | |
149 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
150 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); | |
151 | } | |
152 | ||
153 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
154 | ||
55c57023 PD |
155 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
156 | ||
356b230e SL |
157 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); |
158 | ||
159 | for (i = 0; i < sc->wdts_num; i++) { | |
160 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
161 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); | |
162 | } | |
17075ef2 | 163 | |
d2b3eaef PD |
164 | for (i = 0; i < sc->uarts_num; i++) { |
165 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); | |
166 | } | |
167 | ||
17075ef2 JL |
168 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); |
169 | object_initialize_child(obj, "gpio", &s->gpio, typename); | |
80beb085 | 170 | |
98fb9678 PMD |
171 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); |
172 | object_initialize_child(obj, "hace", &s->hace, typename); | |
173 | ||
80beb085 PD |
174 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); |
175 | object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented, | |
176 | TYPE_UNIMPLEMENTED_DEVICE); | |
72006c61 PMD |
177 | object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); |
178 | object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE); | |
179 | object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE); | |
180 | object_initialize_child(obj, "sgpiom", &s->sgpiom, | |
181 | TYPE_UNIMPLEMENTED_DEVICE); | |
182 | object_initialize_child(obj, "jtag[0]", &s->jtag[0], | |
183 | TYPE_UNIMPLEMENTED_DEVICE); | |
184 | object_initialize_child(obj, "jtag[1]", &s->jtag[1], | |
185 | TYPE_UNIMPLEMENTED_DEVICE); | |
356b230e SL |
186 | } |
187 | ||
188 | static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) | |
189 | { | |
a0c21030 | 190 | Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc); |
356b230e SL |
191 | AspeedSoCState *s = ASPEED_SOC(dev_soc); |
192 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
356b230e SL |
193 | DeviceState *armv7m; |
194 | Error *err = NULL; | |
195 | int i; | |
72a7c473 | 196 | g_autofree char *sram_name = NULL; |
356b230e SL |
197 | |
198 | if (!clock_has_source(s->sysclk)) { | |
199 | error_setg(errp, "sysclk clock must be wired up by the board code"); | |
200 | return; | |
201 | } | |
202 | ||
203 | /* General I/O memory space to catch all unimplemented device */ | |
80beb085 PD |
204 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", |
205 | sc->memmap[ASPEED_DEV_IOMEM], | |
206 | ASPEED_SOC_IOMEM_SIZE); | |
207 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented), | |
208 | "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], | |
209 | 0x40000); | |
356b230e SL |
210 | |
211 | /* AST1030 CPU Core */ | |
a0c21030 | 212 | armv7m = DEVICE(&a->armv7m); |
356b230e | 213 | qdev_prop_set_uint32(armv7m, "num-irq", 256); |
d815649c | 214 | qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); |
356b230e | 215 | qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); |
a0c21030 | 216 | object_property_set_link(OBJECT(&a->armv7m), "memory", |
4dd9d554 | 217 | OBJECT(s->memory), &error_abort); |
a0c21030 | 218 | sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); |
356b230e SL |
219 | |
220 | /* Internal SRAM */ | |
72a7c473 | 221 | sram_name = g_strdup_printf("aspeed.sram.%d", |
a0c21030 | 222 | CPU(a->armv7m.cpu)->cpu_index); |
72a7c473 | 223 | memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); |
356b230e SL |
224 | if (err != NULL) { |
225 | error_propagate(errp, err); | |
226 | return; | |
227 | } | |
4dd9d554 | 228 | memory_region_add_subregion(s->memory, |
356b230e SL |
229 | sc->memmap[ASPEED_DEV_SRAM], |
230 | &s->sram); | |
6ba3dc25 PMD |
231 | memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram", |
232 | sc->secsram_size, &err); | |
233 | if (err != NULL) { | |
234 | error_propagate(errp, err); | |
235 | return; | |
236 | } | |
237 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], | |
238 | &s->secsram); | |
356b230e SL |
239 | |
240 | /* SCU */ | |
241 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { | |
242 | return; | |
243 | } | |
5bfcbda7 | 244 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
356b230e | 245 | |
4c70ab16 TL |
246 | /* I2C */ |
247 | ||
248 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), | |
249 | &error_abort); | |
250 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { | |
251 | return; | |
252 | } | |
5bfcbda7 | 253 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
4c70ab16 | 254 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
a0c21030 | 255 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), |
4c70ab16 TL |
256 | sc->irqmap[ASPEED_DEV_I2C] + i); |
257 | /* The AST1030 I2C controller has one IRQ per bus. */ | |
258 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
259 | } | |
260 | ||
29c4f060 PMD |
261 | /* I3C */ |
262 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { | |
263 | return; | |
264 | } | |
265 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); | |
266 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { | |
a0c21030 | 267 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), |
29c4f060 PMD |
268 | sc->irqmap[ASPEED_DEV_I3C] + i); |
269 | /* The AST1030 I3C controller has one IRQ per bus. */ | |
270 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | |
271 | } | |
272 | ||
55c57023 PD |
273 | /* PECI */ |
274 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { | |
275 | return; | |
276 | } | |
277 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, | |
278 | sc->memmap[ASPEED_DEV_PECI]); | |
279 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, | |
280 | aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); | |
281 | ||
356b230e SL |
282 | /* LPC */ |
283 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
284 | return; | |
285 | } | |
5bfcbda7 | 286 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); |
356b230e SL |
287 | |
288 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
289 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, | |
290 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
291 | ||
292 | /* | |
293 | * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. | |
294 | */ | |
295 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
a0c21030 | 296 | qdev_get_gpio_in(DEVICE(&a->armv7m), |
356b230e SL |
297 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); |
298 | ||
299 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
a0c21030 | 300 | qdev_get_gpio_in(DEVICE(&a->armv7m), |
356b230e SL |
301 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); |
302 | ||
303 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
a0c21030 | 304 | qdev_get_gpio_in(DEVICE(&a->armv7m), |
356b230e SL |
305 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); |
306 | ||
307 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
a0c21030 | 308 | qdev_get_gpio_in(DEVICE(&a->armv7m), |
356b230e SL |
309 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); |
310 | ||
470253b6 | 311 | /* UART */ |
d2b3eaef PD |
312 | if (!aspeed_soc_uart_realize(s, errp)) { |
313 | return; | |
314 | } | |
356b230e SL |
315 | |
316 | /* Timer */ | |
317 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), | |
318 | &error_abort); | |
319 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { | |
320 | return; | |
321 | } | |
5bfcbda7 | 322 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, |
356b230e SL |
323 | sc->memmap[ASPEED_DEV_TIMER1]); |
324 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | |
325 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); | |
326 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
327 | } | |
328 | ||
329 | /* ADC */ | |
330 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
331 | return; | |
332 | } | |
5bfcbda7 | 333 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); |
356b230e SL |
334 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
335 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
336 | ||
337 | /* FMC, The number of CS is set at the board level */ | |
338 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), | |
339 | &error_abort); | |
340 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { | |
341 | return; | |
342 | } | |
5bfcbda7 PD |
343 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
344 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, | |
356b230e SL |
345 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
346 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | |
347 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); | |
348 | ||
349 | /* SPI */ | |
350 | for (i = 0; i < sc->spis_num; i++) { | |
351 | object_property_set_link(OBJECT(&s->spi[i]), "dram", | |
352 | OBJECT(&s->sram), &error_abort); | |
353 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { | |
354 | return; | |
355 | } | |
5bfcbda7 | 356 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, |
356b230e | 357 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
5bfcbda7 | 358 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, |
356b230e SL |
359 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
360 | } | |
361 | ||
362 | /* Secure Boot Controller */ | |
363 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
364 | return; | |
365 | } | |
5bfcbda7 | 366 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); |
356b230e | 367 | |
98fb9678 PMD |
368 | /* HACE */ |
369 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), | |
370 | &error_abort); | |
371 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
372 | return; | |
373 | } | |
374 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, | |
375 | sc->memmap[ASPEED_DEV_HACE]); | |
376 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
377 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
378 | ||
356b230e SL |
379 | /* Watch dog */ |
380 | for (i = 0; i < sc->wdts_num; i++) { | |
381 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
6fdb4381 | 382 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
356b230e SL |
383 | |
384 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), | |
385 | &error_abort); | |
386 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { | |
387 | return; | |
388 | } | |
6fdb4381 | 389 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
356b230e | 390 | } |
17075ef2 JL |
391 | |
392 | /* GPIO */ | |
393 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { | |
394 | return; | |
395 | } | |
5bfcbda7 PD |
396 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, |
397 | sc->memmap[ASPEED_DEV_GPIO]); | |
17075ef2 JL |
398 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
399 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); | |
72006c61 PMD |
400 | |
401 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", | |
402 | sc->memmap[ASPEED_DEV_PWM], 0x100); | |
403 | ||
404 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi", | |
405 | sc->memmap[ASPEED_DEV_ESPI], 0x800); | |
406 | ||
407 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc", | |
408 | sc->memmap[ASPEED_DEV_UDC], 0x1000); | |
409 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom", | |
410 | sc->memmap[ASPEED_DEV_SGPIOM], 0x100); | |
411 | ||
412 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag", | |
413 | sc->memmap[ASPEED_DEV_JTAG0], 0x20); | |
414 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", | |
415 | sc->memmap[ASPEED_DEV_JTAG1], 0x20); | |
356b230e SL |
416 | } |
417 | ||
418 | static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) | |
419 | { | |
420 | DeviceClass *dc = DEVICE_CLASS(klass); | |
421 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); | |
422 | ||
423 | dc->realize = aspeed_soc_ast1030_realize; | |
424 | ||
425 | sc->name = "ast1030-a1"; | |
f16c27a5 | 426 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ |
356b230e SL |
427 | sc->silicon_rev = AST1030_A1_SILICON_REV; |
428 | sc->sram_size = 0xc0000; | |
6ba3dc25 | 429 | sc->secsram_size = 0x40000; /* 256 * KiB */ |
356b230e SL |
430 | sc->spis_num = 2; |
431 | sc->ehcis_num = 0; | |
432 | sc->wdts_num = 4; | |
433 | sc->macs_num = 1; | |
c5e1bdb9 | 434 | sc->uarts_num = 13; |
356b230e SL |
435 | sc->irqmap = aspeed_soc_ast1030_irqmap; |
436 | sc->memmap = aspeed_soc_ast1030_memmap; | |
437 | sc->num_cpus = 1; | |
699db715 | 438 | sc->get_irq = aspeed_soc_ast1030_get_irq; |
356b230e SL |
439 | } |
440 | ||
df4ab076 PMD |
441 | static const TypeInfo aspeed_soc_ast10x0_types[] = { |
442 | { | |
443 | .name = TYPE_ASPEED10X0_SOC, | |
444 | .parent = TYPE_ASPEED_SOC, | |
445 | .instance_size = sizeof(Aspeed10x0SoCState), | |
446 | .abstract = true, | |
447 | }, { | |
448 | .name = "ast1030-a1", | |
449 | .parent = TYPE_ASPEED10X0_SOC, | |
450 | .instance_init = aspeed_soc_ast1030_init, | |
451 | .class_init = aspeed_soc_ast1030_class_init, | |
452 | }, | |
356b230e SL |
453 | }; |
454 | ||
df4ab076 | 455 | DEFINE_TYPES(aspeed_soc_ast10x0_types) |