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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
12 | #include "cpu.h" | |
13 | #include "exec/address-spaces.h" | |
14 | #include "hw/misc/unimp.h" | |
15 | #include "hw/arm/aspeed_soc.h" | |
16 | #include "hw/char/serial.h" | |
17 | #include "qemu/log.h" | |
18 | #include "qemu/module.h" | |
19 | #include "qemu/error-report.h" | |
20 | #include "hw/i2c/aspeed_i2c.h" | |
21 | #include "net/net.h" | |
22 | #include "sysemu/sysemu.h" | |
23 | ||
24 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
25 | ||
26 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
347df6f8 | 27 | [ASPEED_DEV_SRAM] = 0x10000000, |
f25c0ae1 | 28 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
29 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
30 | [ASPEED_DEV_PWM] = 0x1E610000, | |
31 | [ASPEED_DEV_FMC] = 0x1E620000, | |
32 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
33 | [ASPEED_DEV_SPI2] = 0x1E641000, | |
34 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, | |
35 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
36 | [ASPEED_DEV_MII1] = 0x1E650000, | |
37 | [ASPEED_DEV_MII2] = 0x1E650008, | |
38 | [ASPEED_DEV_MII3] = 0x1E650010, | |
39 | [ASPEED_DEV_MII4] = 0x1E650018, | |
40 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
41 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
42 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
43 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
44 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 45 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
46 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
47 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
48 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
49 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
50 | [ASPEED_DEV_VIDEO] = 0x1E700000, | |
51 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
52 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
53 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
54 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
55 | [ASPEED_DEV_RTC] = 0x1E781000, | |
56 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
57 | [ASPEED_DEV_WDT] = 0x1E785000, | |
58 | [ASPEED_DEV_LPC] = 0x1E789000, | |
59 | [ASPEED_DEV_IBT] = 0x1E789140, | |
60 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
61 | [ASPEED_DEV_UART1] = 0x1E783000, | |
62 | [ASPEED_DEV_UART5] = 0x1E784000, | |
63 | [ASPEED_DEV_VUART] = 0x1E787000, | |
64 | [ASPEED_DEV_SDRAM] = 0x80000000, | |
f25c0ae1 CLG |
65 | }; |
66 | ||
67 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
68 | ||
b151de69 | 69 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 70 | |
a29e3e12 | 71 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 72 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
73 | [ASPEED_DEV_UART1] = 47, |
74 | [ASPEED_DEV_UART2] = 48, | |
75 | [ASPEED_DEV_UART3] = 49, | |
76 | [ASPEED_DEV_UART4] = 50, | |
77 | [ASPEED_DEV_UART5] = 8, | |
78 | [ASPEED_DEV_VUART] = 8, | |
79 | [ASPEED_DEV_FMC] = 39, | |
80 | [ASPEED_DEV_SDMC] = 0, | |
81 | [ASPEED_DEV_SCU] = 12, | |
82 | [ASPEED_DEV_ADC] = 78, | |
83 | [ASPEED_DEV_XDMA] = 6, | |
84 | [ASPEED_DEV_SDHCI] = 43, | |
85 | [ASPEED_DEV_EHCI1] = 5, | |
86 | [ASPEED_DEV_EHCI2] = 9, | |
87 | [ASPEED_DEV_EMMC] = 15, | |
88 | [ASPEED_DEV_GPIO] = 40, | |
89 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
90 | [ASPEED_DEV_RTC] = 13, | |
91 | [ASPEED_DEV_TIMER1] = 16, | |
92 | [ASPEED_DEV_TIMER2] = 17, | |
93 | [ASPEED_DEV_TIMER3] = 18, | |
94 | [ASPEED_DEV_TIMER4] = 19, | |
95 | [ASPEED_DEV_TIMER5] = 20, | |
96 | [ASPEED_DEV_TIMER6] = 21, | |
97 | [ASPEED_DEV_TIMER7] = 22, | |
98 | [ASPEED_DEV_TIMER8] = 23, | |
99 | [ASPEED_DEV_WDT] = 24, | |
100 | [ASPEED_DEV_PWM] = 44, | |
101 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 102 | [ASPEED_DEV_IBT] = 143, |
347df6f8 EH |
103 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
104 | [ASPEED_DEV_ETH1] = 2, | |
105 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 106 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
107 | [ASPEED_DEV_ETH3] = 32, |
108 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 109 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
f25c0ae1 CLG |
110 | }; |
111 | ||
112 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | |
113 | { | |
114 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
115 | ||
116 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | |
117 | } | |
118 | ||
119 | static void aspeed_soc_ast2600_init(Object *obj) | |
120 | { | |
121 | AspeedSoCState *s = ASPEED_SOC(obj); | |
122 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123 | int i; | |
124 | char socname[8]; | |
125 | char typename[64]; | |
126 | ||
127 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
128 | g_assert_not_reached(); | |
129 | } | |
130 | ||
131 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 132 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
133 | } |
134 | ||
135 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 136 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
137 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
138 | sc->silicon_rev); | |
139 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 140 | "hw-strap1"); |
f25c0ae1 | 141 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 142 | "hw-strap2"); |
f25c0ae1 | 143 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 144 | "hw-prot-key"); |
f25c0ae1 | 145 | |
db873cc5 MA |
146 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
147 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 148 | |
db873cc5 | 149 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
150 | |
151 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 152 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 CLG |
153 | |
154 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | |
db873cc5 | 155 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 CLG |
156 | |
157 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
db873cc5 | 158 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 159 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
f25c0ae1 CLG |
160 | |
161 | for (i = 0; i < sc->spis_num; i++) { | |
162 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 163 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
164 | } |
165 | ||
917940ce | 166 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
167 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
168 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
169 | } |
170 | ||
f25c0ae1 | 171 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 172 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 173 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 174 | "ram-size"); |
f25c0ae1 | 175 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 176 | "max-ram-size"); |
f25c0ae1 CLG |
177 | |
178 | for (i = 0; i < sc->wdts_num; i++) { | |
179 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 180 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
181 | } |
182 | ||
d300db02 | 183 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
184 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
185 | TYPE_FTGMAC100); | |
289251b0 | 186 | |
db873cc5 | 187 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
188 | } |
189 | ||
db873cc5 | 190 | object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); |
f25c0ae1 CLG |
191 | |
192 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 193 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
194 | |
195 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 196 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 197 | |
db873cc5 MA |
198 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
199 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 200 | |
5325cc34 | 201 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 202 | |
f25c0ae1 CLG |
203 | /* Init sd card slot class here so that they're under the correct parent */ |
204 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
205 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
206 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 207 | } |
a29e3e12 | 208 | |
db873cc5 MA |
209 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
210 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 211 | |
5325cc34 | 212 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 213 | |
7089e0cc MA |
214 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
215 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
216 | |
217 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
218 | |
219 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
220 | object_initialize_child(obj, "hace", &s->hace, typename); | |
f25c0ae1 CLG |
221 | } |
222 | ||
223 | /* | |
224 | * ASPEED ast2600 has 0xf as cluster ID | |
225 | * | |
932a8d1f | 226 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
227 | */ |
228 | static uint64_t aspeed_calc_affinity(int cpu) | |
229 | { | |
230 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
231 | } | |
232 | ||
233 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
234 | { | |
235 | int i; | |
236 | AspeedSoCState *s = ASPEED_SOC(dev); | |
237 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 238 | Error *err = NULL; |
f25c0ae1 CLG |
239 | qemu_irq irq; |
240 | ||
241 | /* IO space */ | |
347df6f8 | 242 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_DEV_IOMEM], |
f25c0ae1 CLG |
243 | ASPEED_SOC_IOMEM_SIZE); |
244 | ||
514bcf6f | 245 | /* Video engine stub */ |
347df6f8 | 246 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_DEV_VIDEO], |
514bcf6f JS |
247 | 0x1000); |
248 | ||
f25c0ae1 | 249 | /* CPU */ |
b7f1a0cb | 250 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 251 | if (sc->num_cpus > 1) { |
5325cc34 MA |
252 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
253 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 254 | } |
5325cc34 MA |
255 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
256 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 257 | |
5325cc34 | 258 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 AJ |
259 | &error_abort); |
260 | ||
668f62ec | 261 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
262 | return; |
263 | } | |
264 | } | |
265 | ||
266 | /* A7MPCORE */ | |
5325cc34 | 267 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 268 | &error_abort); |
5325cc34 | 269 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
957ad79f | 270 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 271 | &error_abort); |
f25c0ae1 | 272 | |
db873cc5 | 273 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
f25c0ae1 CLG |
274 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
275 | ||
b7f1a0cb | 276 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 CLG |
277 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
278 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
279 | ||
280 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
281 | sysbus_connect_irq(sbd, i, irq); | |
282 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 283 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 284 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 285 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 286 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 287 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
288 | } |
289 | ||
290 | /* SRAM */ | |
291 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | |
292 | sc->sram_size, &err); | |
293 | if (err) { | |
294 | error_propagate(errp, err); | |
295 | return; | |
296 | } | |
297 | memory_region_add_subregion(get_system_memory(), | |
347df6f8 | 298 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 CLG |
299 | |
300 | /* SCU */ | |
668f62ec | 301 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
302 | return; |
303 | } | |
347df6f8 | 304 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
305 | |
306 | /* RTC */ | |
668f62ec | 307 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
308 | return; |
309 | } | |
347df6f8 | 310 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 311 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 312 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
313 | |
314 | /* Timer */ | |
5325cc34 MA |
315 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
316 | &error_abort); | |
668f62ec | 317 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
318 | return; |
319 | } | |
320 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
347df6f8 | 321 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 322 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
347df6f8 | 323 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
324 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
325 | } | |
326 | ||
327 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
a6b2f1fc PMD |
328 | serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, |
329 | aspeed_soc_get_irq(s, ASPEED_DEV_UART5), | |
330 | 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | |
f25c0ae1 CLG |
331 | |
332 | /* I2C */ | |
5325cc34 | 333 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 334 | &error_abort); |
668f62ec | 335 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
336 | return; |
337 | } | |
347df6f8 | 338 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 CLG |
339 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
340 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
347df6f8 | 341 | sc->irqmap[ASPEED_DEV_I2C] + i); |
f25c0ae1 CLG |
342 | /* |
343 | * The AST2600 SoC has one IRQ per I2C bus. Skip the common | |
344 | * IRQ (AST2400 and AST2500) and connect all bussses. | |
345 | */ | |
346 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); | |
347 | } | |
348 | ||
349 | /* FMC, The number of CS is set at the board level */ | |
5325cc34 | 350 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 351 | &error_abort); |
668f62ec | 352 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
353 | return; |
354 | } | |
347df6f8 | 355 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
f25c0ae1 CLG |
356 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, |
357 | s->fmc.ctrl->flash_window_base); | |
358 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | |
347df6f8 | 359 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 CLG |
360 | |
361 | /* SPI */ | |
362 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
363 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
364 | OBJECT(s->dram_mr), &error_abort); | |
365 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); | |
668f62ec | 366 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
367 | return; |
368 | } | |
369 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
347df6f8 | 370 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
f25c0ae1 CLG |
371 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, |
372 | s->spi[i].ctrl->flash_window_base); | |
373 | } | |
374 | ||
917940ce GR |
375 | /* EHCI */ |
376 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 377 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
378 | return; |
379 | } | |
380 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
347df6f8 | 381 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 382 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 383 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
384 | } |
385 | ||
f25c0ae1 | 386 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 387 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
388 | return; |
389 | } | |
347df6f8 | 390 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_DEV_SDMC]); |
f25c0ae1 CLG |
391 | |
392 | /* Watch dog */ | |
393 | for (i = 0; i < sc->wdts_num; i++) { | |
394 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
395 | ||
5325cc34 MA |
396 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
397 | &error_abort); | |
668f62ec | 398 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
399 | return; |
400 | } | |
401 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
347df6f8 | 402 | sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); |
f25c0ae1 CLG |
403 | } |
404 | ||
405 | /* Net */ | |
d3bad7e7 | 406 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 407 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 408 | &error_abort); |
668f62ec | 409 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 410 | return; |
f25c0ae1 CLG |
411 | } |
412 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
347df6f8 | 413 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 414 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 415 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 416 | |
5325cc34 MA |
417 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
418 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 419 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
420 | return; |
421 | } | |
422 | ||
423 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | |
347df6f8 | 424 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
425 | } |
426 | ||
427 | /* XDMA */ | |
668f62ec | 428 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
429 | return; |
430 | } | |
431 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
347df6f8 | 432 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 433 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 434 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
435 | |
436 | /* GPIO */ | |
668f62ec | 437 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
438 | return; |
439 | } | |
347df6f8 | 440 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 441 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 442 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 443 | |
668f62ec | 444 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
445 | return; |
446 | } | |
447 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
347df6f8 | 448 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 449 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 450 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
451 | |
452 | /* SDHCI */ | |
668f62ec | 453 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
454 | return; |
455 | } | |
456 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
347df6f8 | 457 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 458 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 459 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
460 | |
461 | /* eMMC */ | |
668f62ec | 462 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
463 | return; |
464 | } | |
347df6f8 | 465 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]); |
a29e3e12 | 466 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 467 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
468 | |
469 | /* LPC */ | |
470 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
471 | return; | |
472 | } | |
473 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); | |
c59f781e AJ |
474 | |
475 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
476 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
477 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
478 | |
479 | /* | |
480 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
481 | * | |
482 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
483 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
484 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
485 | * offset 0. | |
486 | */ | |
487 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
488 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
489 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); | |
490 | ||
491 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
492 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
493 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); | |
494 | ||
495 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
496 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
497 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); | |
498 | ||
499 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
500 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
501 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); | |
a3888d75 JS |
502 | |
503 | /* HACE */ | |
504 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
505 | &error_abort); | |
506 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
507 | return; | |
508 | } | |
509 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); | |
510 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, | |
511 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
f25c0ae1 CLG |
512 | } |
513 | ||
514 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
515 | { | |
516 | DeviceClass *dc = DEVICE_CLASS(oc); | |
517 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
518 | ||
519 | dc->realize = aspeed_soc_ast2600_realize; | |
520 | ||
7582591a | 521 | sc->name = "ast2600-a1"; |
f25c0ae1 | 522 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
7582591a | 523 | sc->silicon_rev = AST2600_A1_SILICON_REV; |
e01b4d5b | 524 | sc->sram_size = 0x16400; |
f25c0ae1 | 525 | sc->spis_num = 2; |
917940ce | 526 | sc->ehcis_num = 2; |
f25c0ae1 | 527 | sc->wdts_num = 4; |
d300db02 | 528 | sc->macs_num = 4; |
f25c0ae1 CLG |
529 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
530 | sc->memmap = aspeed_soc_ast2600_memmap; | |
531 | sc->num_cpus = 2; | |
532 | } | |
533 | ||
534 | static const TypeInfo aspeed_soc_ast2600_type_info = { | |
7582591a | 535 | .name = "ast2600-a1", |
f25c0ae1 CLG |
536 | .parent = TYPE_ASPEED_SOC, |
537 | .instance_size = sizeof(AspeedSoCState), | |
538 | .instance_init = aspeed_soc_ast2600_init, | |
539 | .class_init = aspeed_soc_ast2600_class_init, | |
540 | .class_size = sizeof(AspeedSoCClass), | |
541 | }; | |
542 | ||
543 | static void aspeed_soc_register_types(void) | |
544 | { | |
545 | type_register_static(&aspeed_soc_ast2600_type_info); | |
546 | }; | |
547 | ||
548 | type_init(aspeed_soc_register_types) |