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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
12 | #include "cpu.h" | |
13 | #include "exec/address-spaces.h" | |
14 | #include "hw/misc/unimp.h" | |
15 | #include "hw/arm/aspeed_soc.h" | |
16 | #include "hw/char/serial.h" | |
17 | #include "qemu/log.h" | |
18 | #include "qemu/module.h" | |
19 | #include "qemu/error-report.h" | |
20 | #include "hw/i2c/aspeed_i2c.h" | |
21 | #include "net/net.h" | |
22 | #include "sysemu/sysemu.h" | |
23 | ||
24 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
25 | ||
26 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
27 | [ASPEED_SRAM] = 0x10000000, | |
28 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ | |
29 | [ASPEED_IOMEM] = 0x1E600000, | |
30 | [ASPEED_PWM] = 0x1E610000, | |
31 | [ASPEED_FMC] = 0x1E620000, | |
32 | [ASPEED_SPI1] = 0x1E630000, | |
33 | [ASPEED_SPI2] = 0x1E641000, | |
917940ce GR |
34 | [ASPEED_EHCI1] = 0x1E6A1000, |
35 | [ASPEED_EHCI2] = 0x1E6A3000, | |
289251b0 CLG |
36 | [ASPEED_MII1] = 0x1E650000, |
37 | [ASPEED_MII2] = 0x1E650008, | |
38 | [ASPEED_MII3] = 0x1E650010, | |
39 | [ASPEED_MII4] = 0x1E650018, | |
f25c0ae1 | 40 | [ASPEED_ETH1] = 0x1E660000, |
d300db02 | 41 | [ASPEED_ETH3] = 0x1E670000, |
f25c0ae1 | 42 | [ASPEED_ETH2] = 0x1E680000, |
d300db02 | 43 | [ASPEED_ETH4] = 0x1E690000, |
f25c0ae1 CLG |
44 | [ASPEED_VIC] = 0x1E6C0000, |
45 | [ASPEED_SDMC] = 0x1E6E0000, | |
46 | [ASPEED_SCU] = 0x1E6E2000, | |
47 | [ASPEED_XDMA] = 0x1E6E7000, | |
48 | [ASPEED_ADC] = 0x1E6E9000, | |
514bcf6f | 49 | [ASPEED_VIDEO] = 0x1E700000, |
f25c0ae1 | 50 | [ASPEED_SDHCI] = 0x1E740000, |
a29e3e12 | 51 | [ASPEED_EMMC] = 0x1E750000, |
f25c0ae1 CLG |
52 | [ASPEED_GPIO] = 0x1E780000, |
53 | [ASPEED_GPIO_1_8V] = 0x1E780800, | |
54 | [ASPEED_RTC] = 0x1E781000, | |
55 | [ASPEED_TIMER1] = 0x1E782000, | |
56 | [ASPEED_WDT] = 0x1E785000, | |
57 | [ASPEED_LPC] = 0x1E789000, | |
58 | [ASPEED_IBT] = 0x1E789140, | |
59 | [ASPEED_I2C] = 0x1E78A000, | |
60 | [ASPEED_UART1] = 0x1E783000, | |
61 | [ASPEED_UART5] = 0x1E784000, | |
62 | [ASPEED_VUART] = 0x1E787000, | |
63 | [ASPEED_SDRAM] = 0x80000000, | |
64 | }; | |
65 | ||
66 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
67 | ||
68 | #define ASPEED_SOC_AST2600_MAX_IRQ 128 | |
69 | ||
a29e3e12 | 70 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 CLG |
71 | static const int aspeed_soc_ast2600_irqmap[] = { |
72 | [ASPEED_UART1] = 47, | |
73 | [ASPEED_UART2] = 48, | |
74 | [ASPEED_UART3] = 49, | |
75 | [ASPEED_UART4] = 50, | |
76 | [ASPEED_UART5] = 8, | |
77 | [ASPEED_VUART] = 8, | |
78 | [ASPEED_FMC] = 39, | |
79 | [ASPEED_SDMC] = 0, | |
80 | [ASPEED_SCU] = 12, | |
81 | [ASPEED_ADC] = 78, | |
82 | [ASPEED_XDMA] = 6, | |
83 | [ASPEED_SDHCI] = 43, | |
917940ce GR |
84 | [ASPEED_EHCI1] = 5, |
85 | [ASPEED_EHCI2] = 9, | |
a29e3e12 | 86 | [ASPEED_EMMC] = 15, |
f25c0ae1 CLG |
87 | [ASPEED_GPIO] = 40, |
88 | [ASPEED_GPIO_1_8V] = 11, | |
89 | [ASPEED_RTC] = 13, | |
90 | [ASPEED_TIMER1] = 16, | |
91 | [ASPEED_TIMER2] = 17, | |
92 | [ASPEED_TIMER3] = 18, | |
93 | [ASPEED_TIMER4] = 19, | |
94 | [ASPEED_TIMER5] = 20, | |
95 | [ASPEED_TIMER6] = 21, | |
96 | [ASPEED_TIMER7] = 22, | |
97 | [ASPEED_TIMER8] = 23, | |
98 | [ASPEED_WDT] = 24, | |
99 | [ASPEED_PWM] = 44, | |
100 | [ASPEED_LPC] = 35, | |
101 | [ASPEED_IBT] = 35, /* LPC */ | |
102 | [ASPEED_I2C] = 110, /* 110 -> 125 */ | |
103 | [ASPEED_ETH1] = 2, | |
104 | [ASPEED_ETH2] = 3, | |
d300db02 JS |
105 | [ASPEED_ETH3] = 32, |
106 | [ASPEED_ETH4] = 33, | |
107 | ||
f25c0ae1 CLG |
108 | }; |
109 | ||
110 | static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) | |
111 | { | |
112 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
113 | ||
114 | return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); | |
115 | } | |
116 | ||
117 | static void aspeed_soc_ast2600_init(Object *obj) | |
118 | { | |
119 | AspeedSoCState *s = ASPEED_SOC(obj); | |
120 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
121 | int i; | |
122 | char socname[8]; | |
123 | char typename[64]; | |
124 | ||
125 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
126 | g_assert_not_reached(); | |
127 | } | |
128 | ||
129 | for (i = 0; i < sc->num_cpus; i++) { | |
9fc7fc4d | 130 | object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type); |
f25c0ae1 CLG |
131 | } |
132 | ||
133 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 134 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
135 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
136 | sc->silicon_rev); | |
137 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 138 | "hw-strap1"); |
f25c0ae1 | 139 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 140 | "hw-strap2"); |
f25c0ae1 | 141 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 142 | "hw-prot-key"); |
f25c0ae1 | 143 | |
db873cc5 MA |
144 | object_initialize_child(obj, "a7mpcore", &s->a7mpcore, |
145 | TYPE_A15MPCORE_PRIV); | |
f25c0ae1 | 146 | |
db873cc5 | 147 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
148 | |
149 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 150 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 CLG |
151 | |
152 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); | |
db873cc5 | 153 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 CLG |
154 | |
155 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); | |
db873cc5 | 156 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
d2623129 | 157 | object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs"); |
f25c0ae1 CLG |
158 | |
159 | for (i = 0; i < sc->spis_num; i++) { | |
160 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 161 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
162 | } |
163 | ||
917940ce | 164 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
165 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
166 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
167 | } |
168 | ||
f25c0ae1 | 169 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 170 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 171 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 172 | "ram-size"); |
f25c0ae1 | 173 | object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), |
d2623129 | 174 | "max-ram-size"); |
f25c0ae1 CLG |
175 | |
176 | for (i = 0; i < sc->wdts_num; i++) { | |
177 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 178 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
179 | } |
180 | ||
d300db02 | 181 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
182 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
183 | TYPE_FTGMAC100); | |
289251b0 | 184 | |
db873cc5 | 185 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
186 | } |
187 | ||
db873cc5 | 188 | object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); |
f25c0ae1 CLG |
189 | |
190 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 191 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
192 | |
193 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 194 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 195 | |
db873cc5 MA |
196 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
197 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 198 | |
5325cc34 | 199 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 200 | |
f25c0ae1 CLG |
201 | /* Init sd card slot class here so that they're under the correct parent */ |
202 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
203 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
204 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 205 | } |
a29e3e12 | 206 | |
db873cc5 MA |
207 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
208 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 209 | |
5325cc34 | 210 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 211 | |
7089e0cc MA |
212 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
213 | TYPE_SYSBUS_SDHCI); | |
f25c0ae1 CLG |
214 | } |
215 | ||
216 | /* | |
217 | * ASPEED ast2600 has 0xf as cluster ID | |
218 | * | |
219 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html | |
220 | */ | |
221 | static uint64_t aspeed_calc_affinity(int cpu) | |
222 | { | |
223 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
224 | } | |
225 | ||
226 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
227 | { | |
228 | int i; | |
229 | AspeedSoCState *s = ASPEED_SOC(dev); | |
230 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
123327d1 | 231 | Error *err = NULL; |
f25c0ae1 CLG |
232 | qemu_irq irq; |
233 | ||
234 | /* IO space */ | |
235 | create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM], | |
236 | ASPEED_SOC_IOMEM_SIZE); | |
237 | ||
514bcf6f JS |
238 | /* Video engine stub */ |
239 | create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO], | |
240 | 0x1000); | |
241 | ||
f25c0ae1 | 242 | /* CPU */ |
b7f1a0cb | 243 | for (i = 0; i < sc->num_cpus; i++) { |
5325cc34 MA |
244 | object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit", |
245 | QEMU_PSCI_CONDUIT_SMC, &error_abort); | |
b7f1a0cb | 246 | if (sc->num_cpus > 1) { |
5325cc34 MA |
247 | object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", |
248 | ASPEED_A7MPCORE_ADDR, &error_abort); | |
f25c0ae1 | 249 | } |
5325cc34 MA |
250 | object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", |
251 | aspeed_calc_affinity(i), &error_abort); | |
f25c0ae1 | 252 | |
5325cc34 | 253 | object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, |
058d0955 AJ |
254 | &error_abort); |
255 | ||
f25c0ae1 CLG |
256 | /* |
257 | * TODO: the secondary CPUs are started and a boot helper | |
258 | * is needed when using -kernel | |
259 | */ | |
260 | ||
118bfd76 | 261 | if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, &err)) { |
f25c0ae1 CLG |
262 | error_propagate(errp, err); |
263 | return; | |
264 | } | |
265 | } | |
266 | ||
267 | /* A7MPCORE */ | |
5325cc34 | 268 | object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 269 | &error_abort); |
5325cc34 | 270 | object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", |
f25c0ae1 | 271 | ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL, |
5325cc34 | 272 | &error_abort); |
f25c0ae1 | 273 | |
db873cc5 | 274 | sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); |
f25c0ae1 CLG |
275 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); |
276 | ||
b7f1a0cb | 277 | for (i = 0; i < sc->num_cpus; i++) { |
f25c0ae1 CLG |
278 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); |
279 | DeviceState *d = DEVICE(qemu_get_cpu(i)); | |
280 | ||
281 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
282 | sysbus_connect_irq(sbd, i, irq); | |
283 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 284 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 285 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 286 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 287 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 288 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
289 | } |
290 | ||
291 | /* SRAM */ | |
292 | memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram", | |
293 | sc->sram_size, &err); | |
294 | if (err) { | |
295 | error_propagate(errp, err); | |
296 | return; | |
297 | } | |
298 | memory_region_add_subregion(get_system_memory(), | |
299 | sc->memmap[ASPEED_SRAM], &s->sram); | |
300 | ||
301 | /* SCU */ | |
118bfd76 | 302 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err)) { |
f25c0ae1 CLG |
303 | error_propagate(errp, err); |
304 | return; | |
305 | } | |
306 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]); | |
307 | ||
308 | /* RTC */ | |
118bfd76 | 309 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err)) { |
f25c0ae1 CLG |
310 | error_propagate(errp, err); |
311 | return; | |
312 | } | |
313 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]); | |
314 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, | |
315 | aspeed_soc_get_irq(s, ASPEED_RTC)); | |
316 | ||
317 | /* Timer */ | |
5325cc34 MA |
318 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
319 | &error_abort); | |
118bfd76 | 320 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err)) { |
f25c0ae1 CLG |
321 | error_propagate(errp, err); |
322 | return; | |
323 | } | |
324 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, | |
325 | sc->memmap[ASPEED_TIMER1]); | |
326 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { | |
327 | qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i); | |
328 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); | |
329 | } | |
330 | ||
331 | /* UART - attach an 8250 to the IO space as our UART5 */ | |
332 | if (serial_hd(0)) { | |
333 | qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5); | |
334 | serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2, | |
335 | uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); | |
336 | } | |
337 | ||
338 | /* I2C */ | |
5325cc34 | 339 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 340 | &error_abort); |
118bfd76 | 341 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err)) { |
f25c0ae1 CLG |
342 | error_propagate(errp, err); |
343 | return; | |
344 | } | |
345 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]); | |
346 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { | |
347 | qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), | |
348 | sc->irqmap[ASPEED_I2C] + i); | |
349 | /* | |
350 | * The AST2600 SoC has one IRQ per I2C bus. Skip the common | |
351 | * IRQ (AST2400 and AST2500) and connect all bussses. | |
352 | */ | |
353 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), i + 1, irq); | |
354 | } | |
355 | ||
356 | /* FMC, The number of CS is set at the board level */ | |
5325cc34 | 357 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 358 | &error_abort); |
5325cc34 MA |
359 | object_property_set_int(OBJECT(&s->fmc), "sdram-base", |
360 | sc->memmap[ASPEED_SDRAM], &err); | |
f25c0ae1 CLG |
361 | if (err) { |
362 | error_propagate(errp, err); | |
363 | return; | |
364 | } | |
118bfd76 | 365 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err)) { |
f25c0ae1 CLG |
366 | error_propagate(errp, err); |
367 | return; | |
368 | } | |
369 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]); | |
370 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1, | |
371 | s->fmc.ctrl->flash_window_base); | |
372 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, | |
373 | aspeed_soc_get_irq(s, ASPEED_FMC)); | |
374 | ||
375 | /* SPI */ | |
376 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
377 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
378 | OBJECT(s->dram_mr), &error_abort); | |
379 | object_property_set_int(OBJECT(&s->spi[i]), "num-cs", 1, &error_abort); | |
118bfd76 | 380 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &err)) { |
f25c0ae1 CLG |
381 | error_propagate(errp, err); |
382 | return; | |
383 | } | |
384 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | |
385 | sc->memmap[ASPEED_SPI1 + i]); | |
386 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1, | |
387 | s->spi[i].ctrl->flash_window_base); | |
388 | } | |
389 | ||
917940ce GR |
390 | /* EHCI */ |
391 | for (i = 0; i < sc->ehcis_num; i++) { | |
118bfd76 | 392 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err)) { |
917940ce GR |
393 | error_propagate(errp, err); |
394 | return; | |
395 | } | |
396 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
397 | sc->memmap[ASPEED_EHCI1 + i]); | |
398 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, | |
399 | aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); | |
400 | } | |
401 | ||
f25c0ae1 | 402 | /* SDMC - SDRAM Memory Controller */ |
118bfd76 | 403 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err)) { |
f25c0ae1 CLG |
404 | error_propagate(errp, err); |
405 | return; | |
406 | } | |
407 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]); | |
408 | ||
409 | /* Watch dog */ | |
410 | for (i = 0; i < sc->wdts_num; i++) { | |
411 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
412 | ||
5325cc34 MA |
413 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
414 | &error_abort); | |
118bfd76 | 415 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err)) { |
f25c0ae1 CLG |
416 | error_propagate(errp, err); |
417 | return; | |
418 | } | |
419 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | |
420 | sc->memmap[ASPEED_WDT] + i * awc->offset); | |
421 | } | |
422 | ||
423 | /* Net */ | |
d3bad7e7 | 424 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 425 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 426 | &error_abort); |
118bfd76 | 427 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &err)) { |
f25c0ae1 | 428 | error_propagate(errp, err); |
123327d1 | 429 | return; |
f25c0ae1 CLG |
430 | } |
431 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
432 | sc->memmap[ASPEED_ETH1 + i]); | |
433 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, | |
434 | aspeed_soc_get_irq(s, ASPEED_ETH1 + i)); | |
289251b0 | 435 | |
5325cc34 MA |
436 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
437 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
118bfd76 | 438 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), &err)) { |
289251b0 CLG |
439 | error_propagate(errp, err); |
440 | return; | |
441 | } | |
442 | ||
443 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0, | |
444 | sc->memmap[ASPEED_MII1 + i]); | |
f25c0ae1 CLG |
445 | } |
446 | ||
447 | /* XDMA */ | |
118bfd76 | 448 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err)) { |
f25c0ae1 CLG |
449 | error_propagate(errp, err); |
450 | return; | |
451 | } | |
452 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0, | |
453 | sc->memmap[ASPEED_XDMA]); | |
454 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, | |
455 | aspeed_soc_get_irq(s, ASPEED_XDMA)); | |
456 | ||
457 | /* GPIO */ | |
118bfd76 | 458 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err)) { |
f25c0ae1 CLG |
459 | error_propagate(errp, err); |
460 | return; | |
461 | } | |
462 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]); | |
463 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, | |
464 | aspeed_soc_get_irq(s, ASPEED_GPIO)); | |
465 | ||
118bfd76 | 466 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), &err)) { |
f25c0ae1 CLG |
467 | error_propagate(errp, err); |
468 | return; | |
469 | } | |
470 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
471 | sc->memmap[ASPEED_GPIO_1_8V]); | |
472 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, | |
473 | aspeed_soc_get_irq(s, ASPEED_GPIO_1_8V)); | |
474 | ||
475 | /* SDHCI */ | |
118bfd76 | 476 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err)) { |
f25c0ae1 CLG |
477 | error_propagate(errp, err); |
478 | return; | |
479 | } | |
480 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | |
481 | sc->memmap[ASPEED_SDHCI]); | |
482 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, | |
483 | aspeed_soc_get_irq(s, ASPEED_SDHCI)); | |
a29e3e12 AJ |
484 | |
485 | /* eMMC */ | |
118bfd76 | 486 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), &err)) { |
a29e3e12 AJ |
487 | error_propagate(errp, err); |
488 | return; | |
489 | } | |
490 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_EMMC]); | |
491 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, | |
492 | aspeed_soc_get_irq(s, ASPEED_EMMC)); | |
f25c0ae1 CLG |
493 | } |
494 | ||
495 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
496 | { | |
497 | DeviceClass *dc = DEVICE_CLASS(oc); | |
498 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
499 | ||
500 | dc->realize = aspeed_soc_ast2600_realize; | |
501 | ||
7582591a | 502 | sc->name = "ast2600-a1"; |
f25c0ae1 | 503 | sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); |
7582591a | 504 | sc->silicon_rev = AST2600_A1_SILICON_REV; |
f25c0ae1 CLG |
505 | sc->sram_size = 0x10000; |
506 | sc->spis_num = 2; | |
917940ce | 507 | sc->ehcis_num = 2; |
f25c0ae1 | 508 | sc->wdts_num = 4; |
d300db02 | 509 | sc->macs_num = 4; |
f25c0ae1 CLG |
510 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
511 | sc->memmap = aspeed_soc_ast2600_memmap; | |
512 | sc->num_cpus = 2; | |
513 | } | |
514 | ||
515 | static const TypeInfo aspeed_soc_ast2600_type_info = { | |
7582591a | 516 | .name = "ast2600-a1", |
f25c0ae1 CLG |
517 | .parent = TYPE_ASPEED_SOC, |
518 | .instance_size = sizeof(AspeedSoCState), | |
519 | .instance_init = aspeed_soc_ast2600_init, | |
520 | .class_init = aspeed_soc_ast2600_class_init, | |
521 | .class_size = sizeof(AspeedSoCClass), | |
522 | }; | |
523 | ||
524 | static void aspeed_soc_register_types(void) | |
525 | { | |
526 | type_register_static(&aspeed_soc_ast2600_type_info); | |
527 | }; | |
528 | ||
529 | type_init(aspeed_soc_register_types) |