]> git.proxmox.com Git - mirror_qemu.git/blame - hw/i386/intel_iommu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pci: mark ROMs read-only
[mirror_qemu.git] / hw / i386 / intel_iommu.c
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
4684a204 23#include "qemu/error-report.h"
6333e93c 24#include "qapi/error.h"
1da12ec4
LT		 25#include "hw/sysbus.h"
26#include "exec/address-spaces.h"
27#include "intel_iommu_internal.h"
7df953bd 28#include "hw/pci/pci.h"
3cb3b154 29#include "hw/pci/pci_bus.h"
621d983a 30#include "hw/i386/pc.h"
dea651a9 31#include "hw/i386/apic-msidef.h"
04af0e18
PX		 32#include "hw/boards.h"
33#include "hw/i386/x86-iommu.h"
cb135f59 34#include "hw/pci-host/q35.h"
4684a204 35#include "sysemu/kvm.h"
32946019 36#include "hw/i386/apic_internal.h"
fb506e70 37#include "kvm_i386.h"
1da12ec4
LT		 38
39/*#define DEBUG_INTEL_IOMMU*/
40#ifdef DEBUG_INTEL_IOMMU
41enum {
42 DEBUG_GENERAL, DEBUG_CSR, DEBUG_INV, DEBUG_MMU, DEBUG_FLOG,
a5861439 43 DEBUG_CACHE, DEBUG_IR,
1da12ec4
LT		 44};
45#define VTD_DBGBIT(x) (1 << DEBUG_##x)
46static int vtd_dbgflags = VTD_DBGBIT(GENERAL) | VTD_DBGBIT(CSR);
47
48#define VTD_DPRINTF(what, fmt, ...) do { \
49 if (vtd_dbgflags & VTD_DBGBIT(what)) { \
50 fprintf(stderr, "(vtd)%s: " fmt "\n", __func__, \
51 ## __VA_ARGS__); } \
52 } while (0)
53#else
54#define VTD_DPRINTF(what, fmt, ...) do {} while (0)
55#endif
56
57static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
58 uint64_t wmask, uint64_t w1cmask)
59{
60 stq_le_p(&s->csr[addr], val);
61 stq_le_p(&s->wmask[addr], wmask);
62 stq_le_p(&s->w1cmask[addr], w1cmask);
63}
64
65static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
66{
67 stq_le_p(&s->womask[addr], mask);
68}
69
70static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
71 uint32_t wmask, uint32_t w1cmask)
72{
73 stl_le_p(&s->csr[addr], val);
74 stl_le_p(&s->wmask[addr], wmask);
75 stl_le_p(&s->w1cmask[addr], w1cmask);
76}
77
78static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
79{
80 stl_le_p(&s->womask[addr], mask);
81}
82
83/* "External" get/set operations */
84static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
85{
86 uint64_t oldval = ldq_le_p(&s->csr[addr]);
87 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
88 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
89 stq_le_p(&s->csr[addr],
90 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
91}
92
93static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
94{
95 uint32_t oldval = ldl_le_p(&s->csr[addr]);
96 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
97 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
98 stl_le_p(&s->csr[addr],
99 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
100}
101
102static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
103{
104 uint64_t val = ldq_le_p(&s->csr[addr]);
105 uint64_t womask = ldq_le_p(&s->womask[addr]);
106 return val & ~womask;
107}
108
109static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
110{
111 uint32_t val = ldl_le_p(&s->csr[addr]);
112 uint32_t womask = ldl_le_p(&s->womask[addr]);
113 return val & ~womask;
114}
115
116/* "Internal" get/set operations */
117static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
118{
119 return ldq_le_p(&s->csr[addr]);
120}
121
122static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
123{
124 return ldl_le_p(&s->csr[addr]);
125}
126
127static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
128{
129 stq_le_p(&s->csr[addr], val);
130}
131
132static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
133 uint32_t clear, uint32_t mask)
134{
135 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
136 stl_le_p(&s->csr[addr], new_val);
137 return new_val;
138}
139
140static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
141 uint64_t clear, uint64_t mask)
142{
143 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
144 stq_le_p(&s->csr[addr], new_val);
145 return new_val;
146}
147
b5a280c0
LT		 148/* GHashTable functions */
149static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
150{
151 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
152}
153
154static guint vtd_uint64_hash(gconstpointer v)
155{
156 return (guint)*(const uint64_t *)v;
157}
158
159static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
160 gpointer user_data)
161{
162 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
163 uint16_t domain_id = *(uint16_t *)user_data;
164 return entry->domain_id == domain_id;
165}
166
d66b969b
JW		 167/* The shift of an addr for a certain level of paging structure */
168static inline uint32_t vtd_slpt_level_shift(uint32_t level)
169{
170 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
171}
172
173static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
174{
175 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
176}
177
b5a280c0
LT		 178static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
179 gpointer user_data)
180{
181 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
182 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 183 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
184 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 185 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 186 (((entry->gfn & info->mask) == gfn) ||
187 (entry->gfn == gfn_tlb));
b5a280c0
LT		 188}
189
d92fa2dc
LT		 190/* Reset all the gen of VTDAddressSpace to zero and set the gen of
191 * IntelIOMMUState to 1.
192 */
193static void vtd_reset_context_cache(IntelIOMMUState *s)
194{
d92fa2dc 195 VTDAddressSpace *vtd_as;
7df953bd
KO		 196 VTDBus *vtd_bus;
197 GHashTableIter bus_it;
d92fa2dc
LT		 198 uint32_t devfn_it;
199
7df953bd
KO		 200 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
201
d92fa2dc 202 VTD_DPRINTF(CACHE, "global context_cache_gen=1");
7df953bd 203 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
04af0e18 204 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 205 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 206 if (!vtd_as) {
207 continue;
208 }
209 vtd_as->context_cache_entry.context_cache_gen = 0;
210 }
211 }
212 s->context_cache_gen = 1;
213}
214
b5a280c0
LT		 215static void vtd_reset_iotlb(IntelIOMMUState *s)
216{
217 assert(s->iotlb);
218 g_hash_table_remove_all(s->iotlb);
219}
220
bacabb0a 221static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
d66b969b
JW		 222 uint32_t level)
223{
224 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
225 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
226}
227
228static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
229{
230 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
231}
232
b5a280c0
LT		 233static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
234 hwaddr addr)
235{
d66b969b 236 VTDIOTLBEntry *entry;
b5a280c0 237 uint64_t key;
d66b969b
JW		 238 int level;
239
240 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
241 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
242 source_id, level);
243 entry = g_hash_table_lookup(s->iotlb, &key);
244 if (entry) {
245 goto out;
246 }
247 }
b5a280c0 248
d66b969b
JW		 249out:
250 return entry;
b5a280c0
LT		 251}
252
253static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
254 uint16_t domain_id, hwaddr addr, uint64_t slpte,
d66b969b
JW		 255 bool read_flags, bool write_flags,
256 uint32_t level)
b5a280c0
LT		 257{
258 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
259 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 260 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0
LT		 261
262 VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
263 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, slpte,
264 domain_id);
265 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
266 VTD_DPRINTF(CACHE, "iotlb exceeds size limit, forced to reset");
267 vtd_reset_iotlb(s);
268 }
269
270 entry->gfn = gfn;
271 entry->domain_id = domain_id;
272 entry->slpte = slpte;
273 entry->read_flags = read_flags;
274 entry->write_flags = write_flags;
d66b969b
JW		 275 entry->mask = vtd_slpt_level_page_mask(level);
276 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 277 g_hash_table_replace(s->iotlb, key, entry);
278}
279
1da12ec4
LT		 280/* Given the reg addr of both the message data and address, generate an
281 * interrupt via MSI.
282 */
283static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
284 hwaddr mesg_data_reg)
285{
32946019 286 MSIMessage msi;
1da12ec4
LT		 287
288 assert(mesg_data_reg < DMAR_REG_SIZE);
289 assert(mesg_addr_reg < DMAR_REG_SIZE);
290
32946019
RK		 291 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
292 msi.data = vtd_get_long_raw(s, mesg_data_reg);
1da12ec4 293
32946019
RK		 294 VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32,
295 msi.address, msi.data);
296 apic_get_class()->send_msi(&msi);
1da12ec4
LT		 297}
298
299/* Generate a fault event to software via MSI if conditions are met.
300 * Notice that the value of FSTS_REG being passed to it should be the one
301 * before any update.
302 */
303static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
304{
305 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
306 pre_fsts & VTD_FSTS_IQE) {
307 VTD_DPRINTF(FLOG, "there are previous interrupt conditions "
308 "to be serviced by software, fault event is not generated "
309 "(FSTS_REG 0x%"PRIx32 ")", pre_fsts);
310 return;
311 }
312 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
313 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
314 VTD_DPRINTF(FLOG, "Interrupt Mask set, fault event is not generated");
315 } else {
316 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
317 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
318 }
319}
320
321/* Check if the Fault (F) field of the Fault Recording Register referenced by
322 * @index is Set.
323 */
324static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
325{
326 /* Each reg is 128-bit */
327 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
328 addr += 8; /* Access the high 64-bit half */
329
330 assert(index < DMAR_FRCD_REG_NR);
331
332 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
333}
334
335/* Update the PPF field of Fault Status Register.
336 * Should be called whenever change the F field of any fault recording
337 * registers.
338 */
339static void vtd_update_fsts_ppf(IntelIOMMUState *s)
340{
341 uint32_t i;
342 uint32_t ppf_mask = 0;
343
344 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
345 if (vtd_is_frcd_set(s, i)) {
346 ppf_mask = VTD_FSTS_PPF;
347 break;
348 }
349 }
350 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
351 VTD_DPRINTF(FLOG, "set PPF of FSTS_REG to %d", ppf_mask ? 1 : 0);
352}
353
354static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
355{
356 /* Each reg is 128-bit */
357 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
358 addr += 8; /* Access the high 64-bit half */
359
360 assert(index < DMAR_FRCD_REG_NR);
361
362 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
363 vtd_update_fsts_ppf(s);
364}
365
366/* Must not update F field now, should be done later */
367static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
368 uint16_t source_id, hwaddr addr,
369 VTDFaultReason fault, bool is_write)
370{
371 uint64_t hi = 0, lo;
372 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
373
374 assert(index < DMAR_FRCD_REG_NR);
375
376 lo = VTD_FRCD_FI(addr);
377 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
378 if (!is_write) {
379 hi |= VTD_FRCD_T;
380 }
381 vtd_set_quad_raw(s, frcd_reg_addr, lo);
382 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
383 VTD_DPRINTF(FLOG, "record to FRCD_REG #%"PRIu16 ": hi 0x%"PRIx64
384 ", lo 0x%"PRIx64, index, hi, lo);
385}
386
387/* Try to collapse multiple pending faults from the same requester */
388static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
389{
390 uint32_t i;
391 uint64_t frcd_reg;
392 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
393
394 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
395 frcd_reg = vtd_get_quad_raw(s, addr);
396 VTD_DPRINTF(FLOG, "frcd_reg #%d 0x%"PRIx64, i, frcd_reg);
397 if ((frcd_reg & VTD_FRCD_F) &&
398 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
399 return true;
400 }
401 addr += 16; /* 128-bit for each */
402 }
403 return false;
404}
405
406/* Log and report an DMAR (address translation) fault to software */
407static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
408 hwaddr addr, VTDFaultReason fault,
409 bool is_write)
410{
411 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
412
413 assert(fault < VTD_FR_MAX);
414
415 if (fault == VTD_FR_RESERVED_ERR) {
416 /* This is not a normal fault reason case. Drop it. */
417 return;
418 }
419 VTD_DPRINTF(FLOG, "sid 0x%"PRIx16 ", fault %d, addr 0x%"PRIx64
420 ", is_write %d", source_id, fault, addr, is_write);
421 if (fsts_reg & VTD_FSTS_PFO) {
422 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
423 "Primary Fault Overflow");
424 return;
425 }
426 if (vtd_try_collapse_fault(s, source_id)) {
427 VTD_DPRINTF(FLOG, "new fault is not recorded due to "
428 "compression of faults");
429 return;
430 }
431 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
432 VTD_DPRINTF(FLOG, "Primary Fault Overflow and "
433 "new fault is not recorded, set PFO field");
434 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
435 return;
436 }
437
438 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
439
440 if (fsts_reg & VTD_FSTS_PPF) {
441 VTD_DPRINTF(FLOG, "there are pending faults already, "
442 "fault event is not generated");
443 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
444 s->next_frcd_reg++;
445 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
446 s->next_frcd_reg = 0;
447 }
448 } else {
449 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
450 VTD_FSTS_FRI(s->next_frcd_reg));
451 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
452 s->next_frcd_reg++;
453 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
454 s->next_frcd_reg = 0;
455 }
456 /* This case actually cause the PPF to be Set.
457 * So generate fault event (interrupt).
458 */
459 vtd_generate_fault_event(s, fsts_reg);
460 }
461}
462
ed7b8fbc
LT		 463/* Handle Invalidation Queue Errors of queued invalidation interface error
464 * conditions.
465 */
466static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
467{
468 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
469
470 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
471 vtd_generate_fault_event(s, fsts_reg);
472}
473
474/* Set the IWC field and try to generate an invalidation completion interrupt */
475static void vtd_generate_completion_event(IntelIOMMUState *s)
476{
477 VTD_DPRINTF(INV, "completes an invalidation wait command with "
478 "Interrupt Flag");
479 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
480 VTD_DPRINTF(INV, "there is a previous interrupt condition to be "
481 "serviced by software, "
482 "new invalidation event is not generated");
483 return;
484 }
485 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
486 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
487 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
488 VTD_DPRINTF(INV, "IM filed in IECTL_REG is set, new invalidation "
489 "event is not generated");
490 return;
491 } else {
492 /* Generate the interrupt event */
493 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
494 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
495 }
496}
497
1da12ec4
LT		 498static inline bool vtd_root_entry_present(VTDRootEntry *root)
499{
500 return root->val & VTD_ROOT_ENTRY_P;
501}
502
503static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
504 VTDRootEntry *re)
505{
506 dma_addr_t addr;
507
508 addr = s->root + index * sizeof(*re);
509 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
510 VTD_DPRINTF(GENERAL, "error: fail to access root-entry at 0x%"PRIx64
511 " + %"PRIu8, s->root, index);
512 re->val = 0;
513 return -VTD_FR_ROOT_TABLE_INV;
514 }
515 re->val = le64_to_cpu(re->val);
516 return 0;
517}
518
519static inline bool vtd_context_entry_present(VTDContextEntry *context)
520{
521 return context->lo & VTD_CONTEXT_ENTRY_P;
522}
523
524static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
525 VTDContextEntry *ce)
526{
527 dma_addr_t addr;
528
529 if (!vtd_root_entry_present(root)) {
530 VTD_DPRINTF(GENERAL, "error: root-entry is not present");
531 return -VTD_FR_ROOT_ENTRY_P;
532 }
533 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
534 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
535 VTD_DPRINTF(GENERAL, "error: fail to access context-entry at 0x%"PRIx64
536 " + %"PRIu8,
537 (uint64_t)(root->val & VTD_ROOT_ENTRY_CTP), index);
538 return -VTD_FR_CONTEXT_TABLE_INV;
539 }
540 ce->lo = le64_to_cpu(ce->lo);
541 ce->hi = le64_to_cpu(ce->hi);
542 return 0;
543}
544
545static inline dma_addr_t vtd_get_slpt_base_from_context(VTDContextEntry *ce)
546{
547 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
548}
549
1da12ec4
LT		 550static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
551{
552 return slpte & VTD_SL_PT_BASE_ADDR_MASK;
553}
554
555/* Whether the pte indicates the address of the page frame */
556static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
557{
558 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
559}
560
561/* Get the content of a spte located in @base_addr[@index] */
562static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
563{
564 uint64_t slpte;
565
566 assert(index < VTD_SL_PT_ENTRY_NR);
567
568 if (dma_memory_read(&address_space_memory,
569 base_addr + index * sizeof(slpte), &slpte,
570 sizeof(slpte))) {
571 slpte = (uint64_t)-1;
572 return slpte;
573 }
574 slpte = le64_to_cpu(slpte);
575 return slpte;
576}
577
578/* Given a gpa and the level of paging structure, return the offset of current
579 * level.
580 */
581static inline uint32_t vtd_gpa_level_offset(uint64_t gpa, uint32_t level)
582{
583 return (gpa >> vtd_slpt_level_shift(level)) &
584 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
585}
586
587/* Check Capability Register to see if the @level of page-table is supported */
588static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
589{
590 return VTD_CAP_SAGAW_MASK & s->cap &
591 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
592}
593
594/* Get the page-table level that hardware should use for the second-level
595 * page-table walk from the Address Width field of context-entry.
596 */
597static inline uint32_t vtd_get_level_from_context_entry(VTDContextEntry *ce)
598{
599 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
600}
601
602static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce)
603{
604 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
605}
606
607static const uint64_t vtd_paging_entry_rsvd_field[] = {
608 [0] = ~0ULL,
609 /* For not large page */
610 [1] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
611 [2] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
612 [3] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
613 [4] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
614 /* For large page */
615 [5] = 0x800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
616 [6] = 0x1ff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
617 [7] = 0x3ffff800ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
618 [8] = 0x880ULL | ~(VTD_HAW_MASK | VTD_SL_IGN_COM),
619};
620
621static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
622{
623 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
624 /* Maybe large page */
625 return slpte & vtd_paging_entry_rsvd_field[level + 4];
626 } else {
627 return slpte & vtd_paging_entry_rsvd_field[level];
628 }
629}
630
631/* Given the @gpa, get relevant @slptep. @slpte_level will be the last level
632 * of the translation, can be used for deciding the size of large page.
633 */
634static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_write,
635 uint64_t *slptep, uint32_t *slpte_level,
636 bool *reads, bool *writes)
637{
638 dma_addr_t addr = vtd_get_slpt_base_from_context(ce);
639 uint32_t level = vtd_get_level_from_context_entry(ce);
640 uint32_t offset;
641 uint64_t slpte;
642 uint32_t ce_agaw = vtd_get_agaw_from_context_entry(ce);
643 uint64_t access_right_check;
644
645 /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP_REG
646 * and AW in context-entry.
647 */
648 if (gpa & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) {
649 VTD_DPRINTF(GENERAL, "error: gpa 0x%"PRIx64 " exceeds limits", gpa);
650 return -VTD_FR_ADDR_BEYOND_MGAW;
651 }
652
653 /* FIXME: what is the Atomics request here? */
654 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
655
656 while (true) {
657 offset = vtd_gpa_level_offset(gpa, level);
658 slpte = vtd_get_slpte(addr, offset);
659
660 if (slpte == (uint64_t)-1) {
661 VTD_DPRINTF(GENERAL, "error: fail to access second-level paging "
662 "entry at level %"PRIu32 " for gpa 0x%"PRIx64,
663 level, gpa);
664 if (level == vtd_get_level_from_context_entry(ce)) {
665 /* Invalid programming of context-entry */
666 return -VTD_FR_CONTEXT_ENTRY_INV;
667 } else {
668 return -VTD_FR_PAGING_ENTRY_INV;
669 }
670 }
671 *reads = (*reads) && (slpte & VTD_SL_R);
672 *writes = (*writes) && (slpte & VTD_SL_W);
673 if (!(slpte & access_right_check)) {
674 VTD_DPRINTF(GENERAL, "error: lack of %s permission for "
675 "gpa 0x%"PRIx64 " slpte 0x%"PRIx64,
676 (is_write ? "write" : "read"), gpa, slpte);
677 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
678 }
679 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
680 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in second "
681 "level paging entry level %"PRIu32 " slpte 0x%"PRIx64,
682 level, slpte);
683 return -VTD_FR_PAGING_ENTRY_RSVD;
684 }
685
686 if (vtd_is_last_slpte(slpte, level)) {
687 *slptep = slpte;
688 *slpte_level = level;
689 return 0;
690 }
691 addr = vtd_get_slpte_addr(slpte);
692 level--;
693 }
694}
695
696/* Map a device to its corresponding domain (context-entry) */
697static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
698 uint8_t devfn, VTDContextEntry *ce)
699{
700 VTDRootEntry re;
701 int ret_fr;
702
703 ret_fr = vtd_get_root_entry(s, bus_num, &re);
704 if (ret_fr) {
705 return ret_fr;
706 }
707
708 if (!vtd_root_entry_present(&re)) {
709 VTD_DPRINTF(GENERAL, "error: root-entry #%"PRIu8 " is not present",
710 bus_num);
711 return -VTD_FR_ROOT_ENTRY_P;
712 } else if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD)) {
713 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in root-entry "
714 "hi 0x%"PRIx64 " lo 0x%"PRIx64, re.rsvd, re.val);
715 return -VTD_FR_ROOT_ENTRY_RSVD;
716 }
717
718 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
719 if (ret_fr) {
720 return ret_fr;
721 }
722
723 if (!vtd_context_entry_present(ce)) {
724 VTD_DPRINTF(GENERAL,
725 "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") "
726 "is not present", devfn, bus_num);
727 return -VTD_FR_CONTEXT_ENTRY_P;
728 } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
729 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) {
730 VTD_DPRINTF(GENERAL,
731 "error: non-zero reserved field in context-entry "
732 "hi 0x%"PRIx64 " lo 0x%"PRIx64, ce->hi, ce->lo);
733 return -VTD_FR_CONTEXT_ENTRY_RSVD;
734 }
735 /* Check if the programming of context-entry is valid */
736 if (!vtd_is_level_supported(s, vtd_get_level_from_context_entry(ce))) {
737 VTD_DPRINTF(GENERAL, "error: unsupported Address Width value in "
738 "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
739 ce->hi, ce->lo);
740 return -VTD_FR_CONTEXT_ENTRY_INV;
554f5e16
JW		 741 } else {
742 switch (ce->lo & VTD_CONTEXT_ENTRY_TT) {
743 case VTD_CONTEXT_TT_MULTI_LEVEL:
744 /* fall through */
745 case VTD_CONTEXT_TT_DEV_IOTLB:
746 break;
747 default:
748 VTD_DPRINTF(GENERAL, "error: unsupported Translation Type in "
749 "context-entry hi 0x%"PRIx64 " lo 0x%"PRIx64,
750 ce->hi, ce->lo);
751 return -VTD_FR_CONTEXT_ENTRY_INV;
752 }
1da12ec4
LT		 753 }
754 return 0;
755}
756
757static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
758{
759 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
760}
761
762static const bool vtd_qualified_faults[] = {
763 [VTD_FR_RESERVED] = false,
764 [VTD_FR_ROOT_ENTRY_P] = false,
765 [VTD_FR_CONTEXT_ENTRY_P] = true,
766 [VTD_FR_CONTEXT_ENTRY_INV] = true,
767 [VTD_FR_ADDR_BEYOND_MGAW] = true,
768 [VTD_FR_WRITE] = true,
769 [VTD_FR_READ] = true,
770 [VTD_FR_PAGING_ENTRY_INV] = true,
771 [VTD_FR_ROOT_TABLE_INV] = false,
772 [VTD_FR_CONTEXT_TABLE_INV] = false,
773 [VTD_FR_ROOT_ENTRY_RSVD] = false,
774 [VTD_FR_PAGING_ENTRY_RSVD] = true,
775 [VTD_FR_CONTEXT_ENTRY_TT] = true,
776 [VTD_FR_RESERVED_ERR] = false,
777 [VTD_FR_MAX] = false,
778};
779
780/* To see if a fault condition is "qualified", which is reported to software
781 * only if the FPD field in the context-entry used to process the faulting
782 * request is 0.
783 */
784static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
785{
786 return vtd_qualified_faults[fault];
787}
788
789static inline bool vtd_is_interrupt_addr(hwaddr addr)
790{
791 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
792}
793
794/* Map dev to context-entry then do a paging-structures walk to do a iommu
795 * translation.
79e2b9ae
PB		 796 *
797 * Called from RCU critical section.
798 *
1da12ec4
LT		 799 * @bus_num: The bus number
800 * @devfn: The devfn, which is the combined of device and function number
801 * @is_write: The access is a write operation
802 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
803 */
7df953bd 804static void vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 805 uint8_t devfn, hwaddr addr, bool is_write,
806 IOMMUTLBEntry *entry)
807{
d92fa2dc 808 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 809 VTDContextEntry ce;
7df953bd 810 uint8_t bus_num = pci_bus_num(bus);
d92fa2dc 811 VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
d66b969b 812 uint64_t slpte, page_mask;
1da12ec4
LT		 813 uint32_t level;
814 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
815 int ret_fr;
816 bool is_fpd_set = false;
817 bool reads = true;
818 bool writes = true;
b5a280c0 819 VTDIOTLBEntry *iotlb_entry;
1da12ec4
LT		 820
821 /* Check if the request is in interrupt address range */
822 if (vtd_is_interrupt_addr(addr)) {
823 if (is_write) {
824 /* FIXME: since we don't know the length of the access here, we
825 * treat Non-DWORD length write requests without PASID as
826 * interrupt requests, too. Withoud interrupt remapping support,
827 * we just use 1:1 mapping.
828 */
829 VTD_DPRINTF(MMU, "write request to interrupt address "
830 "gpa 0x%"PRIx64, addr);
831 entry->iova = addr & VTD_PAGE_MASK_4K;
832 entry->translated_addr = addr & VTD_PAGE_MASK_4K;
833 entry->addr_mask = ~VTD_PAGE_MASK_4K;
834 entry->perm = IOMMU_WO;
835 return;
836 } else {
837 VTD_DPRINTF(GENERAL, "error: read request from interrupt address "
838 "gpa 0x%"PRIx64, addr);
839 vtd_report_dmar_fault(s, source_id, addr, VTD_FR_READ, is_write);
840 return;
841 }
842 }
b5a280c0
LT		 843 /* Try to fetch slpte form IOTLB */
844 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
845 if (iotlb_entry) {
846 VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64
847 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr,
848 iotlb_entry->slpte, iotlb_entry->domain_id);
849 slpte = iotlb_entry->slpte;
850 reads = iotlb_entry->read_flags;
851 writes = iotlb_entry->write_flags;
d66b969b 852 page_mask = iotlb_entry->mask;
b5a280c0
LT		 853 goto out;
854 }
d92fa2dc
LT		 855 /* Try to fetch context-entry from cache first */
856 if (cc_entry->context_cache_gen == s->context_cache_gen) {
857 VTD_DPRINTF(CACHE, "hit context-cache bus %d devfn %d "
858 "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 ")",
859 bus_num, devfn, cc_entry->context_entry.hi,
860 cc_entry->context_entry.lo, cc_entry->context_cache_gen);
861 ce = cc_entry->context_entry;
862 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
863 } else {
864 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
865 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
866 if (ret_fr) {
867 ret_fr = -ret_fr;
868 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
869 VTD_DPRINTF(FLOG, "fault processing is disabled for DMA "
870 "requests through this context-entry "
871 "(with FPD Set)");
872 } else {
873 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
874 }
875 return;
1da12ec4 876 }
d92fa2dc
LT		 877 /* Update context-cache */
878 VTD_DPRINTF(CACHE, "update context-cache bus %d devfn %d "
879 "(hi %"PRIx64 " lo %"PRIx64 " gen %"PRIu32 "->%"PRIu32 ")",
880 bus_num, devfn, ce.hi, ce.lo,
881 cc_entry->context_cache_gen, s->context_cache_gen);
882 cc_entry->context_entry = ce;
883 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 884 }
885
886 ret_fr = vtd_gpa_to_slpte(&ce, addr, is_write, &slpte, &level,
887 &reads, &writes);
888 if (ret_fr) {
889 ret_fr = -ret_fr;
890 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
891 VTD_DPRINTF(FLOG, "fault processing is disabled for DMA requests "
892 "through this context-entry (with FPD Set)");
893 } else {
894 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
895 }
896 return;
897 }
898
d66b969b 899 page_mask = vtd_slpt_level_page_mask(level);
b5a280c0 900 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
d66b969b 901 reads, writes, level);
b5a280c0 902out:
d66b969b
JW		 903 entry->iova = addr & page_mask;
904 entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
905 entry->addr_mask = ~page_mask;
1da12ec4
LT		 906 entry->perm = (writes ? 2 : 0) + (reads ? 1 : 0);
907}
908
909static void vtd_root_table_setup(IntelIOMMUState *s)
910{
911 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
912 s->root_extended = s->root & VTD_RTADDR_RTT;
913 s->root &= VTD_RTADDR_ADDR_MASK;
914
915 VTD_DPRINTF(CSR, "root_table addr 0x%"PRIx64 " %s", s->root,
916 (s->root_extended ? "(extended)" : ""));
917}
918
02a2cbc8
PX		 919static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
920 uint32_t index, uint32_t mask)
921{
922 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
923}
924
a5861439
PX		 925static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
926{
927 uint64_t value = 0;
928 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
929 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
930 s->intr_root = value & VTD_IRTA_ADDR_MASK;
28589311 931 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 932
02a2cbc8
PX		 933 /* Notify global invalidation */
934 vtd_iec_notify_all(s, true, 0, 0);
a5861439
PX		 935
936 VTD_DPRINTF(CSR, "int remap table addr 0x%"PRIx64 " size %"PRIu32,
937 s->intr_root, s->intr_size);
938}
939
d92fa2dc
LT		 940static void vtd_context_global_invalidate(IntelIOMMUState *s)
941{
942 s->context_cache_gen++;
943 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
944 vtd_reset_context_cache(s);
945 }
946}
947
7df953bd
KO		 948
949/* Find the VTD address space currently associated with a given bus number,
950 */
951static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
952{
953 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
954 if (!vtd_bus) {
955 /* Iterate over the registered buses to find the one
956 * which currently hold this bus number, and update the bus_num lookup table:
957 */
958 GHashTableIter iter;
959
960 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
961 while (g_hash_table_iter_next (&iter, NULL, (void**)&vtd_bus)) {
962 if (pci_bus_num(vtd_bus->bus) == bus_num) {
963 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
964 return vtd_bus;
965 }
966 }
967 }
968 return vtd_bus;
969}
970
d92fa2dc
LT		 971/* Do a context-cache device-selective invalidation.
972 * @func_mask: FM field after shifting
973 */
974static void vtd_context_device_invalidate(IntelIOMMUState *s,
975 uint16_t source_id,
976 uint16_t func_mask)
977{
978 uint16_t mask;
7df953bd 979 VTDBus *vtd_bus;
d92fa2dc
LT		 980 VTDAddressSpace *vtd_as;
981 uint16_t devfn;
982 uint16_t devfn_it;
983
984 switch (func_mask & 3) {
985 case 0:
986 mask = 0; /* No bits in the SID field masked */
987 break;
988 case 1:
989 mask = 4; /* Mask bit 2 in the SID field */
990 break;
991 case 2:
992 mask = 6; /* Mask bit 2:1 in the SID field */
993 break;
994 case 3:
995 mask = 7; /* Mask bit 2:0 in the SID field */
996 break;
997 }
6cb99acc 998 mask = ~mask;
d92fa2dc
LT		 999 VTD_DPRINTF(INV, "device-selective invalidation source 0x%"PRIx16
1000 " mask %"PRIu16, source_id, mask);
7df953bd
KO		 1001 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1002 if (vtd_bus) {
d92fa2dc 1003 devfn = VTD_SID_TO_DEVFN(source_id);
04af0e18 1004 for (devfn_it = 0; devfn_it < X86_IOMMU_PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 1005 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 1006 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
1007 VTD_DPRINTF(INV, "invalidate context-cahce of devfn 0x%"PRIx16,
1008 devfn_it);
1009 vtd_as->context_cache_entry.context_cache_gen = 0;
1010 }
1011 }
1012 }
1013}
1014
1da12ec4
LT		 1015/* Context-cache invalidation
1016 * Returns the Context Actual Invalidation Granularity.
1017 * @val: the content of the CCMD_REG
1018 */
1019static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1020{
1021 uint64_t caig;
1022 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1023
1024 switch (type) {
d92fa2dc
LT		 1025 case VTD_CCMD_DOMAIN_INVL:
1026 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1027 (uint16_t)VTD_CCMD_DID(val));
1028 /* Fall through */
1da12ec4 1029 case VTD_CCMD_GLOBAL_INVL:
d92fa2dc 1030 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1031 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1032 vtd_context_global_invalidate(s);
1da12ec4
LT		 1033 break;
1034
1035 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1036 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1037 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1038 break;
1039
1040 default:
d92fa2dc 1041 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1042 caig = 0;
1043 }
1044 return caig;
1045}
1046
b5a280c0
LT		 1047static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1048{
1049 vtd_reset_iotlb(s);
1050}
1051
1052static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1053{
1054 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1055 &domain_id);
1056}
1057
1058static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1059 hwaddr addr, uint8_t am)
1060{
1061 VTDIOTLBPageInvInfo info;
1062
1063 assert(am <= VTD_MAMV);
1064 info.domain_id = domain_id;
d66b969b 1065 info.addr = addr;
b5a280c0
LT		 1066 info.mask = ~((1 << am) - 1);
1067 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
1068}
1069
1da12ec4
LT		 1070/* Flush IOTLB
1071 * Returns the IOTLB Actual Invalidation Granularity.
1072 * @val: the content of the IOTLB_REG
1073 */
1074static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1075{
1076 uint64_t iaig;
1077 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1078 uint16_t domain_id;
1079 hwaddr addr;
1080 uint8_t am;
1da12ec4
LT		 1081
1082 switch (type) {
1083 case VTD_TLB_GLOBAL_FLUSH:
b5a280c0 1084 VTD_DPRINTF(INV, "global invalidation");
1da12ec4 1085 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1086 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1087 break;
1088
1089 case VTD_TLB_DSI_FLUSH:
b5a280c0
LT		 1090 domain_id = VTD_TLB_DID(val);
1091 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1092 domain_id);
1da12ec4 1093 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1094 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1095 break;
1096
1097 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1098 domain_id = VTD_TLB_DID(val);
1099 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1100 am = VTD_IVA_AM(addr);
1101 addr = VTD_IVA_ADDR(addr);
1102 VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1103 " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1104 if (am > VTD_MAMV) {
1105 VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1106 "%"PRIu8, (uint8_t)VTD_MAMV);
1107 iaig = 0;
1108 break;
1109 }
1da12ec4 1110 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1111 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1112 break;
1113
1114 default:
b5a280c0 1115 VTD_DPRINTF(GENERAL, "error: invalid granularity");
1da12ec4
LT		 1116 iaig = 0;
1117 }
1118 return iaig;
1119}
1120
ed7b8fbc
LT		 1121static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)
1122{
1123 return s->iq_tail == 0;
1124}
1125
1126static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1127{
1128 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1129 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1130}
1131
1132static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1133{
1134 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1135
1136 VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off"));
1137 if (en) {
1138 if (vtd_queued_inv_enable_check(s)) {
1139 s->iq = iqa_val & VTD_IQA_IQA_MASK;
1140 /* 2^(x+8) entries */
1141 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1142 s->qi_enabled = true;
1143 VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
1144 VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
1145 s->iq, s->iq_size);
1146 /* Ok - report back to driver */
1147 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1148 } else {
1149 VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: "
1150 "tail %"PRIu16, s->iq_tail);
1151 }
1152 } else {
1153 if (vtd_queued_inv_disable_check(s)) {
1154 /* disable Queued Invalidation */
1155 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1156 s->iq_head = 0;
1157 s->qi_enabled = false;
1158 /* Ok - report back to driver */
1159 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1160 } else {
1161 VTD_DPRINTF(GENERAL, "error: can't disable Queued Invalidation: "
1162 "head %"PRIu16 ", tail %"PRIu16
1163 ", last_descriptor %"PRIu8,
1164 s->iq_head, s->iq_tail, s->iq_last_desc_type);
1165 }
1166 }
1167}
1168
1da12ec4
LT		 1169/* Set Root Table Pointer */
1170static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1171{
1172 VTD_DPRINTF(CSR, "set Root Table Pointer");
1173
1174 vtd_root_table_setup(s);
1175 /* Ok - report back to driver */
1176 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1177}
1178
a5861439
PX		 1179/* Set Interrupt Remap Table Pointer */
1180static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1181{
1182 VTD_DPRINTF(CSR, "set Interrupt Remap Table Pointer");
1183
1184 vtd_interrupt_remap_table_setup(s);
1185 /* Ok - report back to driver */
1186 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1187}
1188
1da12ec4
LT		 1189/* Handle Translation Enable/Disable */
1190static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1191{
1192 VTD_DPRINTF(CSR, "Translation Enable %s", (en ? "on" : "off"));
1193
1194 if (en) {
1195 s->dmar_enabled = true;
1196 /* Ok - report back to driver */
1197 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1198 } else {
1199 s->dmar_enabled = false;
1200
1201 /* Clear the index of Fault Recording Register */
1202 s->next_frcd_reg = 0;
1203 /* Ok - report back to driver */
1204 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1205 }
1206}
1207
80de52ba
PX		 1208/* Handle Interrupt Remap Enable/Disable */
1209static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1210{
1211 VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
1212
1213 if (en) {
1214 s->intr_enabled = true;
1215 /* Ok - report back to driver */
1216 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1217 } else {
1218 s->intr_enabled = false;
1219 /* Ok - report back to driver */
1220 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1221 }
1222}
1223
1da12ec4
LT		 1224/* Handle write to Global Command Register */
1225static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1226{
1227 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1228 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1229 uint32_t changed = status ^ val;
1230
1231 VTD_DPRINTF(CSR, "value 0x%"PRIx32 " status 0x%"PRIx32, val, status);
1232 if (changed & VTD_GCMD_TE) {
1233 /* Translation enable/disable */
1234 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1235 }
1236 if (val & VTD_GCMD_SRTP) {
1237 /* Set/update the root-table pointer */
1238 vtd_handle_gcmd_srtp(s);
1239 }
ed7b8fbc
LT		 1240 if (changed & VTD_GCMD_QIE) {
1241 /* Queued Invalidation Enable */
1242 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1243 }
a5861439
PX		 1244 if (val & VTD_GCMD_SIRTP) {
1245 /* Set/update the interrupt remapping root-table pointer */
1246 vtd_handle_gcmd_sirtp(s);
1247 }
80de52ba
PX		 1248 if (changed & VTD_GCMD_IRE) {
1249 /* Interrupt remap enable/disable */
1250 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1251 }
1da12ec4
LT		 1252}
1253
1254/* Handle write to Context Command Register */
1255static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1256{
1257 uint64_t ret;
1258 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1259
1260 /* Context-cache invalidation request */
1261 if (val & VTD_CCMD_ICC) {
ed7b8fbc
LT		 1262 if (s->qi_enabled) {
1263 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1264 "should not use register-based invalidation");
1265 return;
1266 }
1da12ec4
LT		 1267 ret = vtd_context_cache_invalidate(s, val);
1268 /* Invalidation completed. Change something to show */
1269 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1270 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1271 ret);
1272 VTD_DPRINTF(INV, "CCMD_REG write-back val: 0x%"PRIx64, ret);
1273 }
1274}
1275
1276/* Handle write to IOTLB Invalidation Register */
1277static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1278{
1279 uint64_t ret;
1280 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1281
1282 /* IOTLB invalidation request */
1283 if (val & VTD_TLB_IVT) {
ed7b8fbc
LT		 1284 if (s->qi_enabled) {
1285 VTD_DPRINTF(GENERAL, "error: Queued Invalidation enabled, "
1286 "should not use register-based invalidation");
1287 return;
1288 }
1da12ec4
LT		 1289 ret = vtd_iotlb_flush(s, val);
1290 /* Invalidation completed. Change something to show */
1291 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1292 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1293 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1294 VTD_DPRINTF(INV, "IOTLB_REG write-back val: 0x%"PRIx64, ret);
1295 }
1296}
1297
ed7b8fbc
LT		 1298/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1299static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1300 VTDInvDesc *inv_desc)
1301{
1302 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1303 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1304 sizeof(*inv_desc))) {
1305 VTD_DPRINTF(GENERAL, "error: fail to fetch Invalidation Descriptor "
1306 "base_addr 0x%"PRIx64 " offset %"PRIu32, base_addr, offset);
1307 inv_desc->lo = 0;
1308 inv_desc->hi = 0;
1309
1310 return false;
1311 }
1312 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1313 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1314 return true;
1315}
1316
1317static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1318{
1319 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1320 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
1321 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Invalidation "
1322 "Wait Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1323 inv_desc->hi, inv_desc->lo);
1324 return false;
1325 }
1326 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1327 /* Status Write */
1328 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1329 VTD_INV_DESC_WAIT_DATA_SHIFT);
1330
1331 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1332
1333 /* FIXME: need to be masked with HAW? */
1334 dma_addr_t status_addr = inv_desc->hi;
1335 VTD_DPRINTF(INV, "status data 0x%x, status addr 0x%"PRIx64,
1336 status_data, status_addr);
1337 status_data = cpu_to_le32(status_data);
1338 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1339 sizeof(status_data))) {
1340 VTD_DPRINTF(GENERAL, "error: fail to perform a coherent write");
1341 return false;
1342 }
1343 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1344 /* Interrupt flag */
1345 VTD_DPRINTF(INV, "Invalidation Wait Descriptor interrupt completion");
1346 vtd_generate_completion_event(s);
1347 } else {
1348 VTD_DPRINTF(GENERAL, "error: invalid Invalidation Wait Descriptor: "
1349 "hi 0x%"PRIx64 " lo 0x%"PRIx64, inv_desc->hi, inv_desc->lo);
1350 return false;
1351 }
1352 return true;
1353}
1354
d92fa2dc
LT		 1355static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1356 VTDInvDesc *inv_desc)
1357{
1358 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
1359 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Context-cache "
1360 "Invalidate Descriptor");
1361 return false;
1362 }
1363 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1364 case VTD_INV_DESC_CC_DOMAIN:
1365 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1366 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
1367 /* Fall through */
1368 case VTD_INV_DESC_CC_GLOBAL:
1369 VTD_DPRINTF(INV, "global invalidation");
1370 vtd_context_global_invalidate(s);
1371 break;
1372
1373 case VTD_INV_DESC_CC_DEVICE:
1374 vtd_context_device_invalidate(s, VTD_INV_DESC_CC_SID(inv_desc->lo),
1375 VTD_INV_DESC_CC_FM(inv_desc->lo));
1376 break;
1377
1378 default:
1379 VTD_DPRINTF(GENERAL, "error: invalid granularity in Context-cache "
1380 "Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1381 inv_desc->hi, inv_desc->lo);
1382 return false;
1383 }
1384 return true;
1385}
1386
b5a280c0
LT		 1387static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1388{
1389 uint16_t domain_id;
1390 uint8_t am;
1391 hwaddr addr;
1392
1393 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1394 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
1395 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in IOTLB "
1396 "Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1397 inv_desc->hi, inv_desc->lo);
1398 return false;
1399 }
1400
1401 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1402 case VTD_INV_DESC_IOTLB_GLOBAL:
1403 VTD_DPRINTF(INV, "global invalidation");
1404 vtd_iotlb_global_invalidate(s);
1405 break;
1406
1407 case VTD_INV_DESC_IOTLB_DOMAIN:
1408 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1409 VTD_DPRINTF(INV, "domain-selective invalidation domain 0x%"PRIx16,
1410 domain_id);
1411 vtd_iotlb_domain_invalidate(s, domain_id);
1412 break;
1413
1414 case VTD_INV_DESC_IOTLB_PAGE:
1415 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1416 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1417 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
1418 VTD_DPRINTF(INV, "page-selective invalidation domain 0x%"PRIx16
1419 " addr 0x%"PRIx64 " mask %"PRIu8, domain_id, addr, am);
1420 if (am > VTD_MAMV) {
1421 VTD_DPRINTF(GENERAL, "error: supported max address mask value is "
1422 "%"PRIu8, (uint8_t)VTD_MAMV);
1423 return false;
1424 }
1425 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1426 break;
1427
1428 default:
1429 VTD_DPRINTF(GENERAL, "error: invalid granularity in IOTLB Invalidate "
1430 "Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1431 inv_desc->hi, inv_desc->lo);
1432 return false;
1433 }
1434 return true;
1435}
1436
02a2cbc8
PX		 1437static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1438 VTDInvDesc *inv_desc)
1439{
1440 VTD_DPRINTF(INV, "inv ir glob %d index %d mask %d",
1441 inv_desc->iec.granularity,
1442 inv_desc->iec.index,
1443 inv_desc->iec.index_mask);
1444
1445 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1446 inv_desc->iec.index,
1447 inv_desc->iec.index_mask);
554f5e16
JW		 1448 return true;
1449}
1450
1451static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
1452 VTDInvDesc *inv_desc)
1453{
1454 VTDAddressSpace *vtd_dev_as;
1455 IOMMUTLBEntry entry;
1456 struct VTDBus *vtd_bus;
1457 hwaddr addr;
1458 uint64_t sz;
1459 uint16_t sid;
1460 uint8_t devfn;
1461 bool size;
1462 uint8_t bus_num;
1463
1464 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
1465 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
1466 devfn = sid & 0xff;
1467 bus_num = sid >> 8;
1468 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
1469
1470 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
1471 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
1472 VTD_DPRINTF(GENERAL, "error: non-zero reserved field in Device "
1473 "IOTLB Invalidate Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1474 inv_desc->hi, inv_desc->lo);
1475 return false;
1476 }
1477
1478 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
1479 if (!vtd_bus) {
1480 goto done;
1481 }
1482
1483 vtd_dev_as = vtd_bus->dev_as[devfn];
1484 if (!vtd_dev_as) {
1485 goto done;
1486 }
1487
1488 if (size) {
1489 sz = 1 << (ctz64(~(addr | (VTD_PAGE_MASK_4K - 1))) + 1);
1490 addr &= ~(sz - 1);
1491 } else {
1492 sz = VTD_PAGE_SIZE;
1493 }
02a2cbc8 1494
554f5e16
JW		 1495 entry.target_as = &vtd_dev_as->as;
1496 entry.addr_mask = sz - 1;
1497 entry.iova = addr;
1498 entry.perm = IOMMU_NONE;
1499 entry.translated_addr = 0;
1500 memory_region_notify_iommu(entry.target_as->root, entry);
1501
1502done:
02a2cbc8
PX		 1503 return true;
1504}
1505
ed7b8fbc
LT		 1506static bool vtd_process_inv_desc(IntelIOMMUState *s)
1507{
1508 VTDInvDesc inv_desc;
1509 uint8_t desc_type;
1510
1511 VTD_DPRINTF(INV, "iq head %"PRIu16, s->iq_head);
1512 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1513 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1514 return false;
1515 }
1516 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1517 /* FIXME: should update at first or at last? */
1518 s->iq_last_desc_type = desc_type;
1519
1520 switch (desc_type) {
1521 case VTD_INV_DESC_CC:
1522 VTD_DPRINTF(INV, "Context-cache Invalidate Descriptor hi 0x%"PRIx64
1523 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1524 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1525 return false;
1526 }
ed7b8fbc
LT		 1527 break;
1528
1529 case VTD_INV_DESC_IOTLB:
1530 VTD_DPRINTF(INV, "IOTLB Invalidate Descriptor hi 0x%"PRIx64
1531 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1532 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1533 return false;
1534 }
ed7b8fbc
LT		 1535 break;
1536
1537 case VTD_INV_DESC_WAIT:
1538 VTD_DPRINTF(INV, "Invalidation Wait Descriptor hi 0x%"PRIx64
1539 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1540 if (!vtd_process_wait_desc(s, &inv_desc)) {
1541 return false;
1542 }
1543 break;
1544
b7910472 1545 case VTD_INV_DESC_IEC:
02a2cbc8
PX		 1546 VTD_DPRINTF(INV, "Invalidation Interrupt Entry Cache "
1547 "Descriptor hi 0x%"PRIx64 " lo 0x%"PRIx64,
1548 inv_desc.hi, inv_desc.lo);
1549 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1550 return false;
1551 }
b7910472
PX		 1552 break;
1553
554f5e16
JW		 1554 case VTD_INV_DESC_DEVICE:
1555 VTD_DPRINTF(INV, "Device IOTLB Invalidation Descriptor hi 0x%"PRIx64
1556 " lo 0x%"PRIx64, inv_desc.hi, inv_desc.lo);
1557 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
1558 return false;
1559 }
1560 break;
1561
ed7b8fbc
LT		 1562 default:
1563 VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type "
1564 "hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,
1565 inv_desc.hi, inv_desc.lo, desc_type);
1566 return false;
1567 }
1568 s->iq_head++;
1569 if (s->iq_head == s->iq_size) {
1570 s->iq_head = 0;
1571 }
1572 return true;
1573}
1574
1575/* Try to fetch and process more Invalidation Descriptors */
1576static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1577{
1578 VTD_DPRINTF(INV, "fetch Invalidation Descriptors");
1579 if (s->iq_tail >= s->iq_size) {
1580 /* Detects an invalid Tail pointer */
1581 VTD_DPRINTF(GENERAL, "error: iq_tail is %"PRIu16
1582 " while iq_size is %"PRIu16, s->iq_tail, s->iq_size);
1583 vtd_handle_inv_queue_error(s);
1584 return;
1585 }
1586 while (s->iq_head != s->iq_tail) {
1587 if (!vtd_process_inv_desc(s)) {
1588 /* Invalidation Queue Errors */
1589 vtd_handle_inv_queue_error(s);
1590 break;
1591 }
1592 /* Must update the IQH_REG in time */
1593 vtd_set_quad_raw(s, DMAR_IQH_REG,
1594 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1595 VTD_IQH_QH_MASK);
1596 }
1597}
1598
1599/* Handle write to Invalidation Queue Tail Register */
1600static void vtd_handle_iqt_write(IntelIOMMUState *s)
1601{
1602 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1603
1604 s->iq_tail = VTD_IQT_QT(val);
1605 VTD_DPRINTF(INV, "set iq tail %"PRIu16, s->iq_tail);
1606 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1607 /* Process Invalidation Queue here */
1608 vtd_fetch_inv_desc(s);
1609 }
1610}
1611
1da12ec4
LT		 1612static void vtd_handle_fsts_write(IntelIOMMUState *s)
1613{
1614 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1615 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1616 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1617
1618 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1619 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1620 VTD_DPRINTF(FLOG, "all pending interrupt conditions serviced, clear "
1621 "IP field of FECTL_REG");
1622 }
ed7b8fbc
LT		 1623 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1624 * Descriptors if there are any when Queued Invalidation is enabled?
1625 */
1da12ec4
LT		 1626}
1627
1628static void vtd_handle_fectl_write(IntelIOMMUState *s)
1629{
1630 uint32_t fectl_reg;
1631 /* FIXME: when software clears the IM field, check the IP field. But do we
1632 * need to compare the old value and the new value to conclude that
1633 * software clears the IM field? Or just check if the IM field is zero?
1634 */
1635 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1636 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1637 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1638 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1639 VTD_DPRINTF(FLOG, "IM field is cleared, generate "
1640 "fault event interrupt");
1641 }
1642}
1643
ed7b8fbc
LT		 1644static void vtd_handle_ics_write(IntelIOMMUState *s)
1645{
1646 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1647 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1648
1649 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
1650 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1651 VTD_DPRINTF(INV, "pending completion interrupt condition serviced, "
1652 "clear IP field of IECTL_REG");
1653 }
1654}
1655
1656static void vtd_handle_iectl_write(IntelIOMMUState *s)
1657{
1658 uint32_t iectl_reg;
1659 /* FIXME: when software clears the IM field, check the IP field. But do we
1660 * need to compare the old value and the new value to conclude that
1661 * software clears the IM field? Or just check if the IM field is zero?
1662 */
1663 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1664 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
1665 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
1666 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
1667 VTD_DPRINTF(INV, "IM field is cleared, generate "
1668 "invalidation event interrupt");
1669 }
1670}
1671
1da12ec4
LT		 1672static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
1673{
1674 IntelIOMMUState *s = opaque;
1675 uint64_t val;
1676
1677 if (addr + size > DMAR_REG_SIZE) {
1678 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1679 ", got 0x%"PRIx64 " %d",
1680 (uint64_t)DMAR_REG_SIZE, addr, size);
1681 return (uint64_t)-1;
1682 }
1683
1684 switch (addr) {
1685 /* Root Table Address Register, 64-bit */
1686 case DMAR_RTADDR_REG:
1687 if (size == 4) {
1688 val = s->root & ((1ULL << 32) - 1);
1689 } else {
1690 val = s->root;
1691 }
1692 break;
1693
1694 case DMAR_RTADDR_REG_HI:
1695 assert(size == 4);
1696 val = s->root >> 32;
1697 break;
1698
ed7b8fbc
LT		 1699 /* Invalidation Queue Address Register, 64-bit */
1700 case DMAR_IQA_REG:
1701 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
1702 if (size == 4) {
1703 val = val & ((1ULL << 32) - 1);
1704 }
1705 break;
1706
1707 case DMAR_IQA_REG_HI:
1708 assert(size == 4);
1709 val = s->iq >> 32;
1710 break;
1711
1da12ec4
LT		 1712 default:
1713 if (size == 4) {
1714 val = vtd_get_long(s, addr);
1715 } else {
1716 val = vtd_get_quad(s, addr);
1717 }
1718 }
1719 VTD_DPRINTF(CSR, "addr 0x%"PRIx64 " size %d val 0x%"PRIx64,
1720 addr, size, val);
1721 return val;
1722}
1723
1724static void vtd_mem_write(void *opaque, hwaddr addr,
1725 uint64_t val, unsigned size)
1726{
1727 IntelIOMMUState *s = opaque;
1728
1729 if (addr + size > DMAR_REG_SIZE) {
1730 VTD_DPRINTF(GENERAL, "error: addr outside region: max 0x%"PRIx64
1731 ", got 0x%"PRIx64 " %d",
1732 (uint64_t)DMAR_REG_SIZE, addr, size);
1733 return;
1734 }
1735
1736 switch (addr) {
1737 /* Global Command Register, 32-bit */
1738 case DMAR_GCMD_REG:
1739 VTD_DPRINTF(CSR, "DMAR_GCMD_REG write addr 0x%"PRIx64
1740 ", size %d, val 0x%"PRIx64, addr, size, val);
1741 vtd_set_long(s, addr, val);
1742 vtd_handle_gcmd_write(s);
1743 break;
1744
1745 /* Context Command Register, 64-bit */
1746 case DMAR_CCMD_REG:
1747 VTD_DPRINTF(CSR, "DMAR_CCMD_REG write addr 0x%"PRIx64
1748 ", size %d, val 0x%"PRIx64, addr, size, val);
1749 if (size == 4) {
1750 vtd_set_long(s, addr, val);
1751 } else {
1752 vtd_set_quad(s, addr, val);
1753 vtd_handle_ccmd_write(s);
1754 }
1755 break;
1756
1757 case DMAR_CCMD_REG_HI:
1758 VTD_DPRINTF(CSR, "DMAR_CCMD_REG_HI write addr 0x%"PRIx64
1759 ", size %d, val 0x%"PRIx64, addr, size, val);
1760 assert(size == 4);
1761 vtd_set_long(s, addr, val);
1762 vtd_handle_ccmd_write(s);
1763 break;
1764
1765 /* IOTLB Invalidation Register, 64-bit */
1766 case DMAR_IOTLB_REG:
1767 VTD_DPRINTF(INV, "DMAR_IOTLB_REG write addr 0x%"PRIx64
1768 ", size %d, val 0x%"PRIx64, addr, size, val);
1769 if (size == 4) {
1770 vtd_set_long(s, addr, val);
1771 } else {
1772 vtd_set_quad(s, addr, val);
1773 vtd_handle_iotlb_write(s);
1774 }
1775 break;
1776
1777 case DMAR_IOTLB_REG_HI:
1778 VTD_DPRINTF(INV, "DMAR_IOTLB_REG_HI write addr 0x%"PRIx64
1779 ", size %d, val 0x%"PRIx64, addr, size, val);
1780 assert(size == 4);
1781 vtd_set_long(s, addr, val);
1782 vtd_handle_iotlb_write(s);
1783 break;
1784
b5a280c0
LT		 1785 /* Invalidate Address Register, 64-bit */
1786 case DMAR_IVA_REG:
1787 VTD_DPRINTF(INV, "DMAR_IVA_REG write addr 0x%"PRIx64
1788 ", size %d, val 0x%"PRIx64, addr, size, val);
1789 if (size == 4) {
1790 vtd_set_long(s, addr, val);
1791 } else {
1792 vtd_set_quad(s, addr, val);
1793 }
1794 break;
1795
1796 case DMAR_IVA_REG_HI:
1797 VTD_DPRINTF(INV, "DMAR_IVA_REG_HI write addr 0x%"PRIx64
1798 ", size %d, val 0x%"PRIx64, addr, size, val);
1799 assert(size == 4);
1800 vtd_set_long(s, addr, val);
1801 break;
1802
1da12ec4
LT		 1803 /* Fault Status Register, 32-bit */
1804 case DMAR_FSTS_REG:
1805 VTD_DPRINTF(FLOG, "DMAR_FSTS_REG write addr 0x%"PRIx64
1806 ", size %d, val 0x%"PRIx64, addr, size, val);
1807 assert(size == 4);
1808 vtd_set_long(s, addr, val);
1809 vtd_handle_fsts_write(s);
1810 break;
1811
1812 /* Fault Event Control Register, 32-bit */
1813 case DMAR_FECTL_REG:
1814 VTD_DPRINTF(FLOG, "DMAR_FECTL_REG write addr 0x%"PRIx64
1815 ", size %d, val 0x%"PRIx64, addr, size, val);
1816 assert(size == 4);
1817 vtd_set_long(s, addr, val);
1818 vtd_handle_fectl_write(s);
1819 break;
1820
1821 /* Fault Event Data Register, 32-bit */
1822 case DMAR_FEDATA_REG:
1823 VTD_DPRINTF(FLOG, "DMAR_FEDATA_REG write addr 0x%"PRIx64
1824 ", size %d, val 0x%"PRIx64, addr, size, val);
1825 assert(size == 4);
1826 vtd_set_long(s, addr, val);
1827 break;
1828
1829 /* Fault Event Address Register, 32-bit */
1830 case DMAR_FEADDR_REG:
1831 VTD_DPRINTF(FLOG, "DMAR_FEADDR_REG write addr 0x%"PRIx64
1832 ", size %d, val 0x%"PRIx64, addr, size, val);
1833 assert(size == 4);
1834 vtd_set_long(s, addr, val);
1835 break;
1836
1837 /* Fault Event Upper Address Register, 32-bit */
1838 case DMAR_FEUADDR_REG:
1839 VTD_DPRINTF(FLOG, "DMAR_FEUADDR_REG write addr 0x%"PRIx64
1840 ", size %d, val 0x%"PRIx64, addr, size, val);
1841 assert(size == 4);
1842 vtd_set_long(s, addr, val);
1843 break;
1844
1845 /* Protected Memory Enable Register, 32-bit */
1846 case DMAR_PMEN_REG:
1847 VTD_DPRINTF(CSR, "DMAR_PMEN_REG write addr 0x%"PRIx64
1848 ", size %d, val 0x%"PRIx64, addr, size, val);
1849 assert(size == 4);
1850 vtd_set_long(s, addr, val);
1851 break;
1852
1853 /* Root Table Address Register, 64-bit */
1854 case DMAR_RTADDR_REG:
1855 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG write addr 0x%"PRIx64
1856 ", size %d, val 0x%"PRIx64, addr, size, val);
1857 if (size == 4) {
1858 vtd_set_long(s, addr, val);
1859 } else {
1860 vtd_set_quad(s, addr, val);
1861 }
1862 break;
1863
1864 case DMAR_RTADDR_REG_HI:
1865 VTD_DPRINTF(CSR, "DMAR_RTADDR_REG_HI write addr 0x%"PRIx64
1866 ", size %d, val 0x%"PRIx64, addr, size, val);
1867 assert(size == 4);
1868 vtd_set_long(s, addr, val);
1869 break;
1870
ed7b8fbc
LT		 1871 /* Invalidation Queue Tail Register, 64-bit */
1872 case DMAR_IQT_REG:
1873 VTD_DPRINTF(INV, "DMAR_IQT_REG write addr 0x%"PRIx64
1874 ", size %d, val 0x%"PRIx64, addr, size, val);
1875 if (size == 4) {
1876 vtd_set_long(s, addr, val);
1877 } else {
1878 vtd_set_quad(s, addr, val);
1879 }
1880 vtd_handle_iqt_write(s);
1881 break;
1882
1883 case DMAR_IQT_REG_HI:
1884 VTD_DPRINTF(INV, "DMAR_IQT_REG_HI write addr 0x%"PRIx64
1885 ", size %d, val 0x%"PRIx64, addr, size, val);
1886 assert(size == 4);
1887 vtd_set_long(s, addr, val);
1888 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
1889 break;
1890
1891 /* Invalidation Queue Address Register, 64-bit */
1892 case DMAR_IQA_REG:
1893 VTD_DPRINTF(INV, "DMAR_IQA_REG write addr 0x%"PRIx64
1894 ", size %d, val 0x%"PRIx64, addr, size, val);
1895 if (size == 4) {
1896 vtd_set_long(s, addr, val);
1897 } else {
1898 vtd_set_quad(s, addr, val);
1899 }
1900 break;
1901
1902 case DMAR_IQA_REG_HI:
1903 VTD_DPRINTF(INV, "DMAR_IQA_REG_HI write addr 0x%"PRIx64
1904 ", size %d, val 0x%"PRIx64, addr, size, val);
1905 assert(size == 4);
1906 vtd_set_long(s, addr, val);
1907 break;
1908
1909 /* Invalidation Completion Status Register, 32-bit */
1910 case DMAR_ICS_REG:
1911 VTD_DPRINTF(INV, "DMAR_ICS_REG write addr 0x%"PRIx64
1912 ", size %d, val 0x%"PRIx64, addr, size, val);
1913 assert(size == 4);
1914 vtd_set_long(s, addr, val);
1915 vtd_handle_ics_write(s);
1916 break;
1917
1918 /* Invalidation Event Control Register, 32-bit */
1919 case DMAR_IECTL_REG:
1920 VTD_DPRINTF(INV, "DMAR_IECTL_REG write addr 0x%"PRIx64
1921 ", size %d, val 0x%"PRIx64, addr, size, val);
1922 assert(size == 4);
1923 vtd_set_long(s, addr, val);
1924 vtd_handle_iectl_write(s);
1925 break;
1926
1927 /* Invalidation Event Data Register, 32-bit */
1928 case DMAR_IEDATA_REG:
1929 VTD_DPRINTF(INV, "DMAR_IEDATA_REG write addr 0x%"PRIx64
1930 ", size %d, val 0x%"PRIx64, addr, size, val);
1931 assert(size == 4);
1932 vtd_set_long(s, addr, val);
1933 break;
1934
1935 /* Invalidation Event Address Register, 32-bit */
1936 case DMAR_IEADDR_REG:
1937 VTD_DPRINTF(INV, "DMAR_IEADDR_REG write addr 0x%"PRIx64
1938 ", size %d, val 0x%"PRIx64, addr, size, val);
1939 assert(size == 4);
1940 vtd_set_long(s, addr, val);
1941 break;
1942
1943 /* Invalidation Event Upper Address Register, 32-bit */
1944 case DMAR_IEUADDR_REG:
1945 VTD_DPRINTF(INV, "DMAR_IEUADDR_REG write addr 0x%"PRIx64
1946 ", size %d, val 0x%"PRIx64, addr, size, val);
1947 assert(size == 4);
1948 vtd_set_long(s, addr, val);
1949 break;
1950
1da12ec4
LT		 1951 /* Fault Recording Registers, 128-bit */
1952 case DMAR_FRCD_REG_0_0:
1953 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_0 write addr 0x%"PRIx64
1954 ", size %d, val 0x%"PRIx64, addr, size, val);
1955 if (size == 4) {
1956 vtd_set_long(s, addr, val);
1957 } else {
1958 vtd_set_quad(s, addr, val);
1959 }
1960 break;
1961
1962 case DMAR_FRCD_REG_0_1:
1963 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_1 write addr 0x%"PRIx64
1964 ", size %d, val 0x%"PRIx64, addr, size, val);
1965 assert(size == 4);
1966 vtd_set_long(s, addr, val);
1967 break;
1968
1969 case DMAR_FRCD_REG_0_2:
1970 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_2 write addr 0x%"PRIx64
1971 ", size %d, val 0x%"PRIx64, addr, size, val);
1972 if (size == 4) {
1973 vtd_set_long(s, addr, val);
1974 } else {
1975 vtd_set_quad(s, addr, val);
1976 /* May clear bit 127 (Fault), update PPF */
1977 vtd_update_fsts_ppf(s);
1978 }
1979 break;
1980
1981 case DMAR_FRCD_REG_0_3:
1982 VTD_DPRINTF(FLOG, "DMAR_FRCD_REG_0_3 write addr 0x%"PRIx64
1983 ", size %d, val 0x%"PRIx64, addr, size, val);
1984 assert(size == 4);
1985 vtd_set_long(s, addr, val);
1986 /* May clear bit 127 (Fault), update PPF */
1987 vtd_update_fsts_ppf(s);
1988 break;
1989
a5861439
PX		 1990 case DMAR_IRTA_REG:
1991 VTD_DPRINTF(IR, "DMAR_IRTA_REG write addr 0x%"PRIx64
1992 ", size %d, val 0x%"PRIx64, addr, size, val);
1993 if (size == 4) {
1994 vtd_set_long(s, addr, val);
1995 } else {
1996 vtd_set_quad(s, addr, val);
1997 }
1998 break;
1999
2000 case DMAR_IRTA_REG_HI:
2001 VTD_DPRINTF(IR, "DMAR_IRTA_REG_HI write addr 0x%"PRIx64
2002 ", size %d, val 0x%"PRIx64, addr, size, val);
2003 assert(size == 4);
2004 vtd_set_long(s, addr, val);
2005 break;
2006
1da12ec4
LT		 2007 default:
2008 VTD_DPRINTF(GENERAL, "error: unhandled reg write addr 0x%"PRIx64
2009 ", size %d, val 0x%"PRIx64, addr, size, val);
2010 if (size == 4) {
2011 vtd_set_long(s, addr, val);
2012 } else {
2013 vtd_set_quad(s, addr, val);
2014 }
2015 }
2016}
2017
2018static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion *iommu, hwaddr addr,
2019 bool is_write)
2020{
2021 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2022 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4
LT		 2023 IOMMUTLBEntry ret = {
2024 .target_as = &address_space_memory,
2025 .iova = addr,
2026 .translated_addr = 0,
2027 .addr_mask = ~(hwaddr)0,
2028 .perm = IOMMU_NONE,
2029 };
2030
2031 if (!s->dmar_enabled) {
2032 /* DMAR disabled, passthrough, use 4k-page*/
2033 ret.iova = addr & VTD_PAGE_MASK_4K;
2034 ret.translated_addr = addr & VTD_PAGE_MASK_4K;
2035 ret.addr_mask = ~VTD_PAGE_MASK_4K;
2036 ret.perm = IOMMU_RW;
2037 return ret;
2038 }
2039
7df953bd 2040 vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn, addr,
d92fa2dc 2041 is_write, &ret);
1da12ec4
LT		 2042 VTD_DPRINTF(MMU,
2043 "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8
7df953bd 2044 " gpa 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bus),
d92fa2dc
LT		 2045 VTD_PCI_SLOT(vtd_as->devfn), VTD_PCI_FUNC(vtd_as->devfn),
2046 vtd_as->devfn, addr, ret.translated_addr);
1da12ec4
LT		 2047 return ret;
2048}
2049
5bf3d319
PX		 2050static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu,
2051 IOMMUNotifierFlag old,
2052 IOMMUNotifierFlag new)
3cb3b154
AW		 2053{
2054 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2055
a3276f78
PX		 2056 if (new & IOMMU_NOTIFIER_MAP) {
2057 error_report("Device at bus %s addr %02x.%d requires iommu "
2058 "notifier which is currently not supported by "
2059 "intel-iommu emulation",
2060 vtd_as->bus->qbus.name, PCI_SLOT(vtd_as->devfn),
2061 PCI_FUNC(vtd_as->devfn));
2062 exit(1);
2063 }
3cb3b154
AW		 2064}
2065
1da12ec4
LT		 2066static const VMStateDescription vtd_vmstate = {
2067 .name = "iommu-intel",
8cdcf3c1
PX		 2068 .version_id = 1,
2069 .minimum_version_id = 1,
2070 .priority = MIG_PRI_IOMMU,
2071 .fields = (VMStateField[]) {
2072 VMSTATE_UINT64(root, IntelIOMMUState),
2073 VMSTATE_UINT64(intr_root, IntelIOMMUState),
2074 VMSTATE_UINT64(iq, IntelIOMMUState),
2075 VMSTATE_UINT32(intr_size, IntelIOMMUState),
2076 VMSTATE_UINT16(iq_head, IntelIOMMUState),
2077 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
2078 VMSTATE_UINT16(iq_size, IntelIOMMUState),
2079 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
2080 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
2081 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
2082 VMSTATE_BOOL(root_extended, IntelIOMMUState),
2083 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
2084 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
2085 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
2086 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
2087 VMSTATE_END_OF_LIST()
2088 }
1da12ec4
LT		 2089};
2090
2091static const MemoryRegionOps vtd_mem_ops = {
2092 .read = vtd_mem_read,
2093 .write = vtd_mem_write,
2094 .endianness = DEVICE_LITTLE_ENDIAN,
2095 .impl = {
2096 .min_access_size = 4,
2097 .max_access_size = 8,
2098 },
2099 .valid = {
2100 .min_access_size = 4,
2101 .max_access_size = 8,
2102 },
2103};
2104
2105static Property vtd_properties[] = {
2106 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
e6b6af05
RK		 2107 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
2108 ON_OFF_AUTO_AUTO),
fb506e70 2109 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
1da12ec4
LT		 2110 DEFINE_PROP_END_OF_LIST(),
2111};
2112
651e4cef
PX		 2113/* Read IRTE entry with specific index */
2114static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
bc38ee10 2115 VTD_IR_TableEntry *entry, uint16_t sid)
651e4cef 2116{
ede9c94a
PX		 2117 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
2118 {0xffff, 0xfffb, 0xfff9, 0xfff8};
651e4cef 2119 dma_addr_t addr = 0x00;
ede9c94a
PX		 2120 uint16_t mask, source_id;
2121 uint8_t bus, bus_max, bus_min;
651e4cef
PX		 2122
2123 addr = iommu->intr_root + index * sizeof(*entry);
2124 if (dma_memory_read(&address_space_memory, addr, entry,
2125 sizeof(*entry))) {
2126 VTD_DPRINTF(GENERAL, "error: fail to access IR root at 0x%"PRIx64
2127 " + %"PRIu16, iommu->intr_root, index);
2128 return -VTD_FR_IR_ROOT_INVAL;
2129 }
2130
bc38ee10 2131 if (!entry->irte.present) {
651e4cef
PX		 2132 VTD_DPRINTF(GENERAL, "error: present flag not set in IRTE"
2133 " entry index %u value 0x%"PRIx64 " 0x%"PRIx64,
2134 index, le64_to_cpu(entry->data[1]),
2135 le64_to_cpu(entry->data[0]));
2136 return -VTD_FR_IR_ENTRY_P;
2137 }
2138
bc38ee10
MT		 2139 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
2140 entry->irte.__reserved_2) {
651e4cef
PX		 2141 VTD_DPRINTF(GENERAL, "error: IRTE entry index %"PRIu16
2142 " reserved fields non-zero: 0x%"PRIx64 " 0x%"PRIx64,
2143 index, le64_to_cpu(entry->data[1]),
2144 le64_to_cpu(entry->data[0]));
2145 return -VTD_FR_IR_IRTE_RSVD;
2146 }
2147
ede9c94a
PX		 2148 if (sid != X86_IOMMU_SID_INVALID) {
2149 /* Validate IRTE SID */
bc38ee10
MT		 2150 source_id = le32_to_cpu(entry->irte.source_id);
2151 switch (entry->irte.sid_vtype) {
ede9c94a
PX		 2152 case VTD_SVT_NONE:
2153 VTD_DPRINTF(IR, "No SID validation for IRTE index %d", index);
2154 break;
2155
2156 case VTD_SVT_ALL:
bc38ee10 2157 mask = vtd_svt_mask[entry->irte.sid_q];
ede9c94a
PX		 2158 if ((source_id & mask) != (sid & mask)) {
2159 VTD_DPRINTF(GENERAL, "SID validation for IRTE index "
2160 "%d failed (reqid 0x%04x sid 0x%04x)", index,
2161 sid, source_id);
2162 return -VTD_FR_IR_SID_ERR;
2163 }
2164 break;
2165
2166 case VTD_SVT_BUS:
2167 bus_max = source_id >> 8;
2168 bus_min = source_id & 0xff;
2169 bus = sid >> 8;
2170 if (bus > bus_max || bus < bus_min) {
2171 VTD_DPRINTF(GENERAL, "SID validation for IRTE index %d "
2172 "failed (bus %d outside %d-%d)", index, bus,
2173 bus_min, bus_max);
2174 return -VTD_FR_IR_SID_ERR;
2175 }
2176 break;
2177
2178 default:
2179 VTD_DPRINTF(GENERAL, "Invalid SVT bits (0x%x) in IRTE index "
bc38ee10 2180 "%d", entry->irte.sid_vtype, index);
ede9c94a
PX		 2181 /* Take this as verification failure. */
2182 return -VTD_FR_IR_SID_ERR;
2183 break;
2184 }
2185 }
651e4cef
PX		 2186
2187 return 0;
2188}
2189
2190/* Fetch IRQ information of specific IR index */
ede9c94a
PX		 2191static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
2192 VTDIrq *irq, uint16_t sid)
651e4cef 2193{
bc38ee10 2194 VTD_IR_TableEntry irte = {};
651e4cef
PX		 2195 int ret = 0;
2196
ede9c94a 2197 ret = vtd_irte_get(iommu, index, &irte, sid);
651e4cef
PX		 2198 if (ret) {
2199 return ret;
2200 }
2201
bc38ee10
MT		 2202 irq->trigger_mode = irte.irte.trigger_mode;
2203 irq->vector = irte.irte.vector;
2204 irq->delivery_mode = irte.irte.delivery_mode;
2205 irq->dest = le32_to_cpu(irte.irte.dest_id);
28589311 2206 if (!iommu->intr_eime) {
651e4cef
PX		 2207#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2208#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2209 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2210 VTD_IR_APIC_DEST_SHIFT;
2211 }
bc38ee10
MT		 2212 irq->dest_mode = irte.irte.dest_mode;
2213 irq->redir_hint = irte.irte.redir_hint;
651e4cef
PX		 2214
2215 VTD_DPRINTF(IR, "remapping interrupt index %d: trig:%u,vec:%u,"
2216 "deliver:%u,dest:%u,dest_mode:%u", index,
2217 irq->trigger_mode, irq->vector, irq->delivery_mode,
2218 irq->dest, irq->dest_mode);
2219
2220 return 0;
2221}
2222
2223/* Generate one MSI message from VTDIrq info */
2224static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2225{
2226 VTD_MSIMessage msg = {};
2227
2228 /* Generate address bits */
2229 msg.dest_mode = irq->dest_mode;
2230 msg.redir_hint = irq->redir_hint;
2231 msg.dest = irq->dest;
32946019 2232 msg.__addr_hi = irq->dest & 0xffffff00;
651e4cef
PX		 2233 msg.__addr_head = cpu_to_le32(0xfee);
2234 /* Keep this from original MSI address bits */
2235 msg.__not_used = irq->msi_addr_last_bits;
2236
2237 /* Generate data bits */
2238 msg.vector = irq->vector;
2239 msg.delivery_mode = irq->delivery_mode;
2240 msg.level = 1;
2241 msg.trigger_mode = irq->trigger_mode;
2242
2243 msg_out->address = msg.msi_addr;
2244 msg_out->data = msg.msi_data;
2245}
2246
2247/* Interrupt remapping for MSI/MSI-X entry */
2248static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2249 MSIMessage *origin,
ede9c94a
PX		 2250 MSIMessage *translated,
2251 uint16_t sid)
651e4cef
PX		 2252{
2253 int ret = 0;
2254 VTD_IR_MSIAddress addr;
2255 uint16_t index;
09cd058a 2256 VTDIrq irq = {};
651e4cef
PX		 2257
2258 assert(origin && translated);
2259
2260 if (!iommu || !iommu->intr_enabled) {
2261 goto do_not_translate;
2262 }
2263
2264 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
2265 VTD_DPRINTF(GENERAL, "error: MSI addr high 32 bits nonzero"
2266 " during interrupt remapping: 0x%"PRIx32,
2267 (uint32_t)((origin->address & VTD_MSI_ADDR_HI_MASK) >> \
2268 VTD_MSI_ADDR_HI_SHIFT));
2269 return -VTD_FR_IR_REQ_RSVD;
2270 }
2271
2272 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
1a43713b 2273 if (addr.addr.__head != 0xfee) {
651e4cef
PX		 2274 VTD_DPRINTF(GENERAL, "error: MSI addr low 32 bits invalid: "
2275 "0x%"PRIx32, addr.data);
2276 return -VTD_FR_IR_REQ_RSVD;
2277 }
2278
2279 /* This is compatible mode. */
bc38ee10 2280 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
651e4cef
PX		 2281 goto do_not_translate;
2282 }
2283
bc38ee10 2284 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
651e4cef
PX		 2285
2286#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2287#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2288
bc38ee10 2289 if (addr.addr.sub_valid) {
651e4cef
PX		 2290 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2291 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2292 }
2293
ede9c94a 2294 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
651e4cef
PX		 2295 if (ret) {
2296 return ret;
2297 }
2298
bc38ee10 2299 if (addr.addr.sub_valid) {
651e4cef
PX		 2300 VTD_DPRINTF(IR, "received MSI interrupt");
2301 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
2302 VTD_DPRINTF(GENERAL, "error: MSI data bits non-zero for "
2303 "interrupt remappable entry: 0x%"PRIx32,
2304 origin->data);
2305 return -VTD_FR_IR_REQ_RSVD;
2306 }
2307 } else {
2308 uint8_t vector = origin->data & 0xff;
dea651a9
FW		 2309 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
2310
651e4cef
PX		 2311 VTD_DPRINTF(IR, "received IOAPIC interrupt");
2312 /* IOAPIC entry vector should be aligned with IRTE vector
2313 * (see vt-d spec 5.1.5.1). */
2314 if (vector != irq.vector) {
2315 VTD_DPRINTF(GENERAL, "IOAPIC vector inconsistent: "
2316 "entry: %d, IRTE: %d, index: %d",
2317 vector, irq.vector, index);
2318 }
dea651a9
FW		 2319
2320 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2321 * (see vt-d spec 5.1.5.1). */
2322 if (trigger_mode != irq.trigger_mode) {
2323 VTD_DPRINTF(GENERAL, "IOAPIC trigger mode inconsistent: "
2324 "entry: %u, IRTE: %u, index: %d",
2325 trigger_mode, irq.trigger_mode, index);
2326 }
2327
651e4cef
PX		 2328 }
2329
2330 /*
2331 * We'd better keep the last two bits, assuming that guest OS
2332 * might modify it. Keep it does not hurt after all.
2333 */
bc38ee10 2334 irq.msi_addr_last_bits = addr.addr.__not_care;
651e4cef
PX		 2335
2336 /* Translate VTDIrq to MSI message */
2337 vtd_generate_msi_message(&irq, translated);
2338
2339 VTD_DPRINTF(IR, "mapping MSI 0x%"PRIx64":0x%"PRIx32 " -> "
2340 "0x%"PRIx64":0x%"PRIx32, origin->address, origin->data,
2341 translated->address, translated->data);
2342 return 0;
2343
2344do_not_translate:
2345 memcpy(translated, origin, sizeof(*origin));
2346 return 0;
2347}
2348
8b5ed7df
PX		 2349static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2350 MSIMessage *dst, uint16_t sid)
2351{
ede9c94a
PX		 2352 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
2353 src, dst, sid);
8b5ed7df
PX		 2354}
2355
651e4cef
PX		 2356static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2357 uint64_t *data, unsigned size,
2358 MemTxAttrs attrs)
2359{
2360 return MEMTX_OK;
2361}
2362
2363static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2364 uint64_t value, unsigned size,
2365 MemTxAttrs attrs)
2366{
2367 int ret = 0;
09cd058a 2368 MSIMessage from = {}, to = {};
ede9c94a 2369 uint16_t sid = X86_IOMMU_SID_INVALID;
651e4cef
PX		 2370
2371 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2372 from.data = (uint32_t) value;
2373
ede9c94a
PX		 2374 if (!attrs.unspecified) {
2375 /* We have explicit Source ID */
2376 sid = attrs.requester_id;
2377 }
2378
2379 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
651e4cef
PX		 2380 if (ret) {
2381 /* TODO: report error */
2382 VTD_DPRINTF(GENERAL, "int remap fail for addr 0x%"PRIx64
2383 " data 0x%"PRIx32, from.address, from.data);
2384 /* Drop this interrupt */
2385 return MEMTX_ERROR;
2386 }
2387
2388 VTD_DPRINTF(IR, "delivering MSI 0x%"PRIx64":0x%"PRIx32
2389 " for device sid 0x%04x",
2390 to.address, to.data, sid);
2391
32946019 2392 apic_get_class()->send_msi(&to);
651e4cef
PX		 2393
2394 return MEMTX_OK;
2395}
2396
2397static const MemoryRegionOps vtd_mem_ir_ops = {
2398 .read_with_attrs = vtd_mem_ir_read,
2399 .write_with_attrs = vtd_mem_ir_write,
2400 .endianness = DEVICE_LITTLE_ENDIAN,
2401 .impl = {
2402 .min_access_size = 4,
2403 .max_access_size = 4,
2404 },
2405 .valid = {
2406 .min_access_size = 4,
2407 .max_access_size = 4,
2408 },
2409};
7df953bd
KO		 2410
2411VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2412{
2413 uintptr_t key = (uintptr_t)bus;
2414 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2415 VTDAddressSpace *vtd_dev_as;
e0a3c8cc 2416 char name[128];
7df953bd
KO		 2417
2418 if (!vtd_bus) {
2d3fc581
JW		 2419 uintptr_t *new_key = g_malloc(sizeof(*new_key));
2420 *new_key = (uintptr_t)bus;
7df953bd 2421 /* No corresponding free() */
04af0e18
PX		 2422 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
2423 X86_IOMMU_PCI_DEVFN_MAX);
7df953bd 2424 vtd_bus->bus = bus;
2d3fc581 2425 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
7df953bd
KO		 2426 }
2427
2428 vtd_dev_as = vtd_bus->dev_as[devfn];
2429
2430 if (!vtd_dev_as) {
e0a3c8cc 2431 snprintf(name, sizeof(name), "intel_iommu_devfn_%d", devfn);
7df953bd
KO		 2432 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2433
2434 vtd_dev_as->bus = bus;
2435 vtd_dev_as->devfn = (uint8_t)devfn;
2436 vtd_dev_as->iommu_state = s;
2437 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
2438 memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s),
2439 &s->iommu_ops, "intel_iommu", UINT64_MAX);
651e4cef
PX		 2440 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2441 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2442 VTD_INTERRUPT_ADDR_SIZE);
2443 memory_region_add_subregion(&vtd_dev_as->iommu, VTD_INTERRUPT_ADDR_FIRST,
2444 &vtd_dev_as->iommu_ir);
7df953bd 2445 address_space_init(&vtd_dev_as->as,
e0a3c8cc 2446 &vtd_dev_as->iommu, name);
7df953bd
KO		 2447 }
2448 return vtd_dev_as;
2449}
2450
1da12ec4
LT		 2451/* Do the initialization. It will also be called when reset, so pay
2452 * attention when adding new initialization stuff.
2453 */
2454static void vtd_init(IntelIOMMUState *s)
2455{
d54bd7f8
PX		 2456 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2457
1da12ec4
LT		 2458 memset(s->csr, 0, DMAR_REG_SIZE);
2459 memset(s->wmask, 0, DMAR_REG_SIZE);
2460 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2461 memset(s->womask, 0, DMAR_REG_SIZE);
2462
2463 s->iommu_ops.translate = vtd_iommu_translate;
5bf3d319 2464 s->iommu_ops.notify_flag_changed = vtd_iommu_notify_flag_changed;
1da12ec4
LT		 2465 s->root = 0;
2466 s->root_extended = false;
2467 s->dmar_enabled = false;
2468 s->iq_head = 0;
2469 s->iq_tail = 0;
2470 s->iq = 0;
2471 s->iq_size = 0;
2472 s->qi_enabled = false;
2473 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2474 s->next_frcd_reg = 0;
2475 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MGAW |
d66b969b 2476 VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
ed7b8fbc 2477 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2478
d54bd7f8 2479 if (x86_iommu->intr_supported) {
e6b6af05
RK		 2480 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
2481 if (s->intr_eim == ON_OFF_AUTO_ON) {
2482 s->ecap |= VTD_ECAP_EIM;
2483 }
2484 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
d54bd7f8
PX		 2485 }
2486
554f5e16
JW		 2487 if (x86_iommu->dt_supported) {
2488 s->ecap |= VTD_ECAP_DT;
2489 }
2490
d92fa2dc 2491 vtd_reset_context_cache(s);
b5a280c0 2492 vtd_reset_iotlb(s);
d92fa2dc 2493
1da12ec4
LT		 2494 /* Define registers with default values and bit semantics */
2495 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2496 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2497 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2498 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2499 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2500 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2501 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2502 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2503 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2504
2505 /* Advanced Fault Logging not supported */
2506 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2507 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2508 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2509 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2510
2511 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2512 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2513 */
2514 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2515
2516 /* Treated as RO for implementations that PLMR and PHMR fields reported
2517 * as Clear in the CAP_REG.
2518 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2519 */
2520 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2521
ed7b8fbc
LT		 2522 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2523 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2524 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2525 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2526 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2527 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2528 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2529 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2530 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2531
1da12ec4
LT		 2532 /* IOTLB registers */
2533 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2534 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2535 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2536
2537 /* Fault Recording Registers, 128-bit */
2538 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2539 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 2540
2541 /*
28589311 2542 * Interrupt remapping registers.
a5861439 2543 */
28589311 2544 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 2545}
2546
2547/* Should not reset address_spaces when reset because devices will still use
2548 * the address space they got at first (won't ask the bus again).
2549 */
2550static void vtd_reset(DeviceState *dev)
2551{
2552 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2553
2554 VTD_DPRINTF(GENERAL, "");
2555 vtd_init(s);
2556}
2557
621d983a
MA		 2558static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
2559{
2560 IntelIOMMUState *s = opaque;
2561 VTDAddressSpace *vtd_as;
2562
8e7a0a16 2563 assert(0 <= devfn && devfn < X86_IOMMU_PCI_DEVFN_MAX);
621d983a
MA		 2564
2565 vtd_as = vtd_find_add_as(s, bus, devfn);
2566 return &vtd_as->as;
2567}
2568
e6b6af05 2569static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
6333e93c 2570{
e6b6af05
RK		 2571 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2572
6333e93c
RK		 2573 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
2574 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
2575 !kvm_irqchip_is_split()) {
2576 error_setg(errp, "Intel Interrupt Remapping cannot work with "
2577 "kernel-irqchip=on, please use 'split|off'.");
2578 return false;
2579 }
e6b6af05
RK		 2580 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu->intr_supported) {
2581 error_setg(errp, "eim=on cannot be selected without intremap=on");
2582 return false;
2583 }
2584
2585 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
fb506e70
RK		 2586 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
2587 && x86_iommu->intr_supported ?
e6b6af05
RK		 2588 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
2589 }
fb506e70
RK		 2590 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
2591 if (!kvm_irqchip_in_kernel()) {
2592 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
2593 return false;
2594 }
2595 if (!kvm_enable_x2apic()) {
2596 error_setg(errp, "eim=on requires support on the KVM side"
2597 "(X2APIC_API, first shipped in v4.7)");
2598 return false;
2599 }
2600 }
e6b6af05 2601
6333e93c
RK		 2602 return true;
2603}
2604
1da12ec4
LT		 2605static void vtd_realize(DeviceState *dev, Error **errp)
2606{
cb135f59
PX		 2607 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2608 PCIBus *bus = pcms->bus;
1da12ec4 2609 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
4684a204 2610 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
1da12ec4
LT		 2611
2612 VTD_DPRINTF(GENERAL, "");
fb9f5926 2613 x86_iommu->type = TYPE_INTEL;
6333e93c 2614
e6b6af05 2615 if (!vtd_decide_config(s, errp)) {
6333e93c
RK		 2616 return;
2617 }
2618
7df953bd 2619 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 2620 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
2621 "intel_iommu", DMAR_REG_SIZE);
2622 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 2623 /* No corresponding destroy */
2624 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2625 g_free, g_free);
7df953bd
KO		 2626 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
2627 g_free, g_free);
1da12ec4 2628 vtd_init(s);
621d983a
MA		 2629 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
2630 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 2631 /* Pseudo address space under root PCI bus. */
2632 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 2633}
2634
2635static void vtd_class_init(ObjectClass *klass, void *data)
2636{
2637 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 2638 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 2639
2640 dc->reset = vtd_reset;
1da12ec4
LT		 2641 dc->vmsd = &vtd_vmstate;
2642 dc->props = vtd_properties;
621d983a 2643 dc->hotpluggable = false;
1c7955c4 2644 x86_class->realize = vtd_realize;
8b5ed7df 2645 x86_class->int_remap = vtd_int_remap;
1da12ec4
LT		 2646}
2647
2648static const TypeInfo vtd_info = {
2649 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 2650 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 2651 .instance_size = sizeof(IntelIOMMUState),
2652 .class_init = vtd_class_init,
2653};
2654
2655static void vtd_register_types(void)
2656{
2657 VTD_DPRINTF(GENERAL, "");
2658 type_register_static(&vtd_info);
2659}
2660
2661type_init(vtd_register_types)
QEMU mirror