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hw/i386/pc: Pass the CPUArchIdList array by argument
[mirror_qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
0d09e41a
PB		 27#include "hw/i386/pc.h"
28#include "hw/char/serial.h"
bb3d5ea8 29#include "hw/char/parallel.h"
0d09e41a 30#include "hw/i386/apic.h"
54a40293 31#include "hw/i386/topology.h"
87abaa5d 32#include "hw/i386/fw_cfg.h"
54a40293 33#include "sysemu/cpus.h"
0d09e41a 34#include "hw/block/fdc.h"
83c9f4ca
PB		 35#include "hw/ide.h"
36#include "hw/pci/pci.h"
2118196b 37#include "hw/pci/pci_bus.h"
0d09e41a
PB		 38#include "hw/nvram/fw_cfg.h"
39#include "hw/timer/hpet.h"
a2eb5c0c 40#include "hw/firmware/smbios.h"
83c9f4ca 41#include "hw/loader.h"
ca20cf32 42#include "elf.h"
d6454270 43#include "migration/vmstate.h"
47b43a1f 44#include "multiboot.h"
0d09e41a 45#include "hw/timer/mc146818rtc.h"
55f613ac 46#include "hw/dma/i8257.h"
0d09e41a 47#include "hw/timer/i8254.h"
47973a2d 48#include "hw/input/i8042.h"
64552b6b 49#include "hw/irq.h"
0d09e41a 50#include "hw/audio/pcspk.h"
83c9f4ca
PB		 51#include "hw/pci/msi.h"
52#include "hw/sysbus.h"
9c17d615 53#include "sysemu/sysemu.h"
14a48c1d 54#include "sysemu/tcg.h"
e35704ba 55#include "sysemu/numa.h"
9c17d615 56#include "sysemu/kvm.h"
b1c12027 57#include "sysemu/qtest.h"
71e8a915 58#include "sysemu/reset.h"
54d31236 59#include "sysemu/runstate.h"
1d31f66b 60#include "kvm_i386.h"
0d09e41a 61#include "hw/xen/xen.h"
ab969087 62#include "hw/xen/start_info.h"
a19cbfb3 63#include "ui/qemu-spice.h"
022c62cb
PB		 64#include "exec/memory.h"
65#include "exec/address-spaces.h"
9c17d615 66#include "sysemu/arch_init.h"
1de7afc9 67#include "qemu/bitmap.h"
0c764a9d 68#include "qemu/config-file.h"
d49b6836 69#include "qemu/error-report.h"
922a01a0 70#include "qemu/option.h"
0445259b 71#include "hw/acpi/acpi.h"
5ff020b7 72#include "hw/acpi/cpu_hotplug.h"
c649983b 73#include "hw/boards.h"
72c194f7 74#include "acpi-build.h"
95bee274 75#include "hw/mem/pc-dimm.h"
e688df6b 76#include "qapi/error.h"
9af23989 77#include "qapi/qapi-visit-common.h"
bf1e8939 78#include "qapi/visitor.h"
2e5b09fd 79#include "hw/core/cpu.h"
1255166b 80#include "hw/nmi.h"
a310e653 81#include "hw/usb.h"
60c5e104 82#include "hw/i386/intel_iommu.h"
489983d6 83#include "hw/net/ne2000-isa.h"
06e0259a 84#include "standard-headers/asm-x86/bootparam.h"
a0a49813
DH		 85#include "hw/virtio/virtio-pmem-pci.h"
86#include "hw/mem/memory-device.h"
6f479566
LX		 87#include "sysemu/replay.h"
88#include "qapi/qmp/qerror.h"
97fd1ea8 89#include "config-devices.h"
d6d059ca 90#include "e820_memory_layout.h"
80cabfad 91
471fd342
BS		 92/* debug PC/ISA interrupts */
93//#define DEBUG_IRQ
94
95#ifdef DEBUG_IRQ
96#define DPRINTF(fmt, ...) \
97 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
98#else
99#define DPRINTF(fmt, ...)
100#endif
101
dd703b99 102struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
4c5b10b7 103
ab969087
LM		 104/* Physical Address of PVH entry point read from kernel ELF NOTE */
105static size_t pvh_start_addr;
106
9aec2e52
CH		 107GlobalProperty pc_compat_4_1[] = {};
108const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
109
9bf2650b
CH		 110GlobalProperty pc_compat_4_0[] = {};
111const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
112
abd93cc7 113GlobalProperty pc_compat_3_1[] = {
6c36bddf 114 { "intel-iommu", "dma-drain", "off" },
483c6ad4
BP		 115 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 117 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
118 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
483c6ad4 119 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
9fe8b7be
VK		 120 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
121 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
123 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
125 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
ecb85fe4
PB		 126 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
b0a19803 133 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
f24c3a79 134 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
abd93cc7
MAL		 135};
136const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
137
ddb3235d 138GlobalProperty pc_compat_3_0[] = {
6c36bddf
EH		 139 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
140 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
ddb3235d
MAL		 142};
143const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
144
0d47310b 145GlobalProperty pc_compat_2_12[] = {
6c36bddf
EH		 146 { TYPE_X86_CPU, "legacy-cache", "on" },
147 { TYPE_X86_CPU, "topoext", "off" },
148 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
0d47310b
MAL		 150};
151const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
152
43df70a9 153GlobalProperty pc_compat_2_11[] = {
6c36bddf
EH		 154 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
155 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
43df70a9
MAL		 156};
157const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
158
503224f4 159GlobalProperty pc_compat_2_10[] = {
6c36bddf
EH		 160 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
161 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
162 { "q35-pcihost", "x-pci-hole64-fix", "off" },
503224f4
MAL		 163};
164const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
165
3e803152 166GlobalProperty pc_compat_2_9[] = {
6c36bddf 167 { "mch", "extended-tseg-mbytes", "0" },
3e803152
MAL		 168};
169const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
170
edc24ccd 171GlobalProperty pc_compat_2_8[] = {
6c36bddf
EH		 172 { TYPE_X86_CPU, "tcg-cpuid", "off" },
173 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
174 { "ICH9-LPC", "x-smi-broadcast", "off" },
175 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
176 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
edc24ccd
MAL		 177};
178const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
179
5a995064 180GlobalProperty pc_compat_2_7[] = {
6c36bddf
EH		 181 { TYPE_X86_CPU, "l3-cache", "off" },
182 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
185 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
186 { "isa-pcspk", "migrate", "off" },
5a995064
MAL		 187};
188const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
189
ff8f261f 190GlobalProperty pc_compat_2_6[] = {
6c36bddf
EH		 191 { TYPE_X86_CPU, "cpuid-0xb", "off" },
192 { "vmxnet3", "romfile", "" },
193 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
194 { "apic-common", "legacy-instance-id", "on", }
ff8f261f
MAL		 195};
196const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
197
fe759610
MAL		 198GlobalProperty pc_compat_2_5[] = {};
199const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
200
2f99b9c2
MAL		 201GlobalProperty pc_compat_2_4[] = {
202 PC_CPU_MODEL_IDS("2.4.0")
6c36bddf
EH		 203 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
204 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
206 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
207 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
208 { TYPE_X86_CPU, "check", "off" },
209 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
211 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
213 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
216 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
2f99b9c2
MAL		 217};
218const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
219
8995dd90
MAL		 220GlobalProperty pc_compat_2_3[] = {
221 PC_CPU_MODEL_IDS("2.3.0")
6c36bddf
EH		 222 { TYPE_X86_CPU, "arat", "off" },
223 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
224 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
225 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
226 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
227 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
230 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
8995dd90
MAL		 242};
243const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
244
1c30044e
MAL		 245GlobalProperty pc_compat_2_2[] = {
246 PC_CPU_MODEL_IDS("2.2.0")
6c36bddf
EH		 247 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
248 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
253 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
262 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
264 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
1c30044e
MAL		 265};
266const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
267
c4fc5695
MAL		 268GlobalProperty pc_compat_2_1[] = {
269 PC_CPU_MODEL_IDS("2.1.0")
6c36bddf
EH		 270 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
271 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
c4fc5695
MAL		 272};
273const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
274
a310e653
MAL		 275GlobalProperty pc_compat_2_0[] = {
276 PC_CPU_MODEL_IDS("2.0.0")
6c36bddf
EH		 277 { "virtio-scsi-pci", "any_layout", "off" },
278 { "PIIX4_PM", "memory-hotplug-support", "off" },
279 { "apic", "version", "0x11" },
280 { "nec-usb-xhci", "superspeed-ports-first", "off" },
281 { "nec-usb-xhci", "force-pcie-endcap", "on" },
282 { "pci-serial", "prog_if", "0" },
283 { "pci-serial-2x", "prog_if", "0" },
284 { "pci-serial-4x", "prog_if", "0" },
285 { "virtio-net-pci", "guest_announce", "off" },
286 { "ICH9-LPC", "memory-hotplug-support", "off" },
287 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
288 { "ioh3420", COMPAT_PROP_PCP, "off" },
a310e653
MAL		 289};
290const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
291
292GlobalProperty pc_compat_1_7[] = {
293 PC_CPU_MODEL_IDS("1.7.0")
6c36bddf
EH		 294 { TYPE_USB_DEVICE, "msos-desc", "no" },
295 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
296 { "hpet", HPET_INTCAP, "4" },
a310e653
MAL		 297};
298const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
299
300GlobalProperty pc_compat_1_6[] = {
301 PC_CPU_MODEL_IDS("1.6.0")
6c36bddf
EH		 302 { "e1000", "mitigation", "off" },
303 { "qemu64-" TYPE_X86_CPU, "model", "2" },
304 { "qemu32-" TYPE_X86_CPU, "model", "3" },
305 { "i440FX-pcihost", "short_root_bus", "1" },
306 { "q35-pcihost", "short_root_bus", "1" },
a310e653
MAL		 307};
308const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
309
310GlobalProperty pc_compat_1_5[] = {
311 PC_CPU_MODEL_IDS("1.5.0")
6c36bddf
EH		 312 { "Conroe-" TYPE_X86_CPU, "model", "2" },
313 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
314 { "Penryn-" TYPE_X86_CPU, "model", "2" },
315 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
317 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
318 { "virtio-net-pci", "any_layout", "off" },
319 { TYPE_X86_CPU, "pmu", "on" },
320 { "i440FX-pcihost", "short_root_bus", "0" },
321 { "q35-pcihost", "short_root_bus", "0" },
a310e653
MAL		 322};
323const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
324
325GlobalProperty pc_compat_1_4[] = {
326 PC_CPU_MODEL_IDS("1.4.0")
6c36bddf
EH		 327 { "scsi-hd", "discard_granularity", "0" },
328 { "scsi-cd", "discard_granularity", "0" },
329 { "scsi-disk", "discard_granularity", "0" },
330 { "ide-hd", "discard_granularity", "0" },
331 { "ide-cd", "discard_granularity", "0" },
332 { "ide-drive", "discard_granularity", "0" },
333 { "virtio-blk-pci", "discard_granularity", "0" },
334 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
335 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
336 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
337 { "e1000", "romfile", "pxe-e1000.rom" },
338 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
339 { "pcnet", "romfile", "pxe-pcnet.rom" },
340 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
341 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
342 { "486-" TYPE_X86_CPU, "model", "0" },
343 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
344 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
a310e653
MAL		 345};
346const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
347
b881fbe9 348void gsi_handler(void *opaque, int n, int level)
1452411b 349{
b881fbe9 350 GSIState *s = opaque;
1452411b 351
b881fbe9
JK		 352 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
353 if (n < ISA_NUM_IRQS) {
354 qemu_set_irq(s->i8259_irq[n], level);
1632dc6a 355 }
b881fbe9 356 qemu_set_irq(s->ioapic_irq[n], level);
2e9947d2 357}
1452411b 358
258711c6
JG		 359static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
360 unsigned size)
80cabfad
FB		 361{
362}
363
c02e1eac
JG		 364static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
365{
a6fc23e5 366 return 0xffffffffffffffffULL;
c02e1eac
JG		 367}
368
f929aad6 369/* MSDOS compatibility mode FPU exception support */
d537cf6c 370static qemu_irq ferr_irq;
8e78eb28
IY		 371
372void pc_register_ferr_irq(qemu_irq irq)
373{
374 ferr_irq = irq;
375}
376
f929aad6
FB		 377/* XXX: add IGNNE support */
378void cpu_set_ferr(CPUX86State *s)
379{
d537cf6c 380 qemu_irq_raise(ferr_irq);
f929aad6
FB		 381}
382
258711c6
JG		 383static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
384 unsigned size)
f929aad6 385{
d537cf6c 386 qemu_irq_lower(ferr_irq);
f929aad6
FB		 387}
388
c02e1eac
JG		 389static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
390{
a6fc23e5 391 return 0xffffffffffffffffULL;
c02e1eac
JG		 392}
393
28ab0e2e 394/* TSC handling */
28ab0e2e
FB		 395uint64_t cpu_get_tsc(CPUX86State *env)
396{
4a1418e0 397 return cpu_get_ticks();
28ab0e2e
FB		 398}
399
3de388f6 400/* IRQ handling */
4a8fa5dc 401int cpu_get_pic_interrupt(CPUX86State *env)
3de388f6 402{
6aa9e42f 403 X86CPU *cpu = env_archcpu(env);
3de388f6
FB		 404 int intno;
405
bb93e099
WL		 406 if (!kvm_irqchip_in_kernel()) {
407 intno = apic_get_interrupt(cpu->apic_state);
408 if (intno >= 0) {
409 return intno;
410 }
411 /* read the irq from the PIC */
412 if (!apic_accept_pic_intr(cpu->apic_state)) {
413 return -1;
414 }
cf6d64bf 415 }
0e21e12b 416
3de388f6
FB		 417 intno = pic_read_irq(isa_pic);
418 return intno;
419}
420
d537cf6c 421static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 422{
182735ef
AF		 423 CPUState *cs = first_cpu;
424 X86CPU *cpu = X86_CPU(cs);
a5b38b51 425
471fd342 426 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
bb93e099 427 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
bdc44640 428 CPU_FOREACH(cs) {
182735ef 429 cpu = X86_CPU(cs);
02e51483
CF		 430 if (apic_accept_pic_intr(cpu->apic_state)) {
431 apic_deliver_pic_intr(cpu->apic_state, level);
cf6d64bf 432 }
d5529471
AJ		 433 }
434 } else {
d8ed887b 435 if (level) {
c3affe56 436 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d8ed887b
AF		 437 } else {
438 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
439 }
a5b38b51 440 }
3de388f6
FB		 441}
442
b0a21b53
FB		 443/* PC cmos mappings */
444
80cabfad
FB		 445#define REG_EQUIPMENT_BYTE 0x14
446
bda05509 447int cmos_get_fd_drive_type(FloppyDriveType fd0)
777428f2
FB		 448{
449 int val;
450
451 switch (fd0) {
2da44dd0 452 case FLOPPY_DRIVE_TYPE_144:
777428f2
FB		 453 /* 1.44 Mb 3"5 drive */
454 val = 4;
455 break;
2da44dd0 456 case FLOPPY_DRIVE_TYPE_288:
777428f2
FB		 457 /* 2.88 Mb 3"5 drive */
458 val = 5;
459 break;
2da44dd0 460 case FLOPPY_DRIVE_TYPE_120:
777428f2
FB		 461 /* 1.2 Mb 5"5 drive */
462 val = 2;
463 break;
2da44dd0 464 case FLOPPY_DRIVE_TYPE_NONE:
777428f2
FB		 465 default:
466 val = 0;
467 break;
468 }
469 return val;
470}
471
9139046c
MA		 472static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
473 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 474{
ba6c2377
FB		 475 rtc_set_memory(s, type_ofs, 47);
476 rtc_set_memory(s, info_ofs, cylinders);
477 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
478 rtc_set_memory(s, info_ofs + 2, heads);
479 rtc_set_memory(s, info_ofs + 3, 0xff);
480 rtc_set_memory(s, info_ofs + 4, 0xff);
481 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
482 rtc_set_memory(s, info_ofs + 6, cylinders);
483 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
484 rtc_set_memory(s, info_ofs + 8, sectors);
485}
486
6ac0e82d
AZ		 487/* convert boot_device letter to something recognizable by the bios */
488static int boot_device2nibble(char boot_device)
489{
490 switch(boot_device) {
491 case 'a':
492 case 'b':
493 return 0x01; /* floppy boot */
494 case 'c':
495 return 0x02; /* hard drive boot */
496 case 'd':
497 return 0x03; /* CD-ROM boot */
498 case 'n':
499 return 0x04; /* Network boot */
500 }
501 return 0;
502}
503
ddcd5531 504static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 505{
506#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 507 int nbds, bds[3] = { 0, };
508 int i;
509
510 nbds = strlen(boot_device);
511 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 512 error_setg(errp, "Too many boot devices for PC");
513 return;
0ecdffbb
AJ		 514 }
515 for (i = 0; i < nbds; i++) {
516 bds[i] = boot_device2nibble(boot_device[i]);
517 if (bds[i] == 0) {
ddcd5531
GA		 518 error_setg(errp, "Invalid boot device for PC: '%c'",
519 boot_device[i]);
520 return;
0ecdffbb
AJ		 521 }
522 }
523 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 524 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 525}
526
ddcd5531 527static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 528{
ddcd5531 529 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 530}
531
7444ca4e
LE		 532static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
533{
534 int val, nb, i;
2da44dd0
JS		 535 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
536 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 537
538 /* floppy type */
539 if (floppy) {
540 for (i = 0; i < 2; i++) {
541 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
542 }
543 }
544 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
545 cmos_get_fd_drive_type(fd_type[1]);
546 rtc_set_memory(rtc_state, 0x10, val);
547
548 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
549 nb = 0;
2da44dd0 550 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 551 nb++;
552 }
2da44dd0 553 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 554 nb++;
555 }
556 switch (nb) {
557 case 0:
558 break;
559 case 1:
560 val |= 0x01; /* 1 drive, ready for boot */
561 break;
562 case 2:
563 val |= 0x41; /* 2 drives, ready for boot */
564 break;
565 }
566 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
567}
568
c0897e0c
MA		 569typedef struct pc_cmos_init_late_arg {
570 ISADevice *rtc_state;
9139046c 571 BusState *idebus[2];
c0897e0c
MA		 572} pc_cmos_init_late_arg;
573
b86f4613
LE		 574typedef struct check_fdc_state {
575 ISADevice *floppy;
576 bool multiple;
577} CheckFdcState;
578
579static int check_fdc(Object *obj, void *opaque)
580{
581 CheckFdcState *state = opaque;
582 Object *fdc;
583 uint32_t iobase;
584 Error *local_err = NULL;
585
586 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
587 if (!fdc) {
588 return 0;
589 }
590
1ea1572a 591 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 592 if (local_err || iobase != 0x3f0) {
593 error_free(local_err);
594 return 0;
595 }
596
597 if (state->floppy) {
598 state->multiple = true;
599 } else {
600 state->floppy = ISA_DEVICE(obj);
601 }
602 return 0;
603}
604
605static const char * const fdc_container_path[] = {
606 "/unattached", "/peripheral", "/peripheral-anon"
607};
608
424e4a87
RK		 609/*
610 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
611 * and ACPI objects.
612 */
613ISADevice *pc_find_fdc0(void)
614{
615 int i;
616 Object *container;
617 CheckFdcState state = { 0 };
618
619 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
620 container = container_get(qdev_get_machine(), fdc_container_path[i]);
621 object_child_foreach(container, check_fdc, &state);
622 }
623
624 if (state.multiple) {
3dc6f869
AF		 625 warn_report("multiple floppy disk controllers with "
626 "iobase=0x3f0 have been found");
433672b0 627 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 628 "your intent");
424e4a87
RK		 629 }
630
631 return state.floppy;
632}
633
c0897e0c
MA		 634static void pc_cmos_init_late(void *opaque)
635{
636 pc_cmos_init_late_arg *arg = opaque;
637 ISADevice *s = arg->rtc_state;
9139046c
MA		 638 int16_t cylinders;
639 int8_t heads, sectors;
c0897e0c 640 int val;
2adc99b2 641 int i, trans;
c0897e0c 642
9139046c 643 val = 0;
272f0428
CP		 644 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
645 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 646 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
647 val |= 0xf0;
648 }
272f0428
CP		 649 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
650 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 651 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
652 val |= 0x0f;
653 }
654 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 655
656 val = 0;
657 for (i = 0; i < 4; i++) {
9139046c
MA		 658 /* NOTE: ide_get_geometry() returns the physical
659 geometry. It is always such that: 1 <= sects <= 63, 1
660 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
661 geometry can be different if a translation is done. */
272f0428
CP		 662 if (arg->idebus[i / 2] &&
663 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 664 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 665 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
666 assert((trans & ~3) == 0);
667 val |= trans << (i * 2);
c0897e0c
MA		 668 }
669 }
670 rtc_set_memory(s, 0x39, val);
671
424e4a87 672 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 673
c0897e0c
MA		 674 qemu_unregister_reset(pc_cmos_init_late, opaque);
675}
676
23d30407 677void pc_cmos_init(PCMachineState *pcms,
220a8846 678 BusState *idebus0, BusState *idebus1,
63ffb564 679 ISADevice *s)
80cabfad 680{
7444ca4e 681 int val;
c0897e0c 682 static pc_cmos_init_late_arg arg;
b0a21b53 683
b0a21b53 684 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 685
686 /* memory size */
e89001f7 687 /* base memory (first MiB) */
d471bf3e 688 val = MIN(pcms->below_4g_mem_size / KiB, 640);
333190eb
FB		 689 rtc_set_memory(s, 0x15, val);
690 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 691 /* extended memory (next 64MiB) */
d471bf3e
PB		 692 if (pcms->below_4g_mem_size > 1 * MiB) {
693 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 694 } else {
695 val = 0;
696 }
80cabfad
FB		 697 if (val > 65535)
698 val = 65535;
b0a21b53
FB		 699 rtc_set_memory(s, 0x17, val);
700 rtc_set_memory(s, 0x18, val >> 8);
701 rtc_set_memory(s, 0x30, val);
702 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 703 /* memory between 16MiB and 4GiB */
d471bf3e
PB		 704 if (pcms->below_4g_mem_size > 16 * MiB) {
705 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 706 } else {
9da98861 707 val = 0;
e89001f7 708 }
80cabfad
FB		 709 if (val > 65535)
710 val = 65535;
b0a21b53
FB		 711 rtc_set_memory(s, 0x34, val);
712 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 713 /* memory above 4GiB */
88076854 714 val = pcms->above_4g_mem_size / 65536;
e89001f7
MA		 715 rtc_set_memory(s, 0x5b, val);
716 rtc_set_memory(s, 0x5c, val >> 8);
717 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 718
23d30407 719 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 720 TYPE_ISA_DEVICE,
ec68007a 721 (Object **)&pcms->rtc,
2d996150 722 object_property_allow_set_link,
265b578c 723 OBJ_PROP_LINK_STRONG, &error_abort);
23d30407 724 object_property_set_link(OBJECT(pcms), OBJECT(s),
2d996150 725 "rtc_state", &error_abort);
298e01b6 726
007b0657 727 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
80cabfad 728
b0a21b53 729 val = 0;
b0a21b53
FB		 730 val |= 0x02; /* FPU is there */
731 val |= 0x04; /* PS/2 mouse installed */
732 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
733
b86f4613 734 /* hard drives and FDC */
c0897e0c 735 arg.rtc_state = s;
9139046c
MA		 736 arg.idebus[0] = idebus0;
737 arg.idebus[1] = idebus1;
c0897e0c 738 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 739}
740
a0881c64
AF		 741#define TYPE_PORT92 "port92"
742#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
743
4b78a802
BS		 744/* port 92 stuff: could be split off */
745typedef struct Port92State {
a0881c64
AF		 746 ISADevice parent_obj;
747
23af670e 748 MemoryRegion io;
4b78a802 749 uint8_t outport;
d812b3d6 750 qemu_irq a20_out;
4b78a802
BS		 751} Port92State;
752
93ef4192
AG		 753static void port92_write(void *opaque, hwaddr addr, uint64_t val,
754 unsigned size)
4b78a802
BS		 755{
756 Port92State *s = opaque;
4700a316 757 int oldval = s->outport;
4b78a802 758
c5539cb4 759 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
4b78a802 760 s->outport = val;
d812b3d6 761 qemu_set_irq(s->a20_out, (val >> 1) & 1);
4700a316 762 if ((val & 1) && !(oldval & 1)) {
cf83f140 763 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4b78a802
BS		 764 }
765}
766
93ef4192
AG		 767static uint64_t port92_read(void *opaque, hwaddr addr,
768 unsigned size)
4b78a802
BS		 769{
770 Port92State *s = opaque;
771 uint32_t ret;
772
773 ret = s->outport;
774 DPRINTF("port92: read 0x%02x\n", ret);
775 return ret;
776}
777
d80fe99d 778static void port92_init(ISADevice *dev, qemu_irq a20_out)
4b78a802 779{
d80fe99d 780 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
4b78a802
BS		 781}
782
783static const VMStateDescription vmstate_port92_isa = {
784 .name = "port92",
785 .version_id = 1,
786 .minimum_version_id = 1,
d49805ae 787 .fields = (VMStateField[]) {
4b78a802
BS		 788 VMSTATE_UINT8(outport, Port92State),
789 VMSTATE_END_OF_LIST()
790 }
791};
792
793static void port92_reset(DeviceState *d)
794{
a0881c64 795 Port92State *s = PORT92(d);
4b78a802
BS		 796
797 s->outport &= ~1;
798}
799
23af670e 800static const MemoryRegionOps port92_ops = {
93ef4192
AG		 801 .read = port92_read,
802 .write = port92_write,
803 .impl = {
804 .min_access_size = 1,
805 .max_access_size = 1,
806 },
807 .endianness = DEVICE_LITTLE_ENDIAN,
23af670e
RH		 808};
809
db895a1e 810static void port92_initfn(Object *obj)
4b78a802 811{
db895a1e 812 Port92State *s = PORT92(obj);
4b78a802 813
1437c94b 814 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
23af670e 815
4b78a802 816 s->outport = 0;
d812b3d6
EV		 817
818 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
db895a1e
AF		 819}
820
821static void port92_realizefn(DeviceState *dev, Error **errp)
822{
823 ISADevice *isadev = ISA_DEVICE(dev);
824 Port92State *s = PORT92(dev);
825
826 isa_register_ioport(isadev, &s->io, 0x92);
4b78a802
BS		 827}
828
8f04ee08
AL		 829static void port92_class_initfn(ObjectClass *klass, void *data)
830{
39bffca2 831 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e 832
db895a1e 833 dc->realize = port92_realizefn;
39bffca2
AL		 834 dc->reset = port92_reset;
835 dc->vmsd = &vmstate_port92_isa;
f3b17640
MA		 836 /*
837 * Reason: unlike ordinary ISA devices, this one needs additional
838 * wiring: its A20 output line needs to be wired up by
839 * port92_init().
840 */
e90f2a8c 841 dc->user_creatable = false;
8f04ee08
AL		 842}
843
8c43a6f0 844static const TypeInfo port92_info = {
a0881c64 845 .name = TYPE_PORT92,
39bffca2
AL		 846 .parent = TYPE_ISA_DEVICE,
847 .instance_size = sizeof(Port92State),
db895a1e 848 .instance_init = port92_initfn,
39bffca2 849 .class_init = port92_class_initfn,
4b78a802
BS		 850};
851
83f7d43a 852static void port92_register_types(void)
4b78a802 853{
39bffca2 854 type_register_static(&port92_info);
4b78a802 855}
83f7d43a
AF		 856
857type_init(port92_register_types)
4b78a802 858
956a3e6b 859static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 860{
cc36a7a2 861 X86CPU *cpu = opaque;
e1a23744 862
956a3e6b 863 /* XXX: send to all CPUs ? */
4b78a802 864 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 865 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 866}
867
54a40293
EH		 868/* Calculates initial APIC ID for a specific CPU index
869 *
870 * Currently we need to be able to calculate the APIC ID from the CPU index
871 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
872 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
873 * all CPUs up to max_cpus.
874 */
457cfccc
EH		 875static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
876 unsigned int cpu_index)
54a40293 877{
0e11fc69 878 MachineState *ms = MACHINE(pcms);
457cfccc 879 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
54a40293
EH		 880 uint32_t correct_id;
881 static bool warned;
882
d65af288 883 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores,
0e11fc69 884 ms->smp.threads, cpu_index);
457cfccc 885 if (pcmc->compat_apic_id_mode) {
b1c12027 886 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
54a40293
EH		 887 error_report("APIC IDs set in compatibility mode, "
888 "CPU topology won't match the configuration");
889 warned = true;
890 }
891 return cpu_index;
892 } else {
893 return correct_id;
894 }
895}
896
f2098f48 897static void pc_build_smbios(PCMachineState *pcms)
80cabfad 898{
c97294ec
GS		 899 uint8_t *smbios_tables, *smbios_anchor;
900 size_t smbios_tables_len, smbios_anchor_len;
89cc4a27
WH		 901 struct smbios_phys_mem_area *mem_array;
902 unsigned i, array_count;
38690a1c
IM		 903 MachineState *ms = MACHINE(pcms);
904 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
f2098f48
IM		 905
906 /* tell smbios about cpuid version and features */
907 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
5fd0a9d4 908
a0628599 909 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
5fd0a9d4 910 if (smbios_tables) {
f2098f48 911 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
5fd0a9d4
WH		 912 smbios_tables, smbios_tables_len);
913 }
914
89cc4a27
WH		 915 /* build the array of physical mem area from e820 table */
916 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
917 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
918 uint64_t addr, len;
919
920 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
921 mem_array[array_count].address = addr;
922 mem_array[array_count].length = len;
923 array_count++;
924 }
925 }
a0628599 926 smbios_get_tables(ms, mem_array, array_count,
89cc4a27 927 &smbios_tables, &smbios_tables_len,
5fd0a9d4 928 &smbios_anchor, &smbios_anchor_len);
89cc4a27
WH		 929 g_free(mem_array);
930
5fd0a9d4 931 if (smbios_anchor) {
f2098f48 932 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
5fd0a9d4 933 smbios_tables, smbios_tables_len);
f2098f48 934 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
5fd0a9d4
WH		 935 smbios_anchor, smbios_anchor_len);
936 }
937}
938
524acbe9 939static FWCfgState *fw_cfg_arch_create(PCMachineState *pcms,
264b4857 940 const CPUArchIdList *cpus,
57e23e78
PMD		 941 uint16_t boot_cpus,
942 uint16_t apic_id_limit)
5fd0a9d4
WH		 943{
944 FWCfgState *fw_cfg;
11c2fd3e 945 uint64_t *numa_fw_cfg;
ea265072 946 int i;
aa570207
TX		 947 MachineState *ms = MACHINE(pcms);
948 int nb_numa_nodes = ms->numa_state->num_nodes;
3cce6243 949
0f432b30
PMD		 950 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
951 &address_space_memory);
524acbe9 952 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
c886fc4c 953
1d934e89
EH		 954 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
955 *
a3abd0f2
IM		 956 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
957 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
958 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
959 * for CPU hotplug also uses APIC ID and not "CPU index".
960 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
961 * but the "limit to the APIC ID values SeaBIOS may see".
1d934e89 962 *
a3abd0f2
IM		 963 * So for compatibility reasons with old BIOSes we are stuck with
964 * "etc/max-cpus" actually being apic_id_limit
1d934e89 965 */
264b4857 966 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
905fdcb5 967 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
089da572
MA		 968 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
969 acpi_tables, acpi_tables_len);
9b5b76d4 970 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
b6f6e3d3 971
089da572 972 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
7d67110f
GH		 973 &e820_reserve, sizeof(e820_reserve));
974 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
42d400ac 975 sizeof(struct e820_entry) * e820_get_num_entries());
11c2fd3e 976
089da572 977 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
11c2fd3e
AL		 978 /* allocate memory for the NUMA channel: one (64bit) word for the number
979 * of nodes, one word for each VCPU->node and one word for each node to
980 * hold the amount of memory.
981 */
264b4857 982 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
11c2fd3e 983 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
ea265072
IM		 984 for (i = 0; i < cpus->len; i++) {
985 unsigned int apic_id = cpus->cpus[i].arch_id;
264b4857 986 assert(apic_id < apic_id_limit);
d41f3e75 987 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
11c2fd3e
AL		 988 }
989 for (i = 0; i < nb_numa_nodes; i++) {
264b4857 990 numa_fw_cfg[apic_id_limit + 1 + i] =
7e721e7b 991 cpu_to_le64(ms->numa_state->nodes[i].node_mem);
11c2fd3e 992 }
089da572 993 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
264b4857 994 (1 + apic_id_limit + nb_numa_nodes) *
1d934e89 995 sizeof(*numa_fw_cfg));
bf483392
AG		 996
997 return fw_cfg;
80cabfad
FB		 998}
999
642a4f96
TS		 1000static long get_file_size(FILE *f)
1001{
1002 long where, size;
1003
1004 /* XXX: on Unix systems, using fstat() probably makes more sense */
1005
1006 where = ftell(f);
1007 fseek(f, 0, SEEK_END);
1008 size = ftell(f);
1009 fseek(f, where, SEEK_SET);
1010
1011 return size;
1012}
1013
3cbeb524
AB		 1014struct setup_data {
1015 uint64_t next;
1016 uint32_t type;
1017 uint32_t len;
1018 uint8_t data[0];
1019} __attribute__((packed));
1020
ab969087
LM		 1021
1022/*
1023 * The entry point into the kernel for PVH boot is different from
1024 * the native entry point. The PVH entry is defined by the x86/HVM
1025 * direct boot ABI and is available in an ELFNOTE in the kernel binary.
1026 *
1027 * This function is passed to load_elf() when it is called from
1028 * load_elfboot() which then additionally checks for an ELF Note of
1029 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to
1030 * parse the PVH entry address from the ELF Note.
1031 *
1032 * Due to trickery in elf_opts.h, load_elf() is actually available as
1033 * load_elf32() or load_elf64() and this routine needs to be able
1034 * to deal with being called as 32 or 64 bit.
1035 *
1036 * The address of the PVH entry point is saved to the 'pvh_start_addr'
1037 * global variable. (although the entry point is 32-bit, the kernel
1038 * binary can be either 32-bit or 64-bit).
1039 */
1040static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64)
1041{
1042 size_t *elf_note_data_addr;
1043
1044 /* Check if ELF Note header passed in is valid */
1045 if (arg1 == NULL) {
1046 return 0;
1047 }
1048
1049 if (is64) {
1050 struct elf64_note *nhdr64 = (struct elf64_note *)arg1;
1051 uint64_t nhdr_size64 = sizeof(struct elf64_note);
1052 uint64_t phdr_align = *(uint64_t *)arg2;
1053 uint64_t nhdr_namesz = nhdr64->n_namesz;
1054
1055 elf_note_data_addr =
1056 ((void *)nhdr64) + nhdr_size64 +
1057 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1058 } else {
1059 struct elf32_note *nhdr32 = (struct elf32_note *)arg1;
1060 uint32_t nhdr_size32 = sizeof(struct elf32_note);
1061 uint32_t phdr_align = *(uint32_t *)arg2;
1062 uint32_t nhdr_namesz = nhdr32->n_namesz;
1063
1064 elf_note_data_addr =
1065 ((void *)nhdr32) + nhdr_size32 +
1066 QEMU_ALIGN_UP(nhdr_namesz, phdr_align);
1067 }
1068
1069 pvh_start_addr = *elf_note_data_addr;
1070
1071 return pvh_start_addr;
1072}
1073
1074static bool load_elfboot(const char *kernel_filename,
1075 int kernel_file_size,
1076 uint8_t *header,
1077 size_t pvh_xen_start_addr,
1078 FWCfgState *fw_cfg)
1079{
1080 uint32_t flags = 0;
1081 uint32_t mh_load_addr = 0;
1082 uint32_t elf_kernel_size = 0;
1083 uint64_t elf_entry;
1084 uint64_t elf_low, elf_high;
1085 int kernel_size;
1086
1087 if (ldl_p(header) != 0x464c457f) {
1088 return false; /* no elfboot */
1089 }
1090
1091 bool elf_is64 = header[EI_CLASS] == ELFCLASS64;
1092 flags = elf_is64 ?
1093 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags;
1094
1095 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */
1096 error_report("elfboot unsupported flags = %x", flags);
1097 exit(1);
1098 }
1099
1100 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY;
1101 kernel_size = load_elf(kernel_filename, read_pvh_start_addr,
1102 NULL, &elf_note_type, &elf_entry,
1103 &elf_low, &elf_high, 0, I386_ELF_MACHINE,
1104 0, 0);
1105
1106 if (kernel_size < 0) {
1107 error_report("Error while loading elf kernel");
1108 exit(1);
1109 }
1110 mh_load_addr = elf_low;
1111 elf_kernel_size = elf_high - elf_low;
1112
1113 if (pvh_start_addr == 0) {
1114 error_report("Error loading uncompressed kernel without PVH ELF Note");
1115 exit(1);
1116 }
1117 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr);
1118 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr);
1119 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size);
1120
1121 return true;
1122}
1123
df1f79fd
EH		 1124static void load_linux(PCMachineState *pcms,
1125 FWCfgState *fw_cfg)
642a4f96
TS		 1126{
1127 uint16_t protocol;
f3839fda 1128 int setup_size, kernel_size, cmdline_size;
3cbeb524 1129 int dtb_size, setup_data_offset;
642a4f96 1130 uint32_t initrd_max;
c24323dd 1131 uint8_t header[8192], *setup, *kernel;
a8170e5e 1132 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 1133 FILE *f;
bf4e5d92 1134 char *vmode;
df1f79fd 1135 MachineState *machine = MACHINE(pcms);
cd4040ec 1136 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3cbeb524 1137 struct setup_data *setup_data;
df1f79fd
EH		 1138 const char *kernel_filename = machine->kernel_filename;
1139 const char *initrd_filename = machine->initrd_filename;
3cbeb524 1140 const char *dtb_filename = machine->dtb;
df1f79fd 1141 const char *kernel_cmdline = machine->kernel_cmdline;
642a4f96
TS		 1142
1143 /* Align to 16 bytes as a paranoia measure */
1144 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1145
1146 /* load the kernel header */
1147 f = fopen(kernel_filename, "rb");
1148 if (!f || !(kernel_size = get_file_size(f)) ||
0f9d76e5
LG		 1149 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1150 MIN(ARRAY_SIZE(header), kernel_size)) {
1151 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1152 kernel_filename, strerror(errno));
1153 exit(1);
642a4f96
TS		 1154 }
1155
1156 /* kernel protocol version */
bc4edd79 1157#if 0
642a4f96 1158 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 1159#endif
0f9d76e5
LG		 1160 if (ldl_p(header+0x202) == 0x53726448) {
1161 protocol = lduw_p(header+0x206);
1162 } else {
5dc8ab36
SG		 1163 /*
1164 * This could be a multiboot kernel. If it is, let's stop treating it
1165 * like a Linux kernel.
1166 * Note: some multiboot images could be in the ELF format (the same of
1167 * PVH), so we try multiboot first since we check the multiboot magic
1168 * header before to load it.
1169 */
1170 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
1171 kernel_cmdline, kernel_size, header)) {
1172 return;
1173 }
ab969087
LM		 1174 /*
1175 * Check if the file is an uncompressed kernel file (ELF) and load it,
1176 * saving the PVH entry point used by the x86/HVM direct boot ABI.
1177 * If load_elfboot() is successful, populate the fw_cfg info.
1178 */
fda672b5
SG		 1179 if (pcmc->pvh_enabled &&
1180 load_elfboot(kernel_filename, kernel_size,
ab969087 1181 header, pvh_start_addr, fw_cfg)) {
ab969087
LM		 1182 fclose(f);
1183
1184 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1185 strlen(kernel_cmdline) + 1);
1186 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1187
ab969087
LM		 1188 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header));
1189 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA,
1190 header, sizeof(header));
1191
c5bf7847
SG		 1192 /* load initrd */
1193 if (initrd_filename) {
e502fe96 1194 GMappedFile *mapped_file;
c5bf7847
SG		 1195 gsize initrd_size;
1196 gchar *initrd_data;
1197 GError *gerr = NULL;
1198
e502fe96
SG		 1199 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1200 if (!mapped_file) {
c5bf7847
SG		 1201 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
1202 initrd_filename, gerr->message);
1203 exit(1);
1204 }
e502fe96 1205 pcms->initrd_mapped_file = mapped_file;
c5bf7847 1206
e502fe96
SG		 1207 initrd_data = g_mapped_file_get_contents(mapped_file);
1208 initrd_size = g_mapped_file_get_length(mapped_file);
c5bf7847
SG		 1209 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
1210 if (initrd_size >= initrd_max) {
1211 fprintf(stderr, "qemu: initrd is too large, cannot support."
1212 "(max: %"PRIu32", need %"PRId64")\n",
1213 initrd_max, (uint64_t)initrd_size);
1214 exit(1);
1215 }
1216
1217 initrd_addr = (initrd_max - initrd_size) & ~4095;
1218
1219 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1220 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1221 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data,
1222 initrd_size);
1223 }
1224
1fb0d709
SG		 1225 option_rom[nb_option_roms].bootindex = 0;
1226 option_rom[nb_option_roms].name = "pvh.bin";
1227 nb_option_roms++;
1228
ab969087
LM		 1229 return;
1230 }
0f9d76e5 1231 protocol = 0;
f16408df 1232 }
642a4f96
TS		 1233
1234 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
0f9d76e5
LG		 1235 /* Low kernel */
1236 real_addr = 0x90000;
1237 cmdline_addr = 0x9a000 - cmdline_size;
1238 prot_addr = 0x10000;
642a4f96 1239 } else if (protocol < 0x202) {
0f9d76e5
LG		 1240 /* High but ancient kernel */
1241 real_addr = 0x90000;
1242 cmdline_addr = 0x9a000 - cmdline_size;
1243 prot_addr = 0x100000;
642a4f96 1244 } else {
0f9d76e5
LG		 1245 /* High and recent kernel */
1246 real_addr = 0x10000;
1247 cmdline_addr = 0x20000;
1248 prot_addr = 0x100000;
642a4f96
TS		 1249 }
1250
bc4edd79 1251#if 0
642a4f96 1252 fprintf(stderr,
0f9d76e5
LG		 1253 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1254 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1255 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1256 real_addr,
1257 cmdline_addr,
1258 prot_addr);
bc4edd79 1259#endif
642a4f96
TS		 1260
1261 /* highest address for loading the initrd */
aab50e53
LZ		 1262 if (protocol >= 0x20c &&
1263 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) {
1264 /*
1265 * Linux has supported initrd up to 4 GB for a very long time (2007,
1266 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013),
1267 * though it only sets initrd_max to 2 GB to "work around bootloader
1268 * bugs". Luckily, QEMU firmware(which does something like bootloader)
1269 * has supported this.
1270 *
1271 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can
1272 * be loaded into any address.
1273 *
1274 * In addition, initrd_max is uint32_t simply because QEMU doesn't
1275 * support the 64-bit boot protocol (specifically the ext_ramdisk_image
1276 * field).
1277 *
1278 * Therefore here just limit initrd_max to UINT32_MAX simply as well.
1279 */
1280 initrd_max = UINT32_MAX;
1281 } else if (protocol >= 0x203) {
0f9d76e5
LG		 1282 initrd_max = ldl_p(header+0x22c);
1283 } else {
1284 initrd_max = 0x37ffffff;
1285 }
642a4f96 1286
cd4040ec
EH		 1287 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1288 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
927766c7 1289 }
642a4f96 1290
57a46d05
AG		 1291 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1292 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
96f80586 1293 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
642a4f96
TS		 1294
1295 if (protocol >= 0x202) {
0f9d76e5 1296 stl_p(header+0x228, cmdline_addr);
642a4f96 1297 } else {
0f9d76e5
LG		 1298 stw_p(header+0x20, 0xA33F);
1299 stw_p(header+0x22, cmdline_addr-real_addr);
642a4f96
TS		 1300 }
1301
bf4e5d92
PT		 1302 /* handle vga= parameter */
1303 vmode = strstr(kernel_cmdline, "vga=");
1304 if (vmode) {
1305 unsigned int video_mode;
1306 /* skip "vga=" */
1307 vmode += 4;
1308 if (!strncmp(vmode, "normal", 6)) {
1309 video_mode = 0xffff;
1310 } else if (!strncmp(vmode, "ext", 3)) {
1311 video_mode = 0xfffe;
1312 } else if (!strncmp(vmode, "ask", 3)) {
1313 video_mode = 0xfffd;
1314 } else {
1315 video_mode = strtol(vmode, NULL, 0);
1316 }
1317 stw_p(header+0x1fa, video_mode);
1318 }
1319
642a4f96 1320 /* loader type */
5cbdb3a3 1321 /* High nybble = B reserved for QEMU; low nybble is revision number.
642a4f96
TS		 1322 If this code is substantially changed, you may want to consider
1323 incrementing the revision. */
0f9d76e5
LG		 1324 if (protocol >= 0x200) {
1325 header[0x210] = 0xB0;
1326 }
642a4f96
TS		 1327 /* heap */
1328 if (protocol >= 0x201) {
0f9d76e5
LG		 1329 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1330 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
642a4f96
TS		 1331 }
1332
1333 /* load initrd */
1334 if (initrd_filename) {
e502fe96 1335 GMappedFile *mapped_file;
c24323dd
PM		 1336 gsize initrd_size;
1337 gchar *initrd_data;
1338 GError *gerr = NULL;
1339
0f9d76e5
LG		 1340 if (protocol < 0x200) {
1341 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1342 exit(1);
1343 }
642a4f96 1344
e502fe96
SG		 1345 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr);
1346 if (!mapped_file) {
7454e51d 1347 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
c24323dd 1348 initrd_filename, gerr->message);
d6fa4b77 1349 exit(1);
c24323dd 1350 }
e502fe96
SG		 1351 pcms->initrd_mapped_file = mapped_file;
1352
1353 initrd_data = g_mapped_file_get_contents(mapped_file);
1354 initrd_size = g_mapped_file_get_length(mapped_file);
c24323dd 1355 if (initrd_size >= initrd_max) {
f3839fda 1356 fprintf(stderr, "qemu: initrd is too large, cannot support."
c24323dd
PM		 1357 "(max: %"PRIu32", need %"PRId64")\n",
1358 initrd_max, (uint64_t)initrd_size);
f3839fda 1359 exit(1);
d6fa4b77
MK		 1360 }
1361
45a50b16 1362 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05 1363
57a46d05
AG		 1364 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1365 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1366 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 1367
0f9d76e5
LG		 1368 stl_p(header+0x218, initrd_addr);
1369 stl_p(header+0x21c, initrd_size);
642a4f96
TS		 1370 }
1371
45a50b16 1372 /* load kernel and setup */
642a4f96 1373 setup_size = header[0x1f1];
0f9d76e5
LG		 1374 if (setup_size == 0) {
1375 setup_size = 4;
1376 }
642a4f96 1377 setup_size = (setup_size+1)*512;
ec5fd402
PB		 1378 if (setup_size > kernel_size) {
1379 fprintf(stderr, "qemu: invalid kernel header\n");
1380 exit(1);
1381 }
45a50b16 1382 kernel_size -= setup_size;
642a4f96 1383
7267c094
AL		 1384 setup = g_malloc(setup_size);
1385 kernel = g_malloc(kernel_size);
45a50b16 1386 fseek(f, 0, SEEK_SET);
5a41ecc5
KS		 1387 if (fread(setup, 1, setup_size, f) != setup_size) {
1388 fprintf(stderr, "fread() failed\n");
1389 exit(1);
1390 }
1391 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1392 fprintf(stderr, "fread() failed\n");
1393 exit(1);
1394 }
642a4f96 1395 fclose(f);
3cbeb524
AB		 1396
1397 /* append dtb to kernel */
1398 if (dtb_filename) {
1399 if (protocol < 0x209) {
1400 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1401 exit(1);
1402 }
1403
1404 dtb_size = get_image_size(dtb_filename);
1405 if (dtb_size <= 0) {
1406 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1407 dtb_filename, strerror(errno));
1408 exit(1);
1409 }
1410
1411 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1412 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1413 kernel = g_realloc(kernel, kernel_size);
1414
1415 stq_p(header+0x250, prot_addr + setup_data_offset);
1416
1417 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1418 setup_data->next = 0;
1419 setup_data->type = cpu_to_le32(SETUP_DTB);
1420 setup_data->len = cpu_to_le32(dtb_size);
1421
1422 load_image_size(dtb_filename, setup_data->data, dtb_size);
1423 }
1424
45a50b16 1425 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG		 1426
1427 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1428 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1429 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1430
1431 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1432 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1433 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1434
98e753a6
IM		 1435 option_rom[nb_option_roms].bootindex = 0;
1436 option_rom[nb_option_roms].name = "linuxboot.bin";
1437 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
b2a575a1 1438 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
b2a575a1 1439 }
57a46d05 1440 nb_option_roms++;
642a4f96
TS		 1441}
1442
b41a2cd1
FB		 1443#define NE2000_NB_MAX 6
1444
675d6f82
BS		 1445static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1446 0x280, 0x380 };
1447static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 1448
48a18b3c 1449void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 1450{
1451 static int nb_ne2k = 0;
1452
1453 if (nb_ne2k == NE2000_NB_MAX)
1454 return;
48a18b3c 1455 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 1456 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 1457 nb_ne2k++;
1458}
1459
92a16d7a 1460DeviceState *cpu_get_current_apic(void)
0e26b7b8 1461{
4917cf44
AF		 1462 if (current_cpu) {
1463 X86CPU *cpu = X86_CPU(current_cpu);
02e51483 1464 return cpu->apic_state;
0e26b7b8
BS		 1465 } else {
1466 return NULL;
1467 }
1468}
1469
845773ab 1470void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 1471{
c3affe56 1472 X86CPU *cpu = opaque;
53b67b30
BS		 1473
1474 if (level) {
c3affe56 1475 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 1476 }
1477}
1478
cabea7dc 1479static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp)
31050930 1480{
074281d6 1481 Object *cpu = NULL;
31050930 1482 Error *local_err = NULL;
cabea7dc 1483 CPUX86State *env = NULL;
31050930 1484
cabea7dc
LX		 1485 cpu = object_new(MACHINE(pcms)->cpu_type);
1486
1487 env = &X86_CPU(cpu)->env;
1488 env->nr_dies = pcms->smp_dies;
31050930 1489
c7b4efb4 1490 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
074281d6 1491 object_property_set_bool(cpu, true, "realized", &local_err);
31050930 1492
074281d6 1493 object_unref(cpu);
021c9d25 1494 error_propagate(errp, local_err);
31050930
IM		 1495}
1496
6f479566
LX		 1497/*
1498 * This function is very similar to smp_parse()
1499 * in hw/core/machine.c but includes CPU die support.
1500 */
1501void pc_smp_parse(MachineState *ms, QemuOpts *opts)
1502{
1b458422
LX		 1503 PCMachineState *pcms = PC_MACHINE(ms);
1504
6f479566
LX		 1505 if (opts) {
1506 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
1507 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
1b458422 1508 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
6f479566
LX		 1509 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
1510 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
1511
1512 /* compute missing values, prefer sockets over cores over threads */
1513 if (cpus == 0 || sockets == 0) {
1514 cores = cores > 0 ? cores : 1;
1515 threads = threads > 0 ? threads : 1;
1516 if (cpus == 0) {
1517 sockets = sockets > 0 ? sockets : 1;
1b458422 1518 cpus = cores * threads * dies * sockets;
6f479566
LX		 1519 } else {
1520 ms->smp.max_cpus =
1521 qemu_opt_get_number(opts, "maxcpus", cpus);
1b458422 1522 sockets = ms->smp.max_cpus / (cores * threads * dies);
6f479566
LX		 1523 }
1524 } else if (cores == 0) {
1525 threads = threads > 0 ? threads : 1;
1b458422 1526 cores = cpus / (sockets * dies * threads);
6f479566
LX		 1527 cores = cores > 0 ? cores : 1;
1528 } else if (threads == 0) {
1b458422 1529 threads = cpus / (cores * dies * sockets);
6f479566 1530 threads = threads > 0 ? threads : 1;
1b458422 1531 } else if (sockets * dies * cores * threads < cpus) {
6f479566 1532 error_report("cpu topology: "
1b458422 1533 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
6f479566 1534 "smp_cpus (%u)",
1b458422 1535 sockets, dies, cores, threads, cpus);
6f479566
LX		 1536 exit(1);
1537 }
1538
1539 ms->smp.max_cpus =
1540 qemu_opt_get_number(opts, "maxcpus", cpus);
1541
1542 if (ms->smp.max_cpus < cpus) {
1543 error_report("maxcpus must be equal to or greater than smp");
1544 exit(1);
1545 }
1546
1b458422 1547 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
6f479566 1548 error_report("cpu topology: "
1b458422 1549 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
6f479566 1550 "maxcpus (%u)",
1b458422 1551 sockets, dies, cores, threads,
6f479566
LX		 1552 ms->smp.max_cpus);
1553 exit(1);
1554 }
1555
1b458422 1556 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
6f479566 1557 warn_report("Invalid CPU topology deprecated: "
1b458422 1558 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
6f479566 1559 "!= maxcpus (%u)",
1b458422 1560 sockets, dies, cores, threads,
6f479566
LX		 1561 ms->smp.max_cpus);
1562 }
1563
1564 ms->smp.cpus = cpus;
1565 ms->smp.cores = cores;
1566 ms->smp.threads = threads;
1b458422 1567 pcms->smp_dies = dies;
6f479566
LX		 1568 }
1569
1570 if (ms->smp.cpus > 1) {
1571 Error *blocker = NULL;
1572 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
1573 replay_add_blocker(blocker);
1574 }
1575}
1576
a0628599 1577void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
c649983b 1578{
457cfccc
EH		 1579 PCMachineState *pcms = PC_MACHINE(ms);
1580 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id);
0e3bd562 1581 Error *local_err = NULL;
c649983b 1582
8de433cb
IM		 1583 if (id < 0) {
1584 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1585 return;
1586 }
1587
5ff020b7
EH		 1588 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1589 error_setg(errp, "Unable to add CPU: %" PRIi64
1590 ", resulting APIC ID (%" PRIi64 ") is too large",
1591 id, apic_id);
1592 return;
1593 }
1594
cabea7dc 1595 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err);
0e3bd562
AF		 1596 if (local_err) {
1597 error_propagate(errp, local_err);
1598 return;
1599 }
c649983b
IM		 1600}
1601
4884b7bf 1602void pc_cpus_init(PCMachineState *pcms)
70166477
IY		 1603{
1604 int i;
c96a1c0b 1605 const CPUArchIdList *possible_cpus;
311ca98d 1606 MachineState *ms = MACHINE(pcms);
c96a1c0b 1607 MachineClass *mc = MACHINE_GET_CLASS(pcms);
0788a56b
EH		 1608 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
1609
1610 x86_cpu_set_default_version(pcmc->default_cpu_version);
70166477 1611
ebde2465
IM		 1612 /* Calculates the limit to CPU APIC ID values
1613 *
1614 * Limit for the APIC ID value, so that all
1615 * CPU APIC IDs are < pcms->apic_id_limit.
1616 *
5888e01c 1617 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create().
ebde2465 1618 */
0e11fc69
LX		 1619 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms,
1620 ms->smp.max_cpus - 1) + 1;
311ca98d 1621 possible_cpus = mc->possible_cpu_arch_ids(ms);
0e11fc69 1622 for (i = 0; i < ms->smp.cpus; i++) {
cabea7dc 1623 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal);
70166477
IY		 1624 }
1625}
1626
217f1b4a
HZ		 1627static void pc_build_feature_control_file(PCMachineState *pcms)
1628{
38690a1c
IM		 1629 MachineState *ms = MACHINE(pcms);
1630 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
217f1b4a
HZ		 1631 CPUX86State *env = &cpu->env;
1632 uint32_t unused, ecx, edx;
1633 uint64_t feature_control_bits = 0;
1634 uint64_t *val;
1635
1636 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1637 if (ecx & CPUID_EXT_VMX) {
1638 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1639 }
1640
1641 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1642 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1643 (env->mcg_cap & MCG_LMCE_P)) {
1644 feature_control_bits |= FEATURE_CONTROL_LMCE;
1645 }
1646
1647 if (!feature_control_bits) {
1648 return;
1649 }
1650
1651 val = g_malloc(sizeof(*val));
1652 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1653 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1654}
1655
e3cadac0
IM		 1656static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1657{
1658 if (cpus_count > 0xff) {
1659 /* If the number of CPUs can't be represented in 8 bits, the
1660 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1661 * to make old BIOSes fail more predictably.
1662 */
1663 rtc_set_memory(rtc, 0x5f, 0);
1664 } else {
1665 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1666 }
1667}
1668
3459a625 1669static
9ebeed0c 1670void pc_machine_done(Notifier *notifier, void *data)
3459a625 1671{
9ebeed0c
EH		 1672 PCMachineState *pcms = container_of(notifier,
1673 PCMachineState, machine_done);
1674 PCIBus *bus = pcms->bus;
2118196b 1675
ba157b69 1676 /* set the number of CPUs */
e3cadac0 1677 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
ba157b69 1678
2118196b
MA		 1679 if (bus) {
1680 int extra_hosts = 0;
1681
1682 QLIST_FOREACH(bus, &bus->child, sibling) {
1683 /* look for expander root buses */
1684 if (pci_bus_is_root(bus)) {
1685 extra_hosts++;
1686 }
1687 }
f264d360 1688 if (extra_hosts && pcms->fw_cfg) {
2118196b
MA		 1689 uint64_t *val = g_malloc(sizeof(*val));
1690 *val = cpu_to_le64(extra_hosts);
f264d360 1691 fw_cfg_add_file(pcms->fw_cfg,
2118196b
MA		 1692 "etc/extra-pci-roots", val, sizeof(*val));
1693 }
1694 }
1695
bb292f5a 1696 acpi_setup();
6d42eefa 1697 if (pcms->fw_cfg) {
f2098f48 1698 pc_build_smbios(pcms);
217f1b4a 1699 pc_build_feature_control_file(pcms);
e3cadac0
IM		 1700 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1701 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
6d42eefa 1702 }
60c5e104 1703
1a26f466 1704 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
60c5e104
IM		 1705 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1706
a924b3d8 1707 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
60c5e104
IM		 1708 iommu->intr_eim != ON_OFF_AUTO_ON) {
1709 error_report("current -smp configuration requires "
1710 "Extended Interrupt Mode enabled. "
1711 "You can add an IOMMU using: "
1712 "-device intel-iommu,intremap=on,eim=on");
1713 exit(EXIT_FAILURE);
1714 }
1715 }
3459a625
MT		 1716}
1717
e4e8ba04 1718void pc_guest_info_init(PCMachineState *pcms)
3459a625 1719{
1f3aba37 1720 int i;
aa570207 1721 MachineState *ms = MACHINE(pcms);
b20c9bd5 1722
dd4c2f01 1723 pcms->apic_xrupt_override = kvm_allows_irq0_override();
aa570207 1724 pcms->numa_nodes = ms->numa_state->num_nodes;
dd4c2f01
EH		 1725 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1726 sizeof *pcms->node_mem);
aa570207 1727 for (i = 0; i < ms->numa_state->num_nodes; i++) {
7e721e7b 1728 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
8c85901e
WG		 1729 }
1730
9ebeed0c
EH		 1731 pcms->machine_done.notify = pc_machine_done;
1732 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 1733}
1734
83d08f26
MT		 1735/* setup pci memory address space mapping into system address space */
1736void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1737 MemoryRegion *pci_address_space)
39848901 1738{
83d08f26
MT		 1739 /* Set to lower priority than RAM */
1740 memory_region_add_subregion_overlap(system_memory, 0x0,
1741 pci_address_space, -1);
39848901
IM		 1742}
1743
7bc35e0f 1744void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 1745{
1746 int i;
1747 FWCfgState *fw_cfg;
1748
df1f79fd 1749 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 1750
305ae888 1751 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
e3cadac0 1752 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
b33a5bbf
CL		 1753 rom_set_fw(fw_cfg);
1754
df1f79fd 1755 load_linux(pcms, fw_cfg);
b33a5bbf
CL		 1756 for (i = 0; i < nb_option_roms; i++) {
1757 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 1758 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
1fb0d709 1759 !strcmp(option_rom[i].name, "pvh.bin") ||
b33a5bbf
CL		 1760 !strcmp(option_rom[i].name, "multiboot.bin"));
1761 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1762 }
f264d360 1763 pcms->fw_cfg = fw_cfg;
b33a5bbf
CL		 1764}
1765
5934e216
EH		 1766void pc_memory_init(PCMachineState *pcms,
1767 MemoryRegion *system_memory,
1768 MemoryRegion *rom_memory,
1769 MemoryRegion **ram_memory)
80cabfad 1770{
cbc5b5f3
JJ		 1771 int linux_boot, i;
1772 MemoryRegion *ram, *option_rom_mr;
00cb2a99 1773 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 1774 FWCfgState *fw_cfg;
62b160c0 1775 MachineState *machine = MACHINE(pcms);
264b4857 1776 MachineClass *mc = MACHINE_GET_CLASS(machine);
16a9e8a5 1777 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d592d303 1778
c8d163bc
EH		 1779 assert(machine->ram_size == pcms->below_4g_mem_size +
1780 pcms->above_4g_mem_size);
9521d42b
PB		 1781
1782 linux_boot = (machine->kernel_filename != NULL);
80cabfad 1783
00cb2a99 1784 /* Allocate RAM. We allocate it as a single memory region and use
66a0a2cb 1785 * aliases to address portions of it, mostly for backwards compatibility
00cb2a99
AK		 1786 * with older qemus that used qemu_ram_alloc().
1787 */
7267c094 1788 ram = g_malloc(sizeof(*ram));
9521d42b
PB		 1789 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
1790 machine->ram_size);
ae0a5466 1791 *ram_memory = ram;
7267c094 1792 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
2c9b15ca 1793 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
c8d163bc 1794 0, pcms->below_4g_mem_size);
00cb2a99 1795 memory_region_add_subregion(system_memory, 0, ram_below_4g);
c8d163bc
EH		 1796 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
1797 if (pcms->above_4g_mem_size > 0) {
7267c094 1798 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
2c9b15ca 1799 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
c8d163bc
EH		 1800 pcms->below_4g_mem_size,
1801 pcms->above_4g_mem_size);
00cb2a99
AK		 1802 memory_region_add_subregion(system_memory, 0x100000000ULL,
1803 ram_above_4g);
c8d163bc 1804 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
bbe80adf 1805 }
82b36dc3 1806
bb292f5a 1807 if (!pcmc->has_reserved_memory &&
ca8336f3 1808 (machine->ram_slots ||
9521d42b 1809 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 1810
1811 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1812 mc->name);
1813 exit(EXIT_FAILURE);
1814 }
1815
b0c14ec4
DH		 1816 /* always allocate the device memory information */
1817 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1818
f2ffbe2b 1819 /* initialize device memory address space */
bb292f5a 1820 if (pcmc->has_reserved_memory &&
9521d42b 1821 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 1822 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 1823
a0cc8856
IM		 1824 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1825 error_report("unsupported amount of memory slots: %"PRIu64,
1826 machine->ram_slots);
1827 exit(EXIT_FAILURE);
1828 }
1829
f2c38522
PK		 1830 if (QEMU_ALIGN_UP(machine->maxram_size,
1831 TARGET_PAGE_SIZE) != machine->maxram_size) {
1832 error_report("maximum memory size must by aligned to multiple of "
1833 "%d bytes", TARGET_PAGE_SIZE);
1834 exit(EXIT_FAILURE);
1835 }
1836
b0c14ec4 1837 machine->device_memory->base =
d471bf3e 1838 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
619d11e4 1839
16a9e8a5 1840 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 1841 /* size device region assuming 1G page max alignment per slot */
d471bf3e 1842 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 1843 }
1844
f2ffbe2b
DH		 1845 if ((machine->device_memory->base + device_mem_size) <
1846 device_mem_size) {
619d11e4
IM		 1847 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1848 machine->maxram_size);
1849 exit(EXIT_FAILURE);
1850 }
1851
b0c14ec4 1852 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 1853 "device-memory", device_mem_size);
b0c14ec4
DH		 1854 memory_region_add_subregion(system_memory, machine->device_memory->base,
1855 &machine->device_memory->mr);
619d11e4 1856 }
cbc5b5f3
JJ		 1857
1858 /* Initialize PC system firmware */
5e640a9e 1859 pc_system_firmware_init(pcms, rom_memory);
00cb2a99 1860
7267c094 1861 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 1862 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 1863 &error_fatal);
208fa0e4
IM		 1864 if (pcmc->pci_enabled) {
1865 memory_region_set_readonly(option_rom_mr, true);
1866 }
4463aee6 1867 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 1868 PC_ROM_MIN_VGA,
1869 option_rom_mr,
1870 1);
f753ff16 1871
264b4857
PMD		 1872 fw_cfg = fw_cfg_arch_create(pcms, mc->possible_cpu_arch_ids(machine),
1873 pcms->boot_cpus, pcms->apic_id_limit);
c886fc4c 1874
8832cb80 1875 rom_set_fw(fw_cfg);
1d108d97 1876
b0c14ec4 1877 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 1878 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 1879 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1880 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 1881
1882 if (!pcmc->broken_reserved_end) {
b0c14ec4 1883 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 1884 }
d471bf3e 1885 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 1886 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1887 }
1888
f753ff16 1889 if (linux_boot) {
df1f79fd 1890 load_linux(pcms, fw_cfg);
f753ff16
PB		 1891 }
1892
1893 for (i = 0; i < nb_option_roms; i++) {
2e55e842 1894 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 1895 }
f264d360 1896 pcms->fw_cfg = fw_cfg;
cb135f59
PX		 1897
1898 /* Init default IOAPIC address space */
1899 pcms->ioapic_as = &address_space_memory;
3d53f5c3
IY		 1900}
1901
9fa99d25
MA		 1902/*
1903 * The 64bit pci hole starts after "above 4G RAM" and
1904 * potentially the space reserved for memory hotplug.
1905 */
1906uint64_t pc_pci_hole64_start(void)
1907{
1908 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1909 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 1910 MachineState *ms = MACHINE(pcms);
9fa99d25
MA		 1911 uint64_t hole64_start = 0;
1912
b0c14ec4
DH		 1913 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1914 hole64_start = ms->device_memory->base;
9fa99d25 1915 if (!pcmc->broken_reserved_end) {
b0c14ec4 1916 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25
MA		 1917 }
1918 } else {
1919 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
1920 }
1921
d471bf3e 1922 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 1923}
1924
0b0cc076 1925qemu_irq pc_allocate_cpu_irq(void)
845773ab 1926{
0b0cc076 1927 return qemu_allocate_irq(pic_irq_request, NULL, 0);
845773ab
IY		 1928}
1929
48a18b3c 1930DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 1931{
ad6d45fa
AL		 1932 DeviceState *dev = NULL;
1933
bab47d9a 1934 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 1935 if (pci_bus) {
1936 PCIDevice *pcidev = pci_vga_init(pci_bus);
1937 dev = pcidev ? &pcidev->qdev : NULL;
1938 } else if (isa_bus) {
1939 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 1940 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 1941 }
bab47d9a 1942 rom_reset_order_override();
ad6d45fa 1943 return dev;
765d7908
IY		 1944}
1945
258711c6
JG		 1946static const MemoryRegionOps ioport80_io_ops = {
1947 .write = ioport80_write,
c02e1eac 1948 .read = ioport80_read,
258711c6
JG		 1949 .endianness = DEVICE_NATIVE_ENDIAN,
1950 .impl = {
1951 .min_access_size = 1,
1952 .max_access_size = 1,
1953 },
1954};
1955
1956static const MemoryRegionOps ioportF0_io_ops = {
1957 .write = ioportF0_write,
c02e1eac 1958 .read = ioportF0_read,
258711c6
JG		 1959 .endianness = DEVICE_NATIVE_ENDIAN,
1960 .impl = {
1961 .min_access_size = 1,
1962 .max_access_size = 1,
1963 },
1964};
1965
ac64273c
PMD		 1966static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1967{
1968 int i;
1969 DriveInfo *fd[MAX_FD];
1970 qemu_irq *a20_line;
1971 ISADevice *i8042, *port92, *vmmouse;
1972
def337ff 1973 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 1974 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1975
1976 for (i = 0; i < MAX_FD; i++) {
1977 fd[i] = drive_get(IF_FLOPPY, 0, i);
1978 create_fdctrl |= !!fd[i];
1979 }
1980 if (create_fdctrl) {
1981 fdctrl_init_isa(isa_bus, fd);
1982 }
1983
1984 i8042 = isa_create_simple(isa_bus, "i8042");
1985 if (!no_vmport) {
1986 vmport_init(isa_bus);
1987 vmmouse = isa_try_create(isa_bus, "vmmouse");
1988 } else {
1989 vmmouse = NULL;
1990 }
1991 if (vmmouse) {
1992 DeviceState *dev = DEVICE(vmmouse);
1993 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1994 qdev_init_nofail(dev);
1995 }
1996 port92 = isa_create_simple(isa_bus, "port92");
1997
1998 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1999 i8042_setup_a20_line(i8042, a20_line[0]);
2000 port92_init(port92, a20_line[1]);
2001 g_free(a20_line);
2002}
2003
48a18b3c 2004void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1611977c 2005 ISADevice **rtc_state,
fd53c87c 2006 bool create_fdctrl,
7a10ef51 2007 bool no_vmport,
feddd2fd 2008 bool has_pit,
3a87d009 2009 uint32_t hpet_irqs)
ffe513da
IY		 2010{
2011 int i;
ce967e2f
JK		 2012 DeviceState *hpet = NULL;
2013 int pit_isa_irq = 0;
2014 qemu_irq pit_alt_irq = NULL;
7d932dfd 2015 qemu_irq rtc_irq = NULL;
ac64273c 2016 ISADevice *pit = NULL;
258711c6
JG		 2017 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2018 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
ffe513da 2019
2c9b15ca 2020 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 2021 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 2022
2c9b15ca 2023 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 2024 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 2025
5d17c0d2
JK		 2026 /*
2027 * Check if an HPET shall be created.
2028 *
2029 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2030 * when the HPET wants to take over. Thus we have to disable the latter.
2031 */
2032 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
7a10ef51 2033 /* In order to set property, here not using sysbus_try_create_simple */
51116102 2034 hpet = qdev_try_create(NULL, TYPE_HPET);
dd703b99 2035 if (hpet) {
7a10ef51
LPF		 2036 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2037 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2038 * IRQ8 and IRQ2.
2039 */
5d7fb0f2 2040 uint8_t compat = object_property_get_uint(OBJECT(hpet),
7a10ef51
LPF		 2041 HPET_INTCAP, NULL);
2042 if (!compat) {
2043 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2044 }
2045 qdev_init_nofail(hpet);
2046 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2047
b881fbe9 2048 for (i = 0; i < GSI_NUM_PINS; i++) {
1356b98d 2049 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
dd703b99 2050 }
ce967e2f
JK		 2051 pit_isa_irq = -1;
2052 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2053 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
822557eb 2054 }
ffe513da 2055 }
6c646a11 2056 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 2057
2058 qemu_register_boot_set(pc_boot_set, *rtc_state);
2059
feddd2fd 2060 if (!xen_enabled() && has_pit) {
15eafc2e 2061 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 2062 pit = kvm_pit_init(isa_bus, 0x40);
2063 } else {
acf695ec 2064 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 2065 }
2066 if (hpet) {
2067 /* connect PIT to output control line of the HPET */
4a17cc4f 2068 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311
SS		 2069 }
2070 pcspk_init(isa_bus, pit);
ce967e2f 2071 }
ffe513da 2072
55f613ac 2073 i8257_dma_init(isa_bus, 0);
ffe513da 2074
ac64273c
PMD		 2075 /* Super I/O */
2076 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
ffe513da
IY		 2077}
2078
4b9c264b 2079void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 2080{
2081 int i;
2082
bab47d9a 2083 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 2084 for (i = 0; i < nb_nics; i++) {
2085 NICInfo *nd = &nd_table[i];
4b9c264b 2086 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 2087
4b9c264b 2088 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 2089 pc_init_ne2k_isa(isa_bus, nd);
2090 } else {
4b9c264b 2091 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 2092 }
2093 }
bab47d9a 2094 rom_reset_order_override();
9011a1a7
IY		 2095}
2096
a39e3564
JB		 2097void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2098{
2099 DeviceState *dev;
2100 SysBusDevice *d;
2101 unsigned int i;
2102
15eafc2e 2103 if (kvm_ioapic_in_kernel()) {
34bec7a8 2104 dev = qdev_create(NULL, TYPE_KVM_IOAPIC);
a39e3564 2105 } else {
34bec7a8 2106 dev = qdev_create(NULL, TYPE_IOAPIC);
a39e3564
JB		 2107 }
2108 if (parent_name) {
2109 object_property_add_child(object_resolve_path(parent_name, NULL),
2110 "ioapic", OBJECT(dev), NULL);
2111 }
2112 qdev_init_nofail(dev);
1356b98d 2113 d = SYS_BUS_DEVICE(dev);
3a4a4697 2114 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
a39e3564
JB		 2115
2116 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2117 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2118 }
2119}
d5747cac 2120
d468115b
DH		 2121static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2122 Error **errp)
2123{
2124 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
b0e62443 2125 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
f6a0d06b 2126 const MachineState *ms = MACHINE(hotplug_dev);
d468115b 2127 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 2128 const uint64_t legacy_align = TARGET_PAGE_SIZE;
ae909496 2129 Error *local_err = NULL;
d468115b
DH		 2130
2131 /*
2132 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2133 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2134 * addition to cover this case.
2135 */
2136 if (!pcms->acpi_dev || !acpi_enabled) {
2137 error_setg(errp,
2138 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2139 return;
2140 }
2141
f6a0d06b 2142 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
d468115b
DH		 2143 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2144 return;
2145 }
8f1ffe5b 2146
ae909496
TH		 2147 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
2148 if (local_err) {
2149 error_propagate(errp, local_err);
2150 return;
2151 }
2152
fd3416f5 2153 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 2154 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 2155}
2156
bb6e2f7a
DH		 2157static void pc_memory_plug(HotplugHandler *hotplug_dev,
2158 DeviceState *dev, Error **errp)
95bee274
IM		 2159{
2160 Error *local_err = NULL;
2161 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f6a0d06b 2162 MachineState *ms = MACHINE(hotplug_dev);
7f3cf2d6 2163 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 2164
fd3416f5 2165 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
43bbb49e 2166 if (local_err) {
b8865591
IM		 2167 goto out;
2168 }
2169
7f3cf2d6 2170 if (is_nvdimm) {
f6a0d06b 2171 nvdimm_plug(ms->nvdimms_state);
c7f8d0f3
XG		 2172 }
2173
473ac567 2174 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
95bee274
IM		 2175out:
2176 error_propagate(errp, local_err);
2177}
2178
bb6e2f7a
DH		 2179static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2180 DeviceState *dev, Error **errp)
64fec58e 2181{
64fec58e
TC		 2182 Error *local_err = NULL;
2183 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2184
8cd91ace
HZ		 2185 /*
2186 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2187 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2188 * addition to cover this case.
2189 */
2190 if (!pcms->acpi_dev || !acpi_enabled) {
64fec58e 2191 error_setg(&local_err,
8cd91ace 2192 "memory hotplug is not enabled: missing acpi device or acpi disabled");
64fec58e
TC		 2193 goto out;
2194 }
2195
b097cc52
XG		 2196 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2197 error_setg(&local_err,
2198 "nvdimm device hot unplug is not supported yet.");
2199 goto out;
2200 }
2201
473ac567
DH		 2202 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2203 &local_err);
64fec58e
TC		 2204out:
2205 error_propagate(errp, local_err);
2206}
2207
bb6e2f7a
DH		 2208static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2209 DeviceState *dev, Error **errp)
f7d3e29d
TC		 2210{
2211 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f7d3e29d
TC		 2212 Error *local_err = NULL;
2213
473ac567 2214 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
f7d3e29d
TC		 2215 if (local_err) {
2216 goto out;
2217 }
2218
fd3416f5 2219 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
07578b0a 2220 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
f7d3e29d
TC		 2221 out:
2222 error_propagate(errp, local_err);
2223}
2224
3811ef14
IM		 2225static int pc_apic_cmp(const void *a, const void *b)
2226{
2227 CPUArchId *apic_a = (CPUArchId *)a;
2228 CPUArchId *apic_b = (CPUArchId *)b;
2229
2230 return apic_a->arch_id - apic_b->arch_id;
2231}
2232
7baef5cf 2233/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
38690a1c 2234 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
b12227af 2235 * entry corresponding to CPU's apic_id returns NULL.
7baef5cf 2236 */
1ea69c0e 2237static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
7baef5cf 2238{
7baef5cf
IM		 2239 CPUArchId apic_id, *found_cpu;
2240
1ea69c0e 2241 apic_id.arch_id = id;
38690a1c
IM		 2242 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2243 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
7baef5cf
IM		 2244 pc_apic_cmp);
2245 if (found_cpu && idx) {
38690a1c 2246 *idx = found_cpu - ms->possible_cpus->cpus;
7baef5cf
IM		 2247 }
2248 return found_cpu;
2249}
2250
5279569e
GZ		 2251static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2252 DeviceState *dev, Error **errp)
2253{
7baef5cf 2254 CPUArchId *found_cpu;
5279569e 2255 Error *local_err = NULL;
1ea69c0e 2256 X86CPU *cpu = X86_CPU(dev);
5279569e
GZ		 2257 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2258
a44a49db 2259 if (pcms->acpi_dev) {
473ac567 2260 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
a44a49db
IM		 2261 if (local_err) {
2262 goto out;
2263 }
5279569e
GZ		 2264 }
2265
e3cadac0
IM		 2266 /* increment the number of CPUs */
2267 pcms->boot_cpus++;
26ef65be 2268 if (pcms->rtc) {
e3cadac0 2269 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
26ef65be
IM		 2270 }
2271 if (pcms->fw_cfg) {
e3cadac0 2272 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2d996150
GZ		 2273 }
2274
1ea69c0e 2275 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8aba3842 2276 found_cpu->cpu = OBJECT(dev);
5279569e
GZ		 2277out:
2278 error_propagate(errp, local_err);
2279}
8872c25a
IM		 2280static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2281 DeviceState *dev, Error **errp)
2282{
73360e27 2283 int idx = -1;
8872c25a 2284 Error *local_err = NULL;
1ea69c0e 2285 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2286 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2287
75ba2ddb
IM		 2288 if (!pcms->acpi_dev) {
2289 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2290 goto out;
2291 }
2292
1ea69c0e 2293 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
73360e27
IM		 2294 assert(idx != -1);
2295 if (idx == 0) {
2296 error_setg(&local_err, "Boot CPU is unpluggable");
2297 goto out;
2298 }
2299
473ac567
DH		 2300 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
2301 &local_err);
8872c25a
IM		 2302 if (local_err) {
2303 goto out;
2304 }
2305
2306 out:
2307 error_propagate(errp, local_err);
2308
2309}
2310
2311static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2312 DeviceState *dev, Error **errp)
2313{
8fe6374e 2314 CPUArchId *found_cpu;
8872c25a 2315 Error *local_err = NULL;
1ea69c0e 2316 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2317 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2318
473ac567 2319 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
8872c25a
IM		 2320 if (local_err) {
2321 goto out;
2322 }
2323
1ea69c0e 2324 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8fe6374e 2325 found_cpu->cpu = NULL;
07578b0a 2326 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
8872c25a 2327
e3cadac0
IM		 2328 /* decrement the number of CPUs */
2329 pcms->boot_cpus--;
2330 /* Update the number of CPUs in CMOS */
2331 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2332 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
8872c25a
IM		 2333 out:
2334 error_propagate(errp, local_err);
2335}
5279569e 2336
4ec60c76
IM		 2337static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2338 DeviceState *dev, Error **errp)
2339{
2340 int idx;
a15d2728 2341 CPUState *cs;
e8f7b83e 2342 CPUArchId *cpu_slot;
d89c2b8b 2343 X86CPUTopoInfo topo;
4ec60c76 2344 X86CPU *cpu = X86_CPU(dev);
cabea7dc 2345 CPUX86State *env = &cpu->env;
6970c5ff 2346 MachineState *ms = MACHINE(hotplug_dev);
4ec60c76 2347 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
0e11fc69
LX		 2348 unsigned int smp_cores = ms->smp.cores;
2349 unsigned int smp_threads = ms->smp.threads;
4ec60c76 2350
6970c5ff
IM		 2351 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2352 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2353 ms->cpu_type);
2354 return;
2355 }
2356
cabea7dc
LX		 2357 env->nr_dies = pcms->smp_dies;
2358
c26ae610
LX		 2359 /*
2360 * If APIC ID is not set,
2361 * set it based on socket/die/core/thread properties.
2362 */
e8f7b83e 2363 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
c26ae610
LX		 2364 int max_socket = (ms->smp.max_cpus - 1) /
2365 smp_threads / smp_cores / pcms->smp_dies;
e8f7b83e 2366
fea374e7
EH		 2367 /*
2368 * die-id was optional in QEMU 4.0 and older, so keep it optional
2369 * if there's only one die per socket.
2370 */
2371 if (cpu->die_id < 0 && pcms->smp_dies == 1) {
2372 cpu->die_id = 0;
2373 }
2374
e8f7b83e
IM		 2375 if (cpu->socket_id < 0) {
2376 error_setg(errp, "CPU socket-id is not set");
2377 return;
2378 } else if (cpu->socket_id > max_socket) {
2379 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2380 cpu->socket_id, max_socket);
2381 return;
23d9cff4
EH		 2382 }
2383 if (cpu->die_id < 0) {
2384 error_setg(errp, "CPU die-id is not set");
2385 return;
176d2cda
LX		 2386 } else if (cpu->die_id > pcms->smp_dies - 1) {
2387 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
2a0585e1 2388 cpu->die_id, pcms->smp_dies - 1);
176d2cda 2389 return;
e8f7b83e
IM		 2390 }
2391 if (cpu->core_id < 0) {
2392 error_setg(errp, "CPU core-id is not set");
2393 return;
2394 } else if (cpu->core_id > (smp_cores - 1)) {
2395 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2396 cpu->core_id, smp_cores - 1);
2397 return;
2398 }
2399 if (cpu->thread_id < 0) {
2400 error_setg(errp, "CPU thread-id is not set");
2401 return;
2402 } else if (cpu->thread_id > (smp_threads - 1)) {
2403 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2404 cpu->thread_id, smp_threads - 1);
2405 return;
2406 }
2407
2408 topo.pkg_id = cpu->socket_id;
176d2cda 2409 topo.die_id = cpu->die_id;
e8f7b83e
IM		 2410 topo.core_id = cpu->core_id;
2411 topo.smt_id = cpu->thread_id;
d65af288
LX		 2412 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores,
2413 smp_threads, &topo);
e8f7b83e
IM		 2414 }
2415
1ea69c0e 2416 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
4ec60c76 2417 if (!cpu_slot) {
38690a1c
IM		 2418 MachineState *ms = MACHINE(pcms);
2419
d65af288
LX		 2420 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2421 smp_cores, smp_threads, &topo);
2422 error_setg(errp,
2423 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
2424 " APIC ID %" PRIu32 ", valid index range 0:%d",
2425 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id,
2426 cpu->apic_id, ms->possible_cpus->len - 1);
4ec60c76
IM		 2427 return;
2428 }
2429
2430 if (cpu_slot->cpu) {
2431 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2432 idx, cpu->apic_id);
2433 return;
2434 }
d89c2b8b
IM		 2435
2436 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
c5514d0e 2437 * so that machine_query_hotpluggable_cpus would show correct values
d89c2b8b
IM		 2438 */
2439 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2440 * once -smp refactoring is complete and there will be CPU private
2441 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
d65af288
LX		 2442 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies,
2443 smp_cores, smp_threads, &topo);
d89c2b8b
IM		 2444 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2445 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2446 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2447 return;
2448 }
2449 cpu->socket_id = topo.pkg_id;
2450
176d2cda
LX		 2451 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) {
2452 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
2453 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id);
2454 return;
2455 }
2456 cpu->die_id = topo.die_id;
2457
d89c2b8b
IM		 2458 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2459 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2460 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2461 return;
2462 }
2463 cpu->core_id = topo.core_id;
2464
2465 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2466 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2467 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2468 return;
2469 }
2470 cpu->thread_id = topo.smt_id;
a15d2728 2471
2d384d7c
VK		 2472 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
2473 !kvm_hv_vpindex_settable()) {
e9688fab
RK		 2474 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2475 return;
2476 }
2477
a15d2728
IM		 2478 cs = CPU(cpu);
2479 cs->cpu_index = idx;
93b2a8cb 2480
a0ceb640 2481 numa_cpu_pre_plug(cpu_slot, dev, errp);
4ec60c76
IM		 2482}
2483
a0a49813
DH		 2484static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
2485 DeviceState *dev, Error **errp)
2486{
2487 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2488 Error *local_err = NULL;
2489
2490 if (!hotplug_dev2) {
2491 /*
2492 * Without a bus hotplug handler, we cannot control the plug/unplug
2493 * order. This should never be the case on x86, however better add
2494 * a safety net.
2495 */
2496 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
2497 return;
2498 }
2499 /*
2500 * First, see if we can plug this memory device at all. If that
2501 * succeeds, branch of to the actual hotplug handler.
2502 */
2503 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
2504 &local_err);
2505 if (!local_err) {
2506 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
2507 }
2508 error_propagate(errp, local_err);
2509}
2510
2511static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
2512 DeviceState *dev, Error **errp)
2513{
2514 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
2515 Error *local_err = NULL;
2516
2517 /*
2518 * Plug the memory device first and then branch off to the actual
2519 * hotplug handler. If that one fails, we can easily undo the memory
2520 * device bits.
2521 */
2522 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2523 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
2524 if (local_err) {
2525 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
2526 }
2527 error_propagate(errp, local_err);
2528}
2529
2530static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
2531 DeviceState *dev, Error **errp)
2532{
2533 /* We don't support virtio pmem hot unplug */
2534 error_setg(errp, "virtio pmem device unplug not supported.");
2535}
2536
2537static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
2538 DeviceState *dev, Error **errp)
2539{
2540 /* We don't support virtio pmem hot unplug */
2541}
2542
4ec60c76
IM		 2543static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2544 DeviceState *dev, Error **errp)
2545{
d468115b
DH		 2546 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2547 pc_memory_pre_plug(hotplug_dev, dev, errp);
2548 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
4ec60c76 2549 pc_cpu_pre_plug(hotplug_dev, dev, errp);
a0a49813
DH		 2550 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2551 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
4ec60c76
IM		 2552 }
2553}
2554
95bee274
IM		 2555static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2556 DeviceState *dev, Error **errp)
2557{
2558 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2559 pc_memory_plug(hotplug_dev, dev, errp);
5279569e
GZ		 2560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2561 pc_cpu_plug(hotplug_dev, dev, errp);
a0a49813
DH		 2562 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2563 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
95bee274
IM		 2564 }
2565}
2566
d9c5c5b8
TC		 2567static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2568 DeviceState *dev, Error **errp)
2569{
64fec58e 2570 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2571 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a
IM		 2572 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2573 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
a0a49813
DH		 2574 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2575 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
64fec58e
TC		 2576 } else {
2577 error_setg(errp, "acpi: device unplug request for not supported device"
2578 " type: %s", object_get_typename(OBJECT(dev)));
2579 }
d9c5c5b8
TC		 2580}
2581
232391c1
TC		 2582static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2583 DeviceState *dev, Error **errp)
2584{
f7d3e29d 2585 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2586 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a
IM		 2587 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2588 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
a0a49813
DH		 2589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
2590 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
f7d3e29d
TC		 2591 } else {
2592 error_setg(errp, "acpi: device unplug for not supported device"
2593 " type: %s", object_get_typename(OBJECT(dev)));
2594 }
232391c1
TC		 2595}
2596
285816d7 2597static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
95bee274
IM		 2598 DeviceState *dev)
2599{
5279569e 2600 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
a0a49813
DH		 2601 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
2602 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
95bee274
IM		 2603 return HOTPLUG_HANDLER(machine);
2604 }
2605
38aefb57 2606 return NULL;
95bee274
IM		 2607}
2608
bf1e8939 2609static void
f2ffbe2b
DH		 2610pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2611 const char *name, void *opaque,
2612 Error **errp)
bf1e8939 2613{
b0c14ec4 2614 MachineState *ms = MACHINE(obj);
fc3b77e2
IM		 2615 int64_t value = 0;
2616
2617 if (ms->device_memory) {
2618 value = memory_region_size(&ms->device_memory->mr);
2619 }
bf1e8939 2620
51e72bc1 2621 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 2622}
2623
c87b1520 2624static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2625 const char *name, void *opaque,
2626 Error **errp)
c87b1520
DS		 2627{
2628 PCMachineState *pcms = PC_MACHINE(obj);
2629 uint64_t value = pcms->max_ram_below_4g;
2630
51e72bc1 2631 visit_type_size(v, name, &value, errp);
c87b1520
DS		 2632}
2633
2634static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2635 const char *name, void *opaque,
2636 Error **errp)
c87b1520
DS		 2637{
2638 PCMachineState *pcms = PC_MACHINE(obj);
2639 Error *error = NULL;
2640 uint64_t value;
2641
51e72bc1 2642 visit_type_size(v, name, &value, &error);
c87b1520
DS		 2643 if (error) {
2644 error_propagate(errp, error);
2645 return;
2646 }
d471bf3e 2647 if (value > 4 * GiB) {
455b0fde
EB		 2648 error_setg(&error,
2649 "Machine option 'max-ram-below-4g=%"PRIu64
2650 "' expects size less than or equal to 4G", value);
c87b1520
DS		 2651 error_propagate(errp, error);
2652 return;
2653 }
2654
d471bf3e 2655 if (value < 1 * MiB) {
9e5d2c52
AF		 2656 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2657 "BIOS may not work with less than 1MiB", value);
c87b1520
DS		 2658 }
2659
2660 pcms->max_ram_below_4g = value;
2661}
2662
d7bce999
EB		 2663static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2664 void *opaque, Error **errp)
9b23cfb7
DDAG		 2665{
2666 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 2667 OnOffAuto vmport = pcms->vmport;
9b23cfb7 2668
51e72bc1 2669 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 2670}
2671
d7bce999
EB		 2672static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2673 void *opaque, Error **errp)
9b23cfb7
DDAG		 2674{
2675 PCMachineState *pcms = PC_MACHINE(obj);
2676
51e72bc1 2677 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 2678}
2679
355023f2
PB		 2680bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2681{
2682 bool smm_available = false;
2683
2684 if (pcms->smm == ON_OFF_AUTO_OFF) {
2685 return false;
2686 }
2687
2688 if (tcg_enabled() || qtest_enabled()) {
2689 smm_available = true;
2690 } else if (kvm_enabled()) {
2691 smm_available = kvm_has_smm();
2692 }
2693
2694 if (smm_available) {
2695 return true;
2696 }
2697
2698 if (pcms->smm == ON_OFF_AUTO_ON) {
2699 error_report("System Management Mode not supported by this hypervisor.");
2700 exit(1);
2701 }
2702 return false;
2703}
2704
d7bce999
EB		 2705static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2706 void *opaque, Error **errp)
355023f2
PB		 2707{
2708 PCMachineState *pcms = PC_MACHINE(obj);
2709 OnOffAuto smm = pcms->smm;
2710
51e72bc1 2711 visit_type_OnOffAuto(v, name, &smm, errp);
355023f2
PB		 2712}
2713
d7bce999
EB		 2714static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2715 void *opaque, Error **errp)
355023f2
PB		 2716{
2717 PCMachineState *pcms = PC_MACHINE(obj);
2718
51e72bc1 2719 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
355023f2
PB		 2720}
2721
be232eb0
CP		 2722static bool pc_machine_get_smbus(Object *obj, Error **errp)
2723{
2724 PCMachineState *pcms = PC_MACHINE(obj);
2725
f5878b03 2726 return pcms->smbus_enabled;
be232eb0
CP		 2727}
2728
2729static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2730{
2731 PCMachineState *pcms = PC_MACHINE(obj);
2732
f5878b03 2733 pcms->smbus_enabled = value;
be232eb0
CP		 2734}
2735
272f0428
CP		 2736static bool pc_machine_get_sata(Object *obj, Error **errp)
2737{
2738 PCMachineState *pcms = PC_MACHINE(obj);
2739
f5878b03 2740 return pcms->sata_enabled;
272f0428
CP		 2741}
2742
2743static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2744{
2745 PCMachineState *pcms = PC_MACHINE(obj);
2746
f5878b03 2747 pcms->sata_enabled = value;
272f0428
CP		 2748}
2749
feddd2fd
CP		 2750static bool pc_machine_get_pit(Object *obj, Error **errp)
2751{
2752 PCMachineState *pcms = PC_MACHINE(obj);
2753
f5878b03 2754 return pcms->pit_enabled;
feddd2fd
CP		 2755}
2756
2757static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2758{
2759 PCMachineState *pcms = PC_MACHINE(obj);
2760
f5878b03 2761 pcms->pit_enabled = value;
feddd2fd
CP		 2762}
2763
bf1e8939
IM		 2764static void pc_machine_initfn(Object *obj)
2765{
c87b1520
DS		 2766 PCMachineState *pcms = PC_MACHINE(obj);
2767
5ec7d098 2768 pcms->max_ram_below_4g = 0; /* use default */
355023f2 2769 pcms->smm = ON_OFF_AUTO_AUTO;
97fd1ea8 2770#ifdef CONFIG_VMPORT
d1048bef 2771 pcms->vmport = ON_OFF_AUTO_AUTO;
97fd1ea8
JM		 2772#else
2773 pcms->vmport = ON_OFF_AUTO_OFF;
2774#endif /* CONFIG_VMPORT */
021746c1
WL		 2775 /* acpi build is enabled by default if machine supports it */
2776 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 2777 pcms->smbus_enabled = true;
2778 pcms->sata_enabled = true;
2779 pcms->pit_enabled = true;
c26ae610 2780 pcms->smp_dies = 1;
ebc29e1b
MA		 2781
2782 pc_system_flash_create(pcms);
bf1e8939
IM		 2783}
2784
a0628599 2785static void pc_machine_reset(MachineState *machine)
ae50c55a
ZG		 2786{
2787 CPUState *cs;
2788 X86CPU *cpu;
2789
2790 qemu_devices_reset();
2791
2792 /* Reset APIC after devices have been reset to cancel
2793 * any changes that qemu_devices_reset() might have done.
2794 */
2795 CPU_FOREACH(cs) {
2796 cpu = X86_CPU(cs);
2797
2798 if (cpu->apic_state) {
2799 device_reset(cpu->apic_state);
2800 }
2801 }
2802}
2803
c508bd12
NP		 2804static void pc_machine_wakeup(MachineState *machine)
2805{
2806 cpu_synchronize_all_states();
2807 pc_machine_reset(machine);
2808 cpu_synchronize_all_post_reset();
2809}
2810
ea089eeb
IM		 2811static CpuInstanceProperties
2812pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
fb43b73b 2813{
ea089eeb
IM		 2814 MachineClass *mc = MACHINE_GET_CLASS(ms);
2815 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2816
2817 assert(cpu_index < possible_cpus->len);
2818 return possible_cpus->cpus[cpu_index].props;
fb43b73b
IM		 2819}
2820
79e07936
IM		 2821static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2822{
2823 X86CPUTopoInfo topo;
d65af288 2824 PCMachineState *pcms = PC_MACHINE(ms);
79e07936
IM		 2825
2826 assert(idx < ms->possible_cpus->len);
2827 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
d65af288
LX		 2828 pcms->smp_dies, ms->smp.cores,
2829 ms->smp.threads, &topo);
aa570207 2830 return topo.pkg_id % ms->numa_state->num_nodes;
79e07936
IM		 2831}
2832
c96a1c0b 2833static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
3811ef14 2834{
457cfccc 2835 PCMachineState *pcms = PC_MACHINE(ms);
c96a1c0b 2836 int i;
0e11fc69 2837 unsigned int max_cpus = ms->smp.max_cpus;
c96a1c0b
IM		 2838
2839 if (ms->possible_cpus) {
2840 /*
2841 * make sure that max_cpus hasn't changed since the first use, i.e.
2842 * -smp hasn't been parsed after it
2843 */
2844 assert(ms->possible_cpus->len == max_cpus);
2845 return ms->possible_cpus;
2846 }
2847
2848 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2849 sizeof(CPUArchId) * max_cpus);
2850 ms->possible_cpus->len = max_cpus;
2851 for (i = 0; i < ms->possible_cpus->len; i++) {
c67ae933
IM		 2852 X86CPUTopoInfo topo;
2853
d342eb76 2854 ms->possible_cpus->cpus[i].type = ms->cpu_type;
f2d672c2 2855 ms->possible_cpus->cpus[i].vcpus_count = 1;
457cfccc 2856 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i);
c67ae933 2857 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
d65af288
LX		 2858 pcms->smp_dies, ms->smp.cores,
2859 ms->smp.threads, &topo);
c67ae933
IM		 2860 ms->possible_cpus->cpus[i].props.has_socket_id = true;
2861 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
c6c1bb89
IM		 2862 if (pcms->smp_dies > 1) {
2863 ms->possible_cpus->cpus[i].props.has_die_id = true;
2864 ms->possible_cpus->cpus[i].props.die_id = topo.die_id;
2865 }
c67ae933
IM		 2866 ms->possible_cpus->cpus[i].props.has_core_id = true;
2867 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
2868 ms->possible_cpus->cpus[i].props.has_thread_id = true;
2869 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
c96a1c0b
IM		 2870 }
2871 return ms->possible_cpus;
3811ef14
IM		 2872}
2873
1255166b
BD		 2874static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
2875{
2876 /* cpu index isn't used */
2877 CPUState *cs;
2878
2879 CPU_FOREACH(cs) {
2880 X86CPU *cpu = X86_CPU(cs);
2881
2882 if (!cpu->apic_state) {
2883 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
2884 } else {
2885 apic_deliver_nmi(cpu->apic_state);
2886 }
2887 }
2888}
2889
95bee274
IM		 2890static void pc_machine_class_init(ObjectClass *oc, void *data)
2891{
2892 MachineClass *mc = MACHINE_CLASS(oc);
2893 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
2894 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1255166b 2895 NMIClass *nc = NMI_CLASS(oc);
95bee274 2896
7102fa70
EH		 2897 pcmc->pci_enabled = true;
2898 pcmc->has_acpi_build = true;
2899 pcmc->rsdp_in_ram = true;
2900 pcmc->smbios_defaults = true;
2901 pcmc->smbios_uuid_encoded = true;
2902 pcmc->gigabyte_align = true;
2903 pcmc->has_reserved_memory = true;
2904 pcmc->kvmclock_enabled = true;
16a9e8a5 2905 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 2906 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
2907 * to be used at the moment, 32K should be enough for a while. */
2908 pcmc->acpi_data_size = 0x20000 + 0x8000;
36f96c4b 2909 pcmc->save_tsc_khz = true;
98e753a6 2910 pcmc->linuxboot_dma_enabled = true;
fda672b5 2911 pcmc->pvh_enabled = true;
debbdc00 2912 assert(!mc->get_hotplug_handler);
285816d7 2913 mc->get_hotplug_handler = pc_get_hotplug_handler;
ea089eeb 2914 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
79e07936 2915 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
3811ef14 2916 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
7b8be49d 2917 mc->auto_enable_numa_with_memhp = true;
c5514d0e 2918 mc->has_hotpluggable_cpus = true;
41742767 2919 mc->default_boot_order = "cad";
4458fb3a 2920 mc->hot_add_cpu = pc_hot_add_cpu;
6f479566 2921 mc->smp_parse = pc_smp_parse;
2059839b 2922 mc->block_default_type = IF_IDE;
4458fb3a 2923 mc->max_cpus = 255;
ae50c55a 2924 mc->reset = pc_machine_reset;
c508bd12 2925 mc->wakeup = pc_machine_wakeup;
4ec60c76 2926 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 2927 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 2928 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 2929 hc->unplug = pc_machine_device_unplug_cb;
1255166b 2930 nc->nmi_monitor_handler = x86_nmi;
311ca98d 2931 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
f6a0d06b 2932 mc->nvdimm_supported = true;
cd5ff833 2933 mc->numa_mem_supported = true;
0efc257d 2934
f2ffbe2b
DH		 2935 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
2936 pc_machine_get_device_memory_region_size, NULL,
0efc257d
EH		 2937 NULL, NULL, &error_abort);
2938
2939 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
2940 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
2941 NULL, NULL, &error_abort);
2942
2943 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
2944 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
2945
2946 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
2947 pc_machine_get_smm, pc_machine_set_smm,
2948 NULL, NULL, &error_abort);
2949 object_class_property_set_description(oc, PC_MACHINE_SMM,
2950 "Enable SMM (pc & q35)", &error_abort);
2951
2952 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
2953 pc_machine_get_vmport, pc_machine_set_vmport,
2954 NULL, NULL, &error_abort);
2955 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
2956 "Enable vmport (pc & q35)", &error_abort);
2957
be232eb0
CP		 2958 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
2959 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
272f0428
CP		 2960
2961 object_class_property_add_bool(oc, PC_MACHINE_SATA,
2962 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
feddd2fd
CP		 2963
2964 object_class_property_add_bool(oc, PC_MACHINE_PIT,
2965 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
95bee274
IM		 2966}
2967
d5747cac
IM		 2968static const TypeInfo pc_machine_info = {
2969 .name = TYPE_PC_MACHINE,
2970 .parent = TYPE_MACHINE,
2971 .abstract = true,
2972 .instance_size = sizeof(PCMachineState),
bf1e8939 2973 .instance_init = pc_machine_initfn,
d5747cac 2974 .class_size = sizeof(PCMachineClass),
95bee274
IM		 2975 .class_init = pc_machine_class_init,
2976 .interfaces = (InterfaceInfo[]) {
2977 { TYPE_HOTPLUG_HANDLER },
1255166b 2978 { TYPE_NMI },
95bee274
IM		 2979 { }
2980 },
d5747cac
IM		 2981};
2982
2983static void pc_machine_register_types(void)
2984{
2985 type_register_static(&pc_machine_info);
2986}
2987
2988type_init(pc_machine_register_types)
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