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machine: Eliminate unnecessary stringify() usage
[mirror_qemu.git] / hw / i386 / pc.c
CommitLineData
80cabfad
FB		 1/*
2 * QEMU PC System Emulator
5fafdf24 3 *
80cabfad 4 * Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24 5 *
80cabfad
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
e688df6b 24
b6a0aa05 25#include "qemu/osdep.h"
d471bf3e 26#include "qemu/units.h"
83c9f4ca 27#include "hw/hw.h"
0d09e41a
PB		 28#include "hw/i386/pc.h"
29#include "hw/char/serial.h"
bb3d5ea8 30#include "hw/char/parallel.h"
0d09e41a 31#include "hw/i386/apic.h"
54a40293
EH		 32#include "hw/i386/topology.h"
33#include "sysemu/cpus.h"
0d09e41a 34#include "hw/block/fdc.h"
83c9f4ca
PB		 35#include "hw/ide.h"
36#include "hw/pci/pci.h"
2118196b 37#include "hw/pci/pci_bus.h"
0d09e41a
PB		 38#include "hw/nvram/fw_cfg.h"
39#include "hw/timer/hpet.h"
a2eb5c0c 40#include "hw/firmware/smbios.h"
83c9f4ca 41#include "hw/loader.h"
ca20cf32 42#include "elf.h"
47b43a1f 43#include "multiboot.h"
0d09e41a 44#include "hw/timer/mc146818rtc.h"
55f613ac 45#include "hw/dma/i8257.h"
0d09e41a 46#include "hw/timer/i8254.h"
47973a2d 47#include "hw/input/i8042.h"
0d09e41a 48#include "hw/audio/pcspk.h"
83c9f4ca
PB		 49#include "hw/pci/msi.h"
50#include "hw/sysbus.h"
9c17d615 51#include "sysemu/sysemu.h"
e35704ba 52#include "sysemu/numa.h"
9c17d615 53#include "sysemu/kvm.h"
b1c12027 54#include "sysemu/qtest.h"
1d31f66b 55#include "kvm_i386.h"
0d09e41a 56#include "hw/xen/xen.h"
a19cbfb3 57#include "ui/qemu-spice.h"
022c62cb
PB		 58#include "exec/memory.h"
59#include "exec/address-spaces.h"
9c17d615 60#include "sysemu/arch_init.h"
1de7afc9 61#include "qemu/bitmap.h"
0c764a9d 62#include "qemu/config-file.h"
d49b6836 63#include "qemu/error-report.h"
922a01a0 64#include "qemu/option.h"
0445259b 65#include "hw/acpi/acpi.h"
5ff020b7 66#include "hw/acpi/cpu_hotplug.h"
c649983b 67#include "hw/boards.h"
72c194f7 68#include "acpi-build.h"
95bee274 69#include "hw/mem/pc-dimm.h"
e688df6b 70#include "qapi/error.h"
9af23989 71#include "qapi/qapi-visit-common.h"
bf1e8939 72#include "qapi/visitor.h"
15eafc2e 73#include "qom/cpu.h"
1255166b 74#include "hw/nmi.h"
a310e653 75#include "hw/usb.h"
60c5e104 76#include "hw/i386/intel_iommu.h"
489983d6 77#include "hw/net/ne2000-isa.h"
80cabfad 78
471fd342
BS		 79/* debug PC/ISA interrupts */
80//#define DEBUG_IRQ
81
82#ifdef DEBUG_IRQ
83#define DPRINTF(fmt, ...) \
84 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
85#else
86#define DPRINTF(fmt, ...)
87#endif
88
8a92ea2f 89#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
b6f6e3d3 90#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
6b35e7bf 91#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
4c5b10b7 92#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
40ac17cd 93#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
80cabfad 94
4c5b10b7
JS		 95#define E820_NR_ENTRIES 16
96
97struct e820_entry {
98 uint64_t address;
99 uint64_t length;
100 uint32_t type;
541dc0d4 101} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7
JS		 102
103struct e820_table {
104 uint32_t count;
105 struct e820_entry entry[E820_NR_ENTRIES];
541dc0d4 106} QEMU_PACKED __attribute((__aligned__(4)));
4c5b10b7 107
7d67110f
GH		 108static struct e820_table e820_reserve;
109static struct e820_entry *e820_table;
110static unsigned e820_entries;
dd703b99 111struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
4c5b10b7 112
abd93cc7
MAL		 113GlobalProperty pc_compat_3_1[] = {
114 {
115 .driver = "intel-iommu",
116 .property = "dma-drain",
117 .value = "off",
118 },
119};
120const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
121
ddb3235d
MAL		 122GlobalProperty pc_compat_3_0[] = {
123 {
124 .driver = TYPE_X86_CPU,
125 .property = "x-hv-synic-kvm-only",
126 .value = "on",
127 },{
128 .driver = "Skylake-Server" "-" TYPE_X86_CPU,
129 .property = "pku",
130 .value = "off",
131 },{
132 .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,
133 .property = "pku",
134 .value = "off",
135 },
136};
137const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
138
0d47310b
MAL		 139GlobalProperty pc_compat_2_12[] = {
140 {
141 .driver = TYPE_X86_CPU,
142 .property = "legacy-cache",
143 .value = "on",
144 },{
145 .driver = TYPE_X86_CPU,
146 .property = "topoext",
147 .value = "off",
148 },{
149 .driver = "EPYC-" TYPE_X86_CPU,
150 .property = "xlevel",
e0985450 151 .value = "0x8000000a",
0d47310b
MAL		 152 },{
153 .driver = "EPYC-IBPB-" TYPE_X86_CPU,
154 .property = "xlevel",
e0985450 155 .value = "0x8000000a",
0d47310b
MAL		 156 },
157};
158const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
159
43df70a9
MAL		 160GlobalProperty pc_compat_2_11[] = {
161 {
162 .driver = TYPE_X86_CPU,
163 .property = "x-migrate-smi-count",
164 .value = "off",
165 },{
166 .driver = "Skylake-Server" "-" TYPE_X86_CPU,
167 .property = "clflushopt",
168 .value = "off",
169 },
170};
171const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
172
503224f4
MAL		 173GlobalProperty pc_compat_2_10[] = {
174 {
175 .driver = TYPE_X86_CPU,
176 .property = "x-hv-max-vps",
177 .value = "0x40",
178 },{
179 .driver = "i440FX-pcihost",
180 .property = "x-pci-hole64-fix",
181 .value = "off",
182 },{
183 .driver = "q35-pcihost",
184 .property = "x-pci-hole64-fix",
185 .value = "off",
186 },
187};
188const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
189
3e803152
MAL		 190GlobalProperty pc_compat_2_9[] = {
191 {
192 .driver = "mch",
193 .property = "extended-tseg-mbytes",
e0985450 194 .value = "0",
3e803152
MAL		 195 },
196};
197const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
198
edc24ccd
MAL		 199GlobalProperty pc_compat_2_8[] = {
200 {
201 .driver = TYPE_X86_CPU,
202 .property = "tcg-cpuid",
203 .value = "off",
204 },
205 {
206 .driver = "kvmclock",
207 .property = "x-mach-use-reliable-get-clock",
208 .value = "off",
209 },
210 {
211 .driver = "ICH9-LPC",
212 .property = "x-smi-broadcast",
213 .value = "off",
214 },
215 {
216 .driver = TYPE_X86_CPU,
217 .property = "vmware-cpuid-freq",
218 .value = "off",
219 },
220 {
221 .driver = "Haswell-" TYPE_X86_CPU,
222 .property = "stepping",
223 .value = "1",
224 },
225};
226const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
227
5a995064
MAL		 228GlobalProperty pc_compat_2_7[] = {
229 {
230 .driver = TYPE_X86_CPU,
231 .property = "l3-cache",
232 .value = "off",
233 },
234 {
235 .driver = TYPE_X86_CPU,
236 .property = "full-cpuid-auto-level",
237 .value = "off",
238 },
239 {
240 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
241 .property = "family",
242 .value = "15",
243 },
244 {
245 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
246 .property = "model",
247 .value = "6",
248 },
249 {
250 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
251 .property = "stepping",
252 .value = "1",
253 },
254 {
255 .driver = "isa-pcspk",
256 .property = "migrate",
257 .value = "off",
258 },
259};
260const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
261
ff8f261f
MAL		 262GlobalProperty pc_compat_2_6[] = {
263 {
264 .driver = TYPE_X86_CPU,
265 .property = "cpuid-0xb",
266 .value = "off",
267 },{
268 .driver = "vmxnet3",
269 .property = "romfile",
270 .value = "",
271 },
272 {
273 .driver = TYPE_X86_CPU,
274 .property = "fill-mtrr-mask",
275 .value = "off",
276 },
277 {
278 .driver = "apic-common",
279 .property = "legacy-instance-id",
280 .value = "on",
281 }
282};
283const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
284
fe759610
MAL		 285GlobalProperty pc_compat_2_5[] = {};
286const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
287
2f99b9c2
MAL		 288GlobalProperty pc_compat_2_4[] = {
289 PC_CPU_MODEL_IDS("2.4.0")
290 {
291 .driver = "Haswell-" TYPE_X86_CPU,
292 .property = "abm",
293 .value = "off",
294 },
295 {
296 .driver = "Haswell-noTSX-" TYPE_X86_CPU,
297 .property = "abm",
298 .value = "off",
299 },
300 {
301 .driver = "Broadwell-" TYPE_X86_CPU,
302 .property = "abm",
303 .value = "off",
304 },
305 {
306 .driver = "Broadwell-noTSX-" TYPE_X86_CPU,
307 .property = "abm",
308 .value = "off",
309 },
310 {
311 .driver = "host" "-" TYPE_X86_CPU,
312 .property = "host-cache-info",
313 .value = "on",
314 },
315 {
316 .driver = TYPE_X86_CPU,
317 .property = "check",
318 .value = "off",
319 },
320 {
321 .driver = "qemu64" "-" TYPE_X86_CPU,
322 .property = "sse4a",
323 .value = "on",
324 },
325 {
326 .driver = "qemu64" "-" TYPE_X86_CPU,
327 .property = "abm",
328 .value = "on",
329 },
330 {
331 .driver = "qemu64" "-" TYPE_X86_CPU,
332 .property = "popcnt",
333 .value = "on",
334 },
335 {
336 .driver = "qemu32" "-" TYPE_X86_CPU,
337 .property = "popcnt",
338 .value = "on",
339 },{
340 .driver = "Opteron_G2" "-" TYPE_X86_CPU,
341 .property = "rdtscp",
342 .value = "on",
343 },{
344 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
345 .property = "rdtscp",
346 .value = "on",
347 },{
348 .driver = "Opteron_G4" "-" TYPE_X86_CPU,
349 .property = "rdtscp",
350 .value = "on",
351 },{
352 .driver = "Opteron_G5" "-" TYPE_X86_CPU,
353 .property = "rdtscp",
354 .value = "on",
355 }
356};
357const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
358
8995dd90
MAL		 359GlobalProperty pc_compat_2_3[] = {
360 PC_CPU_MODEL_IDS("2.3.0")
361 {
362 .driver = TYPE_X86_CPU,
363 .property = "arat",
364 .value = "off",
365 },{
366 .driver = "qemu64" "-" TYPE_X86_CPU,
367 .property = "min-level",
e0985450 368 .value = "4",
8995dd90
MAL		 369 },{
370 .driver = "kvm64" "-" TYPE_X86_CPU,
371 .property = "min-level",
e0985450 372 .value = "5",
8995dd90
MAL		 373 },{
374 .driver = "pentium3" "-" TYPE_X86_CPU,
375 .property = "min-level",
e0985450 376 .value = "2",
8995dd90
MAL		 377 },{
378 .driver = "n270" "-" TYPE_X86_CPU,
379 .property = "min-level",
e0985450 380 .value = "5",
8995dd90
MAL		 381 },{
382 .driver = "Conroe" "-" TYPE_X86_CPU,
383 .property = "min-level",
e0985450 384 .value = "4",
8995dd90
MAL		 385 },{
386 .driver = "Penryn" "-" TYPE_X86_CPU,
387 .property = "min-level",
e0985450 388 .value = "4",
8995dd90
MAL		 389 },{
390 .driver = "Nehalem" "-" TYPE_X86_CPU,
391 .property = "min-level",
e0985450 392 .value = "4",
8995dd90
MAL		 393 },{
394 .driver = "n270" "-" TYPE_X86_CPU,
395 .property = "min-xlevel",
e0985450 396 .value = "0x8000000a",
8995dd90
MAL		 397 },{
398 .driver = "Penryn" "-" TYPE_X86_CPU,
399 .property = "min-xlevel",
e0985450 400 .value = "0x8000000a",
8995dd90
MAL		 401 },{
402 .driver = "Conroe" "-" TYPE_X86_CPU,
403 .property = "min-xlevel",
e0985450 404 .value = "0x8000000a",
8995dd90
MAL		 405 },{
406 .driver = "Nehalem" "-" TYPE_X86_CPU,
407 .property = "min-xlevel",
e0985450 408 .value = "0x8000000a",
8995dd90
MAL		 409 },{
410 .driver = "Westmere" "-" TYPE_X86_CPU,
411 .property = "min-xlevel",
e0985450 412 .value = "0x8000000a",
8995dd90
MAL		 413 },{
414 .driver = "SandyBridge" "-" TYPE_X86_CPU,
415 .property = "min-xlevel",
e0985450 416 .value = "0x8000000a",
8995dd90
MAL		 417 },{
418 .driver = "IvyBridge" "-" TYPE_X86_CPU,
419 .property = "min-xlevel",
e0985450 420 .value = "0x8000000a",
8995dd90
MAL		 421 },{
422 .driver = "Haswell" "-" TYPE_X86_CPU,
423 .property = "min-xlevel",
e0985450 424 .value = "0x8000000a",
8995dd90
MAL		 425 },{
426 .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,
427 .property = "min-xlevel",
e0985450 428 .value = "0x8000000a",
8995dd90
MAL		 429 },{
430 .driver = "Broadwell" "-" TYPE_X86_CPU,
431 .property = "min-xlevel",
e0985450 432 .value = "0x8000000a",
8995dd90
MAL		 433 },{
434 .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,
435 .property = "min-xlevel",
e0985450 436 .value = "0x8000000a",
8995dd90
MAL		 437 },{
438 .driver = TYPE_X86_CPU,
439 .property = "kvm-no-smi-migration",
440 .value = "on",
441 },
442};
443const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
444
1c30044e
MAL		 445GlobalProperty pc_compat_2_2[] = {
446 PC_CPU_MODEL_IDS("2.2.0")
447 {
448 .driver = "kvm64" "-" TYPE_X86_CPU,
449 .property = "vme",
450 .value = "off",
451 },
452 {
453 .driver = "kvm32" "-" TYPE_X86_CPU,
454 .property = "vme",
455 .value = "off",
456 },
457 {
458 .driver = "Conroe" "-" TYPE_X86_CPU,
459 .property = "vme",
460 .value = "off",
461 },
462 {
463 .driver = "Penryn" "-" TYPE_X86_CPU,
464 .property = "vme",
465 .value = "off",
466 },
467 {
468 .driver = "Nehalem" "-" TYPE_X86_CPU,
469 .property = "vme",
470 .value = "off",
471 },
472 {
473 .driver = "Westmere" "-" TYPE_X86_CPU,
474 .property = "vme",
475 .value = "off",
476 },
477 {
478 .driver = "SandyBridge" "-" TYPE_X86_CPU,
479 .property = "vme",
480 .value = "off",
481 },
482 {
483 .driver = "Haswell" "-" TYPE_X86_CPU,
484 .property = "vme",
485 .value = "off",
486 },
487 {
488 .driver = "Broadwell" "-" TYPE_X86_CPU,
489 .property = "vme",
490 .value = "off",
491 },
492 {
493 .driver = "Opteron_G1" "-" TYPE_X86_CPU,
494 .property = "vme",
495 .value = "off",
496 },
497 {
498 .driver = "Opteron_G2" "-" TYPE_X86_CPU,
499 .property = "vme",
500 .value = "off",
501 },
502 {
503 .driver = "Opteron_G3" "-" TYPE_X86_CPU,
504 .property = "vme",
505 .value = "off",
506 },
507 {
508 .driver = "Opteron_G4" "-" TYPE_X86_CPU,
509 .property = "vme",
510 .value = "off",
511 },
512 {
513 .driver = "Opteron_G5" "-" TYPE_X86_CPU,
514 .property = "vme",
515 .value = "off",
516 },
517 {
518 .driver = "Haswell" "-" TYPE_X86_CPU,
519 .property = "f16c",
520 .value = "off",
521 },
522 {
523 .driver = "Haswell" "-" TYPE_X86_CPU,
524 .property = "rdrand",
525 .value = "off",
526 },
527 {
528 .driver = "Broadwell" "-" TYPE_X86_CPU,
529 .property = "f16c",
530 .value = "off",
531 },
532 {
533 .driver = "Broadwell" "-" TYPE_X86_CPU,
534 .property = "rdrand",
535 .value = "off",
536 },
537};
538const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
539
c4fc5695
MAL		 540GlobalProperty pc_compat_2_1[] = {
541 PC_CPU_MODEL_IDS("2.1.0")
542 {
543 .driver = "coreduo" "-" TYPE_X86_CPU,
544 .property = "vmx",
545 .value = "on",
546 },
547 {
548 .driver = "core2duo" "-" TYPE_X86_CPU,
549 .property = "vmx",
550 .value = "on",
551 },
552};
553const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
554
a310e653
MAL		 555GlobalProperty pc_compat_2_0[] = {
556 PC_CPU_MODEL_IDS("2.0.0")
557 {
558 .driver = "virtio-scsi-pci",
559 .property = "any_layout",
560 .value = "off",
561 },{
562 .driver = "PIIX4_PM",
563 .property = "memory-hotplug-support",
564 .value = "off",
565 },
566 {
567 .driver = "apic",
568 .property = "version",
e0985450 569 .value = "0x11",
a310e653
MAL		 570 },
571 {
572 .driver = "nec-usb-xhci",
573 .property = "superspeed-ports-first",
574 .value = "off",
575 },
576 {
577 .driver = "nec-usb-xhci",
578 .property = "force-pcie-endcap",
579 .value = "on",
580 },
581 {
582 .driver = "pci-serial",
583 .property = "prog_if",
e0985450 584 .value = "0",
a310e653
MAL		 585 },
586 {
587 .driver = "pci-serial-2x",
588 .property = "prog_if",
e0985450 589 .value = "0",
a310e653
MAL		 590 },
591 {
592 .driver = "pci-serial-4x",
593 .property = "prog_if",
e0985450 594 .value = "0",
a310e653
MAL		 595 },
596 {
597 .driver = "virtio-net-pci",
598 .property = "guest_announce",
599 .value = "off",
600 },
601 {
602 .driver = "ICH9-LPC",
603 .property = "memory-hotplug-support",
604 .value = "off",
605 },{
606 .driver = "xio3130-downstream",
607 .property = COMPAT_PROP_PCP,
608 .value = "off",
609 },{
610 .driver = "ioh3420",
611 .property = COMPAT_PROP_PCP,
612 .value = "off",
613 },
614};
615const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
616
617GlobalProperty pc_compat_1_7[] = {
618 PC_CPU_MODEL_IDS("1.7.0")
619 {
620 .driver = TYPE_USB_DEVICE,
621 .property = "msos-desc",
622 .value = "no",
623 },
624 {
625 .driver = "PIIX4_PM",
626 .property = "acpi-pci-hotplug-with-bridge-support",
627 .value = "off",
628 },
629 {
630 .driver = "hpet",
631 .property = HPET_INTCAP,
e0985450 632 .value = "4",
a310e653
MAL		 633 },
634};
635const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
636
637GlobalProperty pc_compat_1_6[] = {
638 PC_CPU_MODEL_IDS("1.6.0")
639 {
640 .driver = "e1000",
641 .property = "mitigation",
642 .value = "off",
643 },{
644 .driver = "qemu64-" TYPE_X86_CPU,
645 .property = "model",
e0985450 646 .value = "2",
a310e653
MAL		 647 },{
648 .driver = "qemu32-" TYPE_X86_CPU,
649 .property = "model",
e0985450 650 .value = "3",
a310e653
MAL		 651 },{
652 .driver = "i440FX-pcihost",
653 .property = "short_root_bus",
e0985450 654 .value = "1",
a310e653
MAL		 655 },{
656 .driver = "q35-pcihost",
657 .property = "short_root_bus",
e0985450 658 .value = "1",
a310e653
MAL		 659 },
660};
661const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
662
663GlobalProperty pc_compat_1_5[] = {
664 PC_CPU_MODEL_IDS("1.5.0")
665 {
666 .driver = "Conroe-" TYPE_X86_CPU,
667 .property = "model",
e0985450 668 .value = "2",
a310e653
MAL		 669 },{
670 .driver = "Conroe-" TYPE_X86_CPU,
671 .property = "min-level",
e0985450 672 .value = "2",
a310e653
MAL		 673 },{
674 .driver = "Penryn-" TYPE_X86_CPU,
675 .property = "model",
e0985450 676 .value = "2",
a310e653
MAL		 677 },{
678 .driver = "Penryn-" TYPE_X86_CPU,
679 .property = "min-level",
e0985450 680 .value = "2",
a310e653
MAL		 681 },{
682 .driver = "Nehalem-" TYPE_X86_CPU,
683 .property = "model",
e0985450 684 .value = "2",
a310e653
MAL		 685 },{
686 .driver = "Nehalem-" TYPE_X86_CPU,
687 .property = "min-level",
e0985450 688 .value = "2",
a310e653
MAL		 689 },{
690 .driver = "virtio-net-pci",
691 .property = "any_layout",
692 .value = "off",
693 },{
694 .driver = TYPE_X86_CPU,
695 .property = "pmu",
696 .value = "on",
697 },{
698 .driver = "i440FX-pcihost",
699 .property = "short_root_bus",
e0985450 700 .value = "0",
a310e653
MAL		 701 },{
702 .driver = "q35-pcihost",
703 .property = "short_root_bus",
e0985450 704 .value = "0",
a310e653
MAL		 705 },
706};
707const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
708
709GlobalProperty pc_compat_1_4[] = {
710 PC_CPU_MODEL_IDS("1.4.0")
711 {
712 .driver = "scsi-hd",
713 .property = "discard_granularity",
e0985450 714 .value = "0",
a310e653
MAL		 715 },{
716 .driver = "scsi-cd",
717 .property = "discard_granularity",
e0985450 718 .value = "0",
a310e653
MAL		 719 },{
720 .driver = "scsi-disk",
721 .property = "discard_granularity",
e0985450 722 .value = "0",
a310e653
MAL		 723 },{
724 .driver = "ide-hd",
725 .property = "discard_granularity",
e0985450 726 .value = "0",
a310e653
MAL		 727 },{
728 .driver = "ide-cd",
729 .property = "discard_granularity",
e0985450 730 .value = "0",
a310e653
MAL		 731 },{
732 .driver = "ide-drive",
733 .property = "discard_granularity",
e0985450 734 .value = "0",
a310e653
MAL		 735 },{
736 .driver = "virtio-blk-pci",
737 .property = "discard_granularity",
e0985450 738 .value = "0",
a310e653
MAL		 739 },{
740 .driver = "virtio-serial-pci",
741 .property = "vectors",
742 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */
e0985450 743 .value = "0xFFFFFFFF",
a310e653
MAL		 744 },{
745 .driver = "virtio-net-pci",
746 .property = "ctrl_guest_offloads",
747 .value = "off",
748 },{
749 .driver = "e1000",
750 .property = "romfile",
751 .value = "pxe-e1000.rom",
752 },{
753 .driver = "ne2k_pci",
754 .property = "romfile",
755 .value = "pxe-ne2k_pci.rom",
756 },{
757 .driver = "pcnet",
758 .property = "romfile",
759 .value = "pxe-pcnet.rom",
760 },{
761 .driver = "rtl8139",
762 .property = "romfile",
763 .value = "pxe-rtl8139.rom",
764 },{
765 .driver = "virtio-net-pci",
766 .property = "romfile",
767 .value = "pxe-virtio.rom",
768 },{
769 .driver = "486-" TYPE_X86_CPU,
770 .property = "model",
e0985450 771 .value = "0",
a310e653
MAL		 772 },
773 {
774 .driver = "n270" "-" TYPE_X86_CPU,
775 .property = "movbe",
776 .value = "off",
777 },
778 {
779 .driver = "Westmere" "-" TYPE_X86_CPU,
780 .property = "pclmulqdq",
781 .value = "off",
782 },
783};
784const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
785
b881fbe9 786void gsi_handler(void *opaque, int n, int level)
1452411b 787{
b881fbe9 788 GSIState *s = opaque;
1452411b 789
b881fbe9
JK		 790 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
791 if (n < ISA_NUM_IRQS) {
792 qemu_set_irq(s->i8259_irq[n], level);
1632dc6a 793 }
b881fbe9 794 qemu_set_irq(s->ioapic_irq[n], level);
2e9947d2 795}
1452411b 796
258711c6
JG		 797static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
798 unsigned size)
80cabfad
FB		 799{
800}
801
c02e1eac
JG		 802static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
803{
a6fc23e5 804 return 0xffffffffffffffffULL;
c02e1eac
JG		 805}
806
f929aad6 807/* MSDOS compatibility mode FPU exception support */
d537cf6c 808static qemu_irq ferr_irq;
8e78eb28
IY		 809
810void pc_register_ferr_irq(qemu_irq irq)
811{
812 ferr_irq = irq;
813}
814
f929aad6
FB		 815/* XXX: add IGNNE support */
816void cpu_set_ferr(CPUX86State *s)
817{
d537cf6c 818 qemu_irq_raise(ferr_irq);
f929aad6
FB		 819}
820
258711c6
JG		 821static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
822 unsigned size)
f929aad6 823{
d537cf6c 824 qemu_irq_lower(ferr_irq);
f929aad6
FB		 825}
826
c02e1eac
JG		 827static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
828{
a6fc23e5 829 return 0xffffffffffffffffULL;
c02e1eac
JG		 830}
831
28ab0e2e 832/* TSC handling */
28ab0e2e
FB		 833uint64_t cpu_get_tsc(CPUX86State *env)
834{
4a1418e0 835 return cpu_get_ticks();
28ab0e2e
FB		 836}
837
3de388f6 838/* IRQ handling */
4a8fa5dc 839int cpu_get_pic_interrupt(CPUX86State *env)
3de388f6 840{
02e51483 841 X86CPU *cpu = x86_env_get_cpu(env);
3de388f6
FB		 842 int intno;
843
bb93e099
WL		 844 if (!kvm_irqchip_in_kernel()) {
845 intno = apic_get_interrupt(cpu->apic_state);
846 if (intno >= 0) {
847 return intno;
848 }
849 /* read the irq from the PIC */
850 if (!apic_accept_pic_intr(cpu->apic_state)) {
851 return -1;
852 }
cf6d64bf 853 }
0e21e12b 854
3de388f6
FB		 855 intno = pic_read_irq(isa_pic);
856 return intno;
857}
858
d537cf6c 859static void pic_irq_request(void *opaque, int irq, int level)
3de388f6 860{
182735ef
AF		 861 CPUState *cs = first_cpu;
862 X86CPU *cpu = X86_CPU(cs);
a5b38b51 863
471fd342 864 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
bb93e099 865 if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
bdc44640 866 CPU_FOREACH(cs) {
182735ef 867 cpu = X86_CPU(cs);
02e51483
CF		 868 if (apic_accept_pic_intr(cpu->apic_state)) {
869 apic_deliver_pic_intr(cpu->apic_state, level);
cf6d64bf 870 }
d5529471
AJ		 871 }
872 } else {
d8ed887b 873 if (level) {
c3affe56 874 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d8ed887b
AF		 875 } else {
876 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
877 }
a5b38b51 878 }
3de388f6
FB		 879}
880
b0a21b53
FB		 881/* PC cmos mappings */
882
80cabfad
FB		 883#define REG_EQUIPMENT_BYTE 0x14
884
bda05509 885int cmos_get_fd_drive_type(FloppyDriveType fd0)
777428f2
FB		 886{
887 int val;
888
889 switch (fd0) {
2da44dd0 890 case FLOPPY_DRIVE_TYPE_144:
777428f2
FB		 891 /* 1.44 Mb 3"5 drive */
892 val = 4;
893 break;
2da44dd0 894 case FLOPPY_DRIVE_TYPE_288:
777428f2
FB		 895 /* 2.88 Mb 3"5 drive */
896 val = 5;
897 break;
2da44dd0 898 case FLOPPY_DRIVE_TYPE_120:
777428f2
FB		 899 /* 1.2 Mb 5"5 drive */
900 val = 2;
901 break;
2da44dd0 902 case FLOPPY_DRIVE_TYPE_NONE:
777428f2
FB		 903 default:
904 val = 0;
905 break;
906 }
907 return val;
908}
909
9139046c
MA		 910static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
911 int16_t cylinders, int8_t heads, int8_t sectors)
ba6c2377 912{
ba6c2377
FB		 913 rtc_set_memory(s, type_ofs, 47);
914 rtc_set_memory(s, info_ofs, cylinders);
915 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
916 rtc_set_memory(s, info_ofs + 2, heads);
917 rtc_set_memory(s, info_ofs + 3, 0xff);
918 rtc_set_memory(s, info_ofs + 4, 0xff);
919 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
920 rtc_set_memory(s, info_ofs + 6, cylinders);
921 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
922 rtc_set_memory(s, info_ofs + 8, sectors);
923}
924
6ac0e82d
AZ		 925/* convert boot_device letter to something recognizable by the bios */
926static int boot_device2nibble(char boot_device)
927{
928 switch(boot_device) {
929 case 'a':
930 case 'b':
931 return 0x01; /* floppy boot */
932 case 'c':
933 return 0x02; /* hard drive boot */
934 case 'd':
935 return 0x03; /* CD-ROM boot */
936 case 'n':
937 return 0x04; /* Network boot */
938 }
939 return 0;
940}
941
ddcd5531 942static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
0ecdffbb
AJ		 943{
944#define PC_MAX_BOOT_DEVICES 3
0ecdffbb
AJ		 945 int nbds, bds[3] = { 0, };
946 int i;
947
948 nbds = strlen(boot_device);
949 if (nbds > PC_MAX_BOOT_DEVICES) {
ddcd5531
GA		 950 error_setg(errp, "Too many boot devices for PC");
951 return;
0ecdffbb
AJ		 952 }
953 for (i = 0; i < nbds; i++) {
954 bds[i] = boot_device2nibble(boot_device[i]);
955 if (bds[i] == 0) {
ddcd5531
GA		 956 error_setg(errp, "Invalid boot device for PC: '%c'",
957 boot_device[i]);
958 return;
0ecdffbb
AJ		 959 }
960 }
961 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
d9346e81 962 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
0ecdffbb
AJ		 963}
964
ddcd5531 965static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
d9346e81 966{
ddcd5531 967 set_boot_dev(opaque, boot_device, errp);
d9346e81
MA		 968}
969
7444ca4e
LE		 970static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
971{
972 int val, nb, i;
2da44dd0
JS		 973 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
974 FLOPPY_DRIVE_TYPE_NONE };
7444ca4e
LE		 975
976 /* floppy type */
977 if (floppy) {
978 for (i = 0; i < 2; i++) {
979 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
980 }
981 }
982 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
983 cmos_get_fd_drive_type(fd_type[1]);
984 rtc_set_memory(rtc_state, 0x10, val);
985
986 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
987 nb = 0;
2da44dd0 988 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 989 nb++;
990 }
2da44dd0 991 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
7444ca4e
LE		 992 nb++;
993 }
994 switch (nb) {
995 case 0:
996 break;
997 case 1:
998 val |= 0x01; /* 1 drive, ready for boot */
999 break;
1000 case 2:
1001 val |= 0x41; /* 2 drives, ready for boot */
1002 break;
1003 }
1004 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
1005}
1006
c0897e0c
MA		 1007typedef struct pc_cmos_init_late_arg {
1008 ISADevice *rtc_state;
9139046c 1009 BusState *idebus[2];
c0897e0c
MA		 1010} pc_cmos_init_late_arg;
1011
b86f4613
LE		 1012typedef struct check_fdc_state {
1013 ISADevice *floppy;
1014 bool multiple;
1015} CheckFdcState;
1016
1017static int check_fdc(Object *obj, void *opaque)
1018{
1019 CheckFdcState *state = opaque;
1020 Object *fdc;
1021 uint32_t iobase;
1022 Error *local_err = NULL;
1023
1024 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
1025 if (!fdc) {
1026 return 0;
1027 }
1028
1ea1572a 1029 iobase = object_property_get_uint(obj, "iobase", &local_err);
b86f4613
LE		 1030 if (local_err || iobase != 0x3f0) {
1031 error_free(local_err);
1032 return 0;
1033 }
1034
1035 if (state->floppy) {
1036 state->multiple = true;
1037 } else {
1038 state->floppy = ISA_DEVICE(obj);
1039 }
1040 return 0;
1041}
1042
1043static const char * const fdc_container_path[] = {
1044 "/unattached", "/peripheral", "/peripheral-anon"
1045};
1046
424e4a87
RK		 1047/*
1048 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
1049 * and ACPI objects.
1050 */
1051ISADevice *pc_find_fdc0(void)
1052{
1053 int i;
1054 Object *container;
1055 CheckFdcState state = { 0 };
1056
1057 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
1058 container = container_get(qdev_get_machine(), fdc_container_path[i]);
1059 object_child_foreach(container, check_fdc, &state);
1060 }
1061
1062 if (state.multiple) {
3dc6f869
AF		 1063 warn_report("multiple floppy disk controllers with "
1064 "iobase=0x3f0 have been found");
433672b0 1065 error_printf("the one being picked for CMOS setup might not reflect "
9e5d2c52 1066 "your intent");
424e4a87
RK		 1067 }
1068
1069 return state.floppy;
1070}
1071
c0897e0c
MA		 1072static void pc_cmos_init_late(void *opaque)
1073{
1074 pc_cmos_init_late_arg *arg = opaque;
1075 ISADevice *s = arg->rtc_state;
9139046c
MA		 1076 int16_t cylinders;
1077 int8_t heads, sectors;
c0897e0c 1078 int val;
2adc99b2 1079 int i, trans;
c0897e0c 1080
9139046c 1081 val = 0;
272f0428
CP		 1082 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
1083 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 1084 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
1085 val |= 0xf0;
1086 }
272f0428
CP		 1087 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
1088 &cylinders, &heads, &sectors) >= 0) {
9139046c
MA		 1089 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
1090 val |= 0x0f;
1091 }
1092 rtc_set_memory(s, 0x12, val);
c0897e0c
MA		 1093
1094 val = 0;
1095 for (i = 0; i < 4; i++) {
9139046c
MA		 1096 /* NOTE: ide_get_geometry() returns the physical
1097 geometry. It is always such that: 1 <= sects <= 63, 1
1098 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
1099 geometry can be different if a translation is done. */
272f0428
CP		 1100 if (arg->idebus[i / 2] &&
1101 ide_get_geometry(arg->idebus[i / 2], i % 2,
9139046c 1102 &cylinders, &heads, &sectors) >= 0) {
2adc99b2
MA		 1103 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
1104 assert((trans & ~3) == 0);
1105 val |= trans << (i * 2);
c0897e0c
MA		 1106 }
1107 }
1108 rtc_set_memory(s, 0x39, val);
1109
424e4a87 1110 pc_cmos_init_floppy(s, pc_find_fdc0());
b86f4613 1111
c0897e0c
MA		 1112 qemu_unregister_reset(pc_cmos_init_late, opaque);
1113}
1114
23d30407 1115void pc_cmos_init(PCMachineState *pcms,
220a8846 1116 BusState *idebus0, BusState *idebus1,
63ffb564 1117 ISADevice *s)
80cabfad 1118{
7444ca4e 1119 int val;
c0897e0c 1120 static pc_cmos_init_late_arg arg;
b0a21b53 1121
b0a21b53 1122 /* various important CMOS locations needed by PC/Bochs bios */
80cabfad
FB		 1123
1124 /* memory size */
e89001f7 1125 /* base memory (first MiB) */
d471bf3e 1126 val = MIN(pcms->below_4g_mem_size / KiB, 640);
333190eb
FB		 1127 rtc_set_memory(s, 0x15, val);
1128 rtc_set_memory(s, 0x16, val >> 8);
e89001f7 1129 /* extended memory (next 64MiB) */
d471bf3e
PB		 1130 if (pcms->below_4g_mem_size > 1 * MiB) {
1131 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
e89001f7
MA		 1132 } else {
1133 val = 0;
1134 }
80cabfad
FB		 1135 if (val > 65535)
1136 val = 65535;
b0a21b53
FB		 1137 rtc_set_memory(s, 0x17, val);
1138 rtc_set_memory(s, 0x18, val >> 8);
1139 rtc_set_memory(s, 0x30, val);
1140 rtc_set_memory(s, 0x31, val >> 8);
e89001f7 1141 /* memory between 16MiB and 4GiB */
d471bf3e
PB		 1142 if (pcms->below_4g_mem_size > 16 * MiB) {
1143 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
e89001f7 1144 } else {
9da98861 1145 val = 0;
e89001f7 1146 }
80cabfad
FB		 1147 if (val > 65535)
1148 val = 65535;
b0a21b53
FB		 1149 rtc_set_memory(s, 0x34, val);
1150 rtc_set_memory(s, 0x35, val >> 8);
e89001f7 1151 /* memory above 4GiB */
88076854 1152 val = pcms->above_4g_mem_size / 65536;
e89001f7
MA		 1153 rtc_set_memory(s, 0x5b, val);
1154 rtc_set_memory(s, 0x5c, val >> 8);
1155 rtc_set_memory(s, 0x5d, val >> 16);
3b46e624 1156
23d30407 1157 object_property_add_link(OBJECT(pcms), "rtc_state",
2d996150 1158 TYPE_ISA_DEVICE,
ec68007a 1159 (Object **)&pcms->rtc,
2d996150 1160 object_property_allow_set_link,
265b578c 1161 OBJ_PROP_LINK_STRONG, &error_abort);
23d30407 1162 object_property_set_link(OBJECT(pcms), OBJECT(s),
2d996150 1163 "rtc_state", &error_abort);
298e01b6 1164
007b0657 1165 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
80cabfad 1166
b0a21b53 1167 val = 0;
b0a21b53
FB		 1168 val |= 0x02; /* FPU is there */
1169 val |= 0x04; /* PS/2 mouse installed */
1170 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
1171
b86f4613 1172 /* hard drives and FDC */
c0897e0c 1173 arg.rtc_state = s;
9139046c
MA		 1174 arg.idebus[0] = idebus0;
1175 arg.idebus[1] = idebus1;
c0897e0c 1176 qemu_register_reset(pc_cmos_init_late, &arg);
80cabfad
FB		 1177}
1178
a0881c64
AF		 1179#define TYPE_PORT92 "port92"
1180#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
1181
4b78a802
BS		 1182/* port 92 stuff: could be split off */
1183typedef struct Port92State {
a0881c64
AF		 1184 ISADevice parent_obj;
1185
23af670e 1186 MemoryRegion io;
4b78a802 1187 uint8_t outport;
d812b3d6 1188 qemu_irq a20_out;
4b78a802
BS		 1189} Port92State;
1190
93ef4192
AG		 1191static void port92_write(void *opaque, hwaddr addr, uint64_t val,
1192 unsigned size)
4b78a802
BS		 1193{
1194 Port92State *s = opaque;
4700a316 1195 int oldval = s->outport;
4b78a802 1196
c5539cb4 1197 DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
4b78a802 1198 s->outport = val;
d812b3d6 1199 qemu_set_irq(s->a20_out, (val >> 1) & 1);
4700a316 1200 if ((val & 1) && !(oldval & 1)) {
cf83f140 1201 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4b78a802
BS		 1202 }
1203}
1204
93ef4192
AG		 1205static uint64_t port92_read(void *opaque, hwaddr addr,
1206 unsigned size)
4b78a802
BS		 1207{
1208 Port92State *s = opaque;
1209 uint32_t ret;
1210
1211 ret = s->outport;
1212 DPRINTF("port92: read 0x%02x\n", ret);
1213 return ret;
1214}
1215
d80fe99d 1216static void port92_init(ISADevice *dev, qemu_irq a20_out)
4b78a802 1217{
d80fe99d 1218 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
4b78a802
BS		 1219}
1220
1221static const VMStateDescription vmstate_port92_isa = {
1222 .name = "port92",
1223 .version_id = 1,
1224 .minimum_version_id = 1,
d49805ae 1225 .fields = (VMStateField[]) {
4b78a802
BS		 1226 VMSTATE_UINT8(outport, Port92State),
1227 VMSTATE_END_OF_LIST()
1228 }
1229};
1230
1231static void port92_reset(DeviceState *d)
1232{
a0881c64 1233 Port92State *s = PORT92(d);
4b78a802
BS		 1234
1235 s->outport &= ~1;
1236}
1237
23af670e 1238static const MemoryRegionOps port92_ops = {
93ef4192
AG		 1239 .read = port92_read,
1240 .write = port92_write,
1241 .impl = {
1242 .min_access_size = 1,
1243 .max_access_size = 1,
1244 },
1245 .endianness = DEVICE_LITTLE_ENDIAN,
23af670e
RH		 1246};
1247
db895a1e 1248static void port92_initfn(Object *obj)
4b78a802 1249{
db895a1e 1250 Port92State *s = PORT92(obj);
4b78a802 1251
1437c94b 1252 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
23af670e 1253
4b78a802 1254 s->outport = 0;
d812b3d6
EV		 1255
1256 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
db895a1e
AF		 1257}
1258
1259static void port92_realizefn(DeviceState *dev, Error **errp)
1260{
1261 ISADevice *isadev = ISA_DEVICE(dev);
1262 Port92State *s = PORT92(dev);
1263
1264 isa_register_ioport(isadev, &s->io, 0x92);
4b78a802
BS		 1265}
1266
8f04ee08
AL		 1267static void port92_class_initfn(ObjectClass *klass, void *data)
1268{
39bffca2 1269 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e 1270
db895a1e 1271 dc->realize = port92_realizefn;
39bffca2
AL		 1272 dc->reset = port92_reset;
1273 dc->vmsd = &vmstate_port92_isa;
f3b17640
MA		 1274 /*
1275 * Reason: unlike ordinary ISA devices, this one needs additional
1276 * wiring: its A20 output line needs to be wired up by
1277 * port92_init().
1278 */
e90f2a8c 1279 dc->user_creatable = false;
8f04ee08
AL		 1280}
1281
8c43a6f0 1282static const TypeInfo port92_info = {
a0881c64 1283 .name = TYPE_PORT92,
39bffca2
AL		 1284 .parent = TYPE_ISA_DEVICE,
1285 .instance_size = sizeof(Port92State),
db895a1e 1286 .instance_init = port92_initfn,
39bffca2 1287 .class_init = port92_class_initfn,
4b78a802
BS		 1288};
1289
83f7d43a 1290static void port92_register_types(void)
4b78a802 1291{
39bffca2 1292 type_register_static(&port92_info);
4b78a802 1293}
83f7d43a
AF		 1294
1295type_init(port92_register_types)
4b78a802 1296
956a3e6b 1297static void handle_a20_line_change(void *opaque, int irq, int level)
59b8ad81 1298{
cc36a7a2 1299 X86CPU *cpu = opaque;
e1a23744 1300
956a3e6b 1301 /* XXX: send to all CPUs ? */
4b78a802 1302 /* XXX: add logic to handle multiple A20 line sources */
cc36a7a2 1303 x86_cpu_set_a20(cpu, level);
e1a23744
FB		 1304}
1305
4c5b10b7
JS		 1306int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
1307{
7d67110f 1308 int index = le32_to_cpu(e820_reserve.count);
4c5b10b7
JS		 1309 struct e820_entry *entry;
1310
7d67110f
GH		 1311 if (type != E820_RAM) {
1312 /* old FW_CFG_E820_TABLE entry -- reservations only */
1313 if (index >= E820_NR_ENTRIES) {
1314 return -EBUSY;
1315 }
1316 entry = &e820_reserve.entry[index++];
1317
1318 entry->address = cpu_to_le64(address);
1319 entry->length = cpu_to_le64(length);
1320 entry->type = cpu_to_le32(type);
1321
1322 e820_reserve.count = cpu_to_le32(index);
1323 }
4c5b10b7 1324
7d67110f 1325 /* new "etc/e820" file -- include ram too */
ab3ad07f 1326 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
7d67110f
GH		 1327 e820_table[e820_entries].address = cpu_to_le64(address);
1328 e820_table[e820_entries].length = cpu_to_le64(length);
1329 e820_table[e820_entries].type = cpu_to_le32(type);
1330 e820_entries++;
4c5b10b7 1331
7d67110f 1332 return e820_entries;
4c5b10b7
JS		 1333}
1334
7bf8ef19
GS		 1335int e820_get_num_entries(void)
1336{
1337 return e820_entries;
1338}
1339
1340bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
1341{
1342 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
1343 *address = le64_to_cpu(e820_table[idx].address);
1344 *length = le64_to_cpu(e820_table[idx].length);
1345 return true;
1346 }
1347 return false;
1348}
1349
54a40293
EH		 1350/* Enables contiguous-apic-ID mode, for compatibility */
1351static bool compat_apic_id_mode;
1352
1353void enable_compat_apic_id_mode(void)
1354{
1355 compat_apic_id_mode = true;
1356}
1357
1358/* Calculates initial APIC ID for a specific CPU index
1359 *
1360 * Currently we need to be able to calculate the APIC ID from the CPU index
1361 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
1362 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
1363 * all CPUs up to max_cpus.
1364 */
1365static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
1366{
1367 uint32_t correct_id;
1368 static bool warned;
1369
1370 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
1371 if (compat_apic_id_mode) {
b1c12027 1372 if (cpu_index != correct_id && !warned && !qtest_enabled()) {
54a40293
EH		 1373 error_report("APIC IDs set in compatibility mode, "
1374 "CPU topology won't match the configuration");
1375 warned = true;
1376 }
1377 return cpu_index;
1378 } else {
1379 return correct_id;
1380 }
1381}
1382
f2098f48 1383static void pc_build_smbios(PCMachineState *pcms)
80cabfad 1384{
c97294ec
GS		 1385 uint8_t *smbios_tables, *smbios_anchor;
1386 size_t smbios_tables_len, smbios_anchor_len;
89cc4a27
WH		 1387 struct smbios_phys_mem_area *mem_array;
1388 unsigned i, array_count;
38690a1c
IM		 1389 MachineState *ms = MACHINE(pcms);
1390 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
f2098f48
IM		 1391
1392 /* tell smbios about cpuid version and features */
1393 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
5fd0a9d4
WH		 1394
1395 smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
1396 if (smbios_tables) {
f2098f48 1397 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
5fd0a9d4
WH		 1398 smbios_tables, smbios_tables_len);
1399 }
1400
89cc4a27
WH		 1401 /* build the array of physical mem area from e820 table */
1402 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
1403 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
1404 uint64_t addr, len;
1405
1406 if (e820_get_entry(i, E820_RAM, &addr, &len)) {
1407 mem_array[array_count].address = addr;
1408 mem_array[array_count].length = len;
1409 array_count++;
1410 }
1411 }
1412 smbios_get_tables(mem_array, array_count,
1413 &smbios_tables, &smbios_tables_len,
5fd0a9d4 1414 &smbios_anchor, &smbios_anchor_len);
89cc4a27
WH		 1415 g_free(mem_array);
1416
5fd0a9d4 1417 if (smbios_anchor) {
f2098f48 1418 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
5fd0a9d4 1419 smbios_tables, smbios_tables_len);
f2098f48 1420 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
5fd0a9d4
WH		 1421 smbios_anchor, smbios_anchor_len);
1422 }
1423}
1424
ebde2465 1425static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
5fd0a9d4
WH		 1426{
1427 FWCfgState *fw_cfg;
11c2fd3e 1428 uint64_t *numa_fw_cfg;
ea265072
IM		 1429 int i;
1430 const CPUArchIdList *cpus;
1431 MachineClass *mc = MACHINE_GET_CLASS(pcms);
3cce6243 1432
305ae888 1433 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
e3cadac0 1434 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
c886fc4c 1435
1d934e89
EH		 1436 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
1437 *
a3abd0f2
IM		 1438 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
1439 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
1440 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
1441 * for CPU hotplug also uses APIC ID and not "CPU index".
1442 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
1443 * but the "limit to the APIC ID values SeaBIOS may see".
1d934e89 1444 *
a3abd0f2
IM		 1445 * So for compatibility reasons with old BIOSes we are stuck with
1446 * "etc/max-cpus" actually being apic_id_limit
1d934e89 1447 */
ebde2465 1448 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit);
905fdcb5 1449 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
089da572
MA		 1450 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
1451 acpi_tables, acpi_tables_len);
9b5b76d4 1452 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
b6f6e3d3 1453
089da572 1454 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
7d67110f
GH		 1455 &e820_reserve, sizeof(e820_reserve));
1456 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
1457 sizeof(struct e820_entry) * e820_entries);
11c2fd3e 1458
089da572 1459 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
11c2fd3e
AL		 1460 /* allocate memory for the NUMA channel: one (64bit) word for the number
1461 * of nodes, one word for each VCPU->node and one word for each node to
1462 * hold the amount of memory.
1463 */
ebde2465 1464 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes);
11c2fd3e 1465 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
ea265072
IM		 1466 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms));
1467 for (i = 0; i < cpus->len; i++) {
1468 unsigned int apic_id = cpus->cpus[i].arch_id;
ebde2465 1469 assert(apic_id < pcms->apic_id_limit);
d41f3e75 1470 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
11c2fd3e
AL		 1471 }
1472 for (i = 0; i < nb_numa_nodes; i++) {
ebde2465
IM		 1473 numa_fw_cfg[pcms->apic_id_limit + 1 + i] =
1474 cpu_to_le64(numa_info[i].node_mem);
11c2fd3e 1475 }
089da572 1476 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
ebde2465 1477 (1 + pcms->apic_id_limit + nb_numa_nodes) *
1d934e89 1478 sizeof(*numa_fw_cfg));
bf483392
AG		 1479
1480 return fw_cfg;
80cabfad
FB		 1481}
1482
642a4f96
TS		 1483static long get_file_size(FILE *f)
1484{
1485 long where, size;
1486
1487 /* XXX: on Unix systems, using fstat() probably makes more sense */
1488
1489 where = ftell(f);
1490 fseek(f, 0, SEEK_END);
1491 size = ftell(f);
1492 fseek(f, where, SEEK_SET);
1493
1494 return size;
1495}
1496
3cbeb524
AB		 1497/* setup_data types */
1498#define SETUP_NONE 0
1499#define SETUP_E820_EXT 1
1500#define SETUP_DTB 2
1501#define SETUP_PCI 3
1502#define SETUP_EFI 4
1503
1504struct setup_data {
1505 uint64_t next;
1506 uint32_t type;
1507 uint32_t len;
1508 uint8_t data[0];
1509} __attribute__((packed));
1510
df1f79fd
EH		 1511static void load_linux(PCMachineState *pcms,
1512 FWCfgState *fw_cfg)
642a4f96
TS		 1513{
1514 uint16_t protocol;
f3839fda 1515 int setup_size, kernel_size, cmdline_size;
3cbeb524 1516 int dtb_size, setup_data_offset;
642a4f96 1517 uint32_t initrd_max;
c24323dd 1518 uint8_t header[8192], *setup, *kernel;
a8170e5e 1519 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
45a50b16 1520 FILE *f;
bf4e5d92 1521 char *vmode;
df1f79fd 1522 MachineState *machine = MACHINE(pcms);
cd4040ec 1523 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
3cbeb524 1524 struct setup_data *setup_data;
df1f79fd
EH		 1525 const char *kernel_filename = machine->kernel_filename;
1526 const char *initrd_filename = machine->initrd_filename;
3cbeb524 1527 const char *dtb_filename = machine->dtb;
df1f79fd 1528 const char *kernel_cmdline = machine->kernel_cmdline;
642a4f96
TS		 1529
1530 /* Align to 16 bytes as a paranoia measure */
1531 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
1532
1533 /* load the kernel header */
1534 f = fopen(kernel_filename, "rb");
1535 if (!f || !(kernel_size = get_file_size(f)) ||
0f9d76e5
LG		 1536 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
1537 MIN(ARRAY_SIZE(header), kernel_size)) {
1538 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
1539 kernel_filename, strerror(errno));
1540 exit(1);
642a4f96
TS		 1541 }
1542
1543 /* kernel protocol version */
bc4edd79 1544#if 0
642a4f96 1545 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
bc4edd79 1546#endif
0f9d76e5
LG		 1547 if (ldl_p(header+0x202) == 0x53726448) {
1548 protocol = lduw_p(header+0x206);
1549 } else {
1550 /* This looks like a multiboot kernel. If it is, let's stop
1551 treating it like a Linux kernel. */
52001445 1552 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
0f9d76e5 1553 kernel_cmdline, kernel_size, header)) {
82663ee2 1554 return;
0f9d76e5
LG		 1555 }
1556 protocol = 0;
f16408df 1557 }
642a4f96
TS		 1558
1559 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
0f9d76e5
LG		 1560 /* Low kernel */
1561 real_addr = 0x90000;
1562 cmdline_addr = 0x9a000 - cmdline_size;
1563 prot_addr = 0x10000;
642a4f96 1564 } else if (protocol < 0x202) {
0f9d76e5
LG		 1565 /* High but ancient kernel */
1566 real_addr = 0x90000;
1567 cmdline_addr = 0x9a000 - cmdline_size;
1568 prot_addr = 0x100000;
642a4f96 1569 } else {
0f9d76e5
LG		 1570 /* High and recent kernel */
1571 real_addr = 0x10000;
1572 cmdline_addr = 0x20000;
1573 prot_addr = 0x100000;
642a4f96
TS		 1574 }
1575
bc4edd79 1576#if 0
642a4f96 1577 fprintf(stderr,
0f9d76e5
LG		 1578 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
1579 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
1580 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
1581 real_addr,
1582 cmdline_addr,
1583 prot_addr);
bc4edd79 1584#endif
642a4f96
TS		 1585
1586 /* highest address for loading the initrd */
0f9d76e5
LG		 1587 if (protocol >= 0x203) {
1588 initrd_max = ldl_p(header+0x22c);
1589 } else {
1590 initrd_max = 0x37ffffff;
1591 }
642a4f96 1592
cd4040ec
EH		 1593 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) {
1594 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1;
927766c7 1595 }
642a4f96 1596
57a46d05
AG		 1597 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
1598 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
96f80586 1599 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
642a4f96
TS		 1600
1601 if (protocol >= 0x202) {
0f9d76e5 1602 stl_p(header+0x228, cmdline_addr);
642a4f96 1603 } else {
0f9d76e5
LG		 1604 stw_p(header+0x20, 0xA33F);
1605 stw_p(header+0x22, cmdline_addr-real_addr);
642a4f96
TS		 1606 }
1607
bf4e5d92
PT		 1608 /* handle vga= parameter */
1609 vmode = strstr(kernel_cmdline, "vga=");
1610 if (vmode) {
1611 unsigned int video_mode;
1612 /* skip "vga=" */
1613 vmode += 4;
1614 if (!strncmp(vmode, "normal", 6)) {
1615 video_mode = 0xffff;
1616 } else if (!strncmp(vmode, "ext", 3)) {
1617 video_mode = 0xfffe;
1618 } else if (!strncmp(vmode, "ask", 3)) {
1619 video_mode = 0xfffd;
1620 } else {
1621 video_mode = strtol(vmode, NULL, 0);
1622 }
1623 stw_p(header+0x1fa, video_mode);
1624 }
1625
642a4f96 1626 /* loader type */
5cbdb3a3 1627 /* High nybble = B reserved for QEMU; low nybble is revision number.
642a4f96
TS		 1628 If this code is substantially changed, you may want to consider
1629 incrementing the revision. */
0f9d76e5
LG		 1630 if (protocol >= 0x200) {
1631 header[0x210] = 0xB0;
1632 }
642a4f96
TS		 1633 /* heap */
1634 if (protocol >= 0x201) {
0f9d76e5
LG		 1635 header[0x211] |= 0x80; /* CAN_USE_HEAP */
1636 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
642a4f96
TS		 1637 }
1638
1639 /* load initrd */
1640 if (initrd_filename) {
c24323dd
PM		 1641 gsize initrd_size;
1642 gchar *initrd_data;
1643 GError *gerr = NULL;
1644
0f9d76e5
LG		 1645 if (protocol < 0x200) {
1646 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
1647 exit(1);
1648 }
642a4f96 1649
c24323dd
PM		 1650 if (!g_file_get_contents(initrd_filename, &initrd_data,
1651 &initrd_size, &gerr)) {
7454e51d 1652 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
c24323dd 1653 initrd_filename, gerr->message);
d6fa4b77 1654 exit(1);
c24323dd
PM		 1655 }
1656 if (initrd_size >= initrd_max) {
f3839fda 1657 fprintf(stderr, "qemu: initrd is too large, cannot support."
c24323dd
PM		 1658 "(max: %"PRIu32", need %"PRId64")\n",
1659 initrd_max, (uint64_t)initrd_size);
f3839fda 1660 exit(1);
d6fa4b77
MK		 1661 }
1662
45a50b16 1663 initrd_addr = (initrd_max-initrd_size) & ~4095;
57a46d05 1664
57a46d05
AG		 1665 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
1666 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1667 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
642a4f96 1668
0f9d76e5
LG		 1669 stl_p(header+0x218, initrd_addr);
1670 stl_p(header+0x21c, initrd_size);
642a4f96
TS		 1671 }
1672
45a50b16 1673 /* load kernel and setup */
642a4f96 1674 setup_size = header[0x1f1];
0f9d76e5
LG		 1675 if (setup_size == 0) {
1676 setup_size = 4;
1677 }
642a4f96 1678 setup_size = (setup_size+1)*512;
ec5fd402
PB		 1679 if (setup_size > kernel_size) {
1680 fprintf(stderr, "qemu: invalid kernel header\n");
1681 exit(1);
1682 }
45a50b16 1683 kernel_size -= setup_size;
642a4f96 1684
7267c094
AL		 1685 setup = g_malloc(setup_size);
1686 kernel = g_malloc(kernel_size);
45a50b16 1687 fseek(f, 0, SEEK_SET);
5a41ecc5
KS		 1688 if (fread(setup, 1, setup_size, f) != setup_size) {
1689 fprintf(stderr, "fread() failed\n");
1690 exit(1);
1691 }
1692 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
1693 fprintf(stderr, "fread() failed\n");
1694 exit(1);
1695 }
642a4f96 1696 fclose(f);
3cbeb524
AB		 1697
1698 /* append dtb to kernel */
1699 if (dtb_filename) {
1700 if (protocol < 0x209) {
1701 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n");
1702 exit(1);
1703 }
1704
1705 dtb_size = get_image_size(dtb_filename);
1706 if (dtb_size <= 0) {
1707 fprintf(stderr, "qemu: error reading dtb %s: %s\n",
1708 dtb_filename, strerror(errno));
1709 exit(1);
1710 }
1711
1712 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16);
1713 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size;
1714 kernel = g_realloc(kernel, kernel_size);
1715
1716 stq_p(header+0x250, prot_addr + setup_data_offset);
1717
1718 setup_data = (struct setup_data *)(kernel + setup_data_offset);
1719 setup_data->next = 0;
1720 setup_data->type = cpu_to_le32(SETUP_DTB);
1721 setup_data->len = cpu_to_le32(dtb_size);
1722
1723 load_image_size(dtb_filename, setup_data->data, dtb_size);
1724 }
1725
45a50b16 1726 memcpy(setup, header, MIN(sizeof(header), setup_size));
57a46d05
AG		 1727
1728 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
1729 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1730 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1731
1732 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
1733 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
1734 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1735
98e753a6
IM		 1736 option_rom[nb_option_roms].bootindex = 0;
1737 option_rom[nb_option_roms].name = "linuxboot.bin";
1738 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) {
b2a575a1 1739 option_rom[nb_option_roms].name = "linuxboot_dma.bin";
b2a575a1 1740 }
57a46d05 1741 nb_option_roms++;
642a4f96
TS		 1742}
1743
b41a2cd1
FB		 1744#define NE2000_NB_MAX 6
1745
675d6f82
BS		 1746static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1747 0x280, 0x380 };
1748static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
b41a2cd1 1749
48a18b3c 1750void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
a41b2ff2
PB		 1751{
1752 static int nb_ne2k = 0;
1753
1754 if (nb_ne2k == NE2000_NB_MAX)
1755 return;
48a18b3c 1756 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
9453c5bc 1757 ne2000_irq[nb_ne2k], nd);
a41b2ff2
PB		 1758 nb_ne2k++;
1759}
1760
92a16d7a 1761DeviceState *cpu_get_current_apic(void)
0e26b7b8 1762{
4917cf44
AF		 1763 if (current_cpu) {
1764 X86CPU *cpu = X86_CPU(current_cpu);
02e51483 1765 return cpu->apic_state;
0e26b7b8
BS		 1766 } else {
1767 return NULL;
1768 }
1769}
1770
845773ab 1771void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
53b67b30 1772{
c3affe56 1773 X86CPU *cpu = opaque;
53b67b30
BS		 1774
1775 if (level) {
c3affe56 1776 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
53b67b30
BS		 1777 }
1778}
1779
074281d6 1780static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp)
31050930 1781{
074281d6 1782 Object *cpu = NULL;
31050930
IM		 1783 Error *local_err = NULL;
1784
074281d6 1785 cpu = object_new(typename);
31050930 1786
c7b4efb4 1787 object_property_set_uint(cpu, apic_id, "apic-id", &local_err);
074281d6 1788 object_property_set_bool(cpu, true, "realized", &local_err);
31050930 1789
074281d6 1790 object_unref(cpu);
021c9d25 1791 error_propagate(errp, local_err);
31050930
IM		 1792}
1793
c649983b
IM		 1794void pc_hot_add_cpu(const int64_t id, Error **errp)
1795{
38690a1c 1796 MachineState *ms = MACHINE(qdev_get_machine());
c649983b 1797 int64_t apic_id = x86_cpu_apic_id_from_index(id);
0e3bd562 1798 Error *local_err = NULL;
c649983b 1799
8de433cb
IM		 1800 if (id < 0) {
1801 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
1802 return;
1803 }
1804
5ff020b7
EH		 1805 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
1806 error_setg(errp, "Unable to add CPU: %" PRIi64
1807 ", resulting APIC ID (%" PRIi64 ") is too large",
1808 id, apic_id);
1809 return;
1810 }
1811
311ca98d 1812 pc_new_cpu(ms->cpu_type, apic_id, &local_err);
0e3bd562
AF		 1813 if (local_err) {
1814 error_propagate(errp, local_err);
1815 return;
1816 }
c649983b
IM		 1817}
1818
4884b7bf 1819void pc_cpus_init(PCMachineState *pcms)
70166477
IY		 1820{
1821 int i;
c96a1c0b 1822 const CPUArchIdList *possible_cpus;
311ca98d 1823 MachineState *ms = MACHINE(pcms);
c96a1c0b 1824 MachineClass *mc = MACHINE_GET_CLASS(pcms);
70166477 1825
ebde2465
IM		 1826 /* Calculates the limit to CPU APIC ID values
1827 *
1828 * Limit for the APIC ID value, so that all
1829 * CPU APIC IDs are < pcms->apic_id_limit.
1830 *
1831 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
1832 */
1833 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
311ca98d 1834 possible_cpus = mc->possible_cpu_arch_ids(ms);
c96a1c0b 1835 for (i = 0; i < smp_cpus; i++) {
d342eb76
IM		 1836 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id,
1837 &error_fatal);
70166477
IY		 1838 }
1839}
1840
217f1b4a
HZ		 1841static void pc_build_feature_control_file(PCMachineState *pcms)
1842{
38690a1c
IM		 1843 MachineState *ms = MACHINE(pcms);
1844 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
217f1b4a
HZ		 1845 CPUX86State *env = &cpu->env;
1846 uint32_t unused, ecx, edx;
1847 uint64_t feature_control_bits = 0;
1848 uint64_t *val;
1849
1850 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
1851 if (ecx & CPUID_EXT_VMX) {
1852 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1853 }
1854
1855 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
1856 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
1857 (env->mcg_cap & MCG_LMCE_P)) {
1858 feature_control_bits |= FEATURE_CONTROL_LMCE;
1859 }
1860
1861 if (!feature_control_bits) {
1862 return;
1863 }
1864
1865 val = g_malloc(sizeof(*val));
1866 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
1867 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
1868}
1869
e3cadac0
IM		 1870static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
1871{
1872 if (cpus_count > 0xff) {
1873 /* If the number of CPUs can't be represented in 8 bits, the
1874 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
1875 * to make old BIOSes fail more predictably.
1876 */
1877 rtc_set_memory(rtc, 0x5f, 0);
1878 } else {
1879 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
1880 }
1881}
1882
3459a625 1883static
9ebeed0c 1884void pc_machine_done(Notifier *notifier, void *data)
3459a625 1885{
9ebeed0c
EH		 1886 PCMachineState *pcms = container_of(notifier,
1887 PCMachineState, machine_done);
1888 PCIBus *bus = pcms->bus;
2118196b 1889
ba157b69 1890 /* set the number of CPUs */
e3cadac0 1891 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
ba157b69 1892
2118196b
MA		 1893 if (bus) {
1894 int extra_hosts = 0;
1895
1896 QLIST_FOREACH(bus, &bus->child, sibling) {
1897 /* look for expander root buses */
1898 if (pci_bus_is_root(bus)) {
1899 extra_hosts++;
1900 }
1901 }
f264d360 1902 if (extra_hosts && pcms->fw_cfg) {
2118196b
MA		 1903 uint64_t *val = g_malloc(sizeof(*val));
1904 *val = cpu_to_le64(extra_hosts);
f264d360 1905 fw_cfg_add_file(pcms->fw_cfg,
2118196b
MA		 1906 "etc/extra-pci-roots", val, sizeof(*val));
1907 }
1908 }
1909
bb292f5a 1910 acpi_setup();
6d42eefa 1911 if (pcms->fw_cfg) {
f2098f48 1912 pc_build_smbios(pcms);
217f1b4a 1913 pc_build_feature_control_file(pcms);
e3cadac0
IM		 1914 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
1915 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
6d42eefa 1916 }
60c5e104 1917
1a26f466 1918 if (pcms->apic_id_limit > 255 && !xen_enabled()) {
60c5e104
IM		 1919 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
1920
a924b3d8 1921 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
60c5e104
IM		 1922 iommu->intr_eim != ON_OFF_AUTO_ON) {
1923 error_report("current -smp configuration requires "
1924 "Extended Interrupt Mode enabled. "
1925 "You can add an IOMMU using: "
1926 "-device intel-iommu,intremap=on,eim=on");
1927 exit(EXIT_FAILURE);
1928 }
1929 }
3459a625
MT		 1930}
1931
e4e8ba04 1932void pc_guest_info_init(PCMachineState *pcms)
3459a625 1933{
1f3aba37 1934 int i;
b20c9bd5 1935
dd4c2f01
EH		 1936 pcms->apic_xrupt_override = kvm_allows_irq0_override();
1937 pcms->numa_nodes = nb_numa_nodes;
1938 pcms->node_mem = g_malloc0(pcms->numa_nodes *
1939 sizeof *pcms->node_mem);
8c85901e 1940 for (i = 0; i < nb_numa_nodes; i++) {
dd4c2f01 1941 pcms->node_mem[i] = numa_info[i].node_mem;
8c85901e
WG		 1942 }
1943
9ebeed0c
EH		 1944 pcms->machine_done.notify = pc_machine_done;
1945 qemu_add_machine_init_done_notifier(&pcms->machine_done);
3459a625
MT		 1946}
1947
83d08f26
MT		 1948/* setup pci memory address space mapping into system address space */
1949void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1950 MemoryRegion *pci_address_space)
39848901 1951{
83d08f26
MT		 1952 /* Set to lower priority than RAM */
1953 memory_region_add_subregion_overlap(system_memory, 0x0,
1954 pci_address_space, -1);
39848901
IM		 1955}
1956
f7e4dd6c
GH		 1957void pc_acpi_init(const char *default_dsdt)
1958{
c5a98cf3 1959 char *filename;
f7e4dd6c
GH		 1960
1961 if (acpi_tables != NULL) {
1962 /* manually set via -acpitable, leave it alone */
1963 return;
1964 }
1965
1966 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1967 if (filename == NULL) {
2ab4b135 1968 warn_report("failed to find %s", default_dsdt);
c5a98cf3 1969 } else {
5bdb59a2
MA		 1970 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0,
1971 &error_abort);
c5a98cf3 1972 Error *err = NULL;
f7e4dd6c 1973
5bdb59a2 1974 qemu_opt_set(opts, "file", filename, &error_abort);
0c764a9d 1975
1a4b2666 1976 acpi_table_add_builtin(opts, &err);
c5a98cf3 1977 if (err) {
88f83f35 1978 warn_reportf_err(err, "failed to load %s: ", filename);
c5a98cf3 1979 }
c5a98cf3 1980 g_free(filename);
f7e4dd6c 1981 }
f7e4dd6c
GH		 1982}
1983
7bc35e0f 1984void xen_load_linux(PCMachineState *pcms)
b33a5bbf
CL		 1985{
1986 int i;
1987 FWCfgState *fw_cfg;
1988
df1f79fd 1989 assert(MACHINE(pcms)->kernel_filename != NULL);
b33a5bbf 1990
305ae888 1991 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
e3cadac0 1992 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
b33a5bbf
CL		 1993 rom_set_fw(fw_cfg);
1994
df1f79fd 1995 load_linux(pcms, fw_cfg);
b33a5bbf
CL		 1996 for (i = 0; i < nb_option_roms; i++) {
1997 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
b2a575a1 1998 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
b33a5bbf
CL		 1999 !strcmp(option_rom[i].name, "multiboot.bin"));
2000 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
2001 }
f264d360 2002 pcms->fw_cfg = fw_cfg;
b33a5bbf
CL		 2003}
2004
5934e216
EH		 2005void pc_memory_init(PCMachineState *pcms,
2006 MemoryRegion *system_memory,
2007 MemoryRegion *rom_memory,
2008 MemoryRegion **ram_memory)
80cabfad 2009{
cbc5b5f3
JJ		 2010 int linux_boot, i;
2011 MemoryRegion *ram, *option_rom_mr;
00cb2a99 2012 MemoryRegion *ram_below_4g, *ram_above_4g;
a88b362c 2013 FWCfgState *fw_cfg;
62b160c0 2014 MachineState *machine = MACHINE(pcms);
16a9e8a5 2015 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d592d303 2016
c8d163bc
EH		 2017 assert(machine->ram_size == pcms->below_4g_mem_size +
2018 pcms->above_4g_mem_size);
9521d42b
PB		 2019
2020 linux_boot = (machine->kernel_filename != NULL);
80cabfad 2021
00cb2a99 2022 /* Allocate RAM. We allocate it as a single memory region and use
66a0a2cb 2023 * aliases to address portions of it, mostly for backwards compatibility
00cb2a99
AK		 2024 * with older qemus that used qemu_ram_alloc().
2025 */
7267c094 2026 ram = g_malloc(sizeof(*ram));
9521d42b
PB		 2027 memory_region_allocate_system_memory(ram, NULL, "pc.ram",
2028 machine->ram_size);
ae0a5466 2029 *ram_memory = ram;
7267c094 2030 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
2c9b15ca 2031 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
c8d163bc 2032 0, pcms->below_4g_mem_size);
00cb2a99 2033 memory_region_add_subregion(system_memory, 0, ram_below_4g);
c8d163bc
EH		 2034 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM);
2035 if (pcms->above_4g_mem_size > 0) {
7267c094 2036 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
2c9b15ca 2037 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
c8d163bc
EH		 2038 pcms->below_4g_mem_size,
2039 pcms->above_4g_mem_size);
00cb2a99
AK		 2040 memory_region_add_subregion(system_memory, 0x100000000ULL,
2041 ram_above_4g);
c8d163bc 2042 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM);
bbe80adf 2043 }
82b36dc3 2044
bb292f5a 2045 if (!pcmc->has_reserved_memory &&
ca8336f3 2046 (machine->ram_slots ||
9521d42b 2047 (machine->maxram_size > machine->ram_size))) {
ca8336f3
IM		 2048 MachineClass *mc = MACHINE_GET_CLASS(machine);
2049
2050 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
2051 mc->name);
2052 exit(EXIT_FAILURE);
2053 }
2054
b0c14ec4
DH		 2055 /* always allocate the device memory information */
2056 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2057
f2ffbe2b 2058 /* initialize device memory address space */
bb292f5a 2059 if (pcmc->has_reserved_memory &&
9521d42b 2060 (machine->ram_size < machine->maxram_size)) {
f2ffbe2b 2061 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
619d11e4 2062
a0cc8856
IM		 2063 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
2064 error_report("unsupported amount of memory slots: %"PRIu64,
2065 machine->ram_slots);
2066 exit(EXIT_FAILURE);
2067 }
2068
f2c38522
PK		 2069 if (QEMU_ALIGN_UP(machine->maxram_size,
2070 TARGET_PAGE_SIZE) != machine->maxram_size) {
2071 error_report("maximum memory size must by aligned to multiple of "
2072 "%d bytes", TARGET_PAGE_SIZE);
2073 exit(EXIT_FAILURE);
2074 }
2075
b0c14ec4 2076 machine->device_memory->base =
d471bf3e 2077 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB);
619d11e4 2078
16a9e8a5 2079 if (pcmc->enforce_aligned_dimm) {
f2ffbe2b 2080 /* size device region assuming 1G page max alignment per slot */
d471bf3e 2081 device_mem_size += (1 * GiB) * machine->ram_slots;
085f8e88
IM		 2082 }
2083
f2ffbe2b
DH		 2084 if ((machine->device_memory->base + device_mem_size) <
2085 device_mem_size) {
619d11e4
IM		 2086 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
2087 machine->maxram_size);
2088 exit(EXIT_FAILURE);
2089 }
2090
b0c14ec4 2091 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
f2ffbe2b 2092 "device-memory", device_mem_size);
b0c14ec4
DH		 2093 memory_region_add_subregion(system_memory, machine->device_memory->base,
2094 &machine->device_memory->mr);
619d11e4 2095 }
cbc5b5f3
JJ		 2096
2097 /* Initialize PC system firmware */
5db3f0de 2098 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled);
00cb2a99 2099
7267c094 2100 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
98a99ce0 2101 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
f8ed85ac 2102 &error_fatal);
208fa0e4
IM		 2103 if (pcmc->pci_enabled) {
2104 memory_region_set_readonly(option_rom_mr, true);
2105 }
4463aee6 2106 memory_region_add_subregion_overlap(rom_memory,
00cb2a99
AK		 2107 PC_ROM_MIN_VGA,
2108 option_rom_mr,
2109 1);
f753ff16 2110
ebde2465 2111 fw_cfg = bochs_bios_init(&address_space_memory, pcms);
c886fc4c 2112
8832cb80 2113 rom_set_fw(fw_cfg);
1d108d97 2114
b0c14ec4 2115 if (pcmc->has_reserved_memory && machine->device_memory->base) {
de268e13 2116 uint64_t *val = g_malloc(sizeof(*val));
2f8b5008 2117 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 2118 uint64_t res_mem_end = machine->device_memory->base;
2f8b5008
IM		 2119
2120 if (!pcmc->broken_reserved_end) {
b0c14ec4 2121 res_mem_end += memory_region_size(&machine->device_memory->mr);
2f8b5008 2122 }
d471bf3e 2123 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
de268e13
IM		 2124 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
2125 }
2126
f753ff16 2127 if (linux_boot) {
df1f79fd 2128 load_linux(pcms, fw_cfg);
f753ff16
PB		 2129 }
2130
2131 for (i = 0; i < nb_option_roms; i++) {
2e55e842 2132 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
406c8df3 2133 }
f264d360 2134 pcms->fw_cfg = fw_cfg;
cb135f59
PX		 2135
2136 /* Init default IOAPIC address space */
2137 pcms->ioapic_as = &address_space_memory;
3d53f5c3
IY		 2138}
2139
9fa99d25
MA		 2140/*
2141 * The 64bit pci hole starts after "above 4G RAM" and
2142 * potentially the space reserved for memory hotplug.
2143 */
2144uint64_t pc_pci_hole64_start(void)
2145{
2146 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2147 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
b0c14ec4 2148 MachineState *ms = MACHINE(pcms);
9fa99d25
MA		 2149 uint64_t hole64_start = 0;
2150
b0c14ec4
DH		 2151 if (pcmc->has_reserved_memory && ms->device_memory->base) {
2152 hole64_start = ms->device_memory->base;
9fa99d25 2153 if (!pcmc->broken_reserved_end) {
b0c14ec4 2154 hole64_start += memory_region_size(&ms->device_memory->mr);
9fa99d25
MA		 2155 }
2156 } else {
2157 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
2158 }
2159
d471bf3e 2160 return ROUND_UP(hole64_start, 1 * GiB);
9fa99d25
MA		 2161}
2162
0b0cc076 2163qemu_irq pc_allocate_cpu_irq(void)
845773ab 2164{
0b0cc076 2165 return qemu_allocate_irq(pic_irq_request, NULL, 0);
845773ab
IY		 2166}
2167
48a18b3c 2168DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
765d7908 2169{
ad6d45fa
AL		 2170 DeviceState *dev = NULL;
2171
bab47d9a 2172 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
16094b75
AJ		 2173 if (pci_bus) {
2174 PCIDevice *pcidev = pci_vga_init(pci_bus);
2175 dev = pcidev ? &pcidev->qdev : NULL;
2176 } else if (isa_bus) {
2177 ISADevice *isadev = isa_vga_init(isa_bus);
4a17cc4f 2178 dev = isadev ? DEVICE(isadev) : NULL;
765d7908 2179 }
bab47d9a 2180 rom_reset_order_override();
ad6d45fa 2181 return dev;
765d7908
IY		 2182}
2183
258711c6
JG		 2184static const MemoryRegionOps ioport80_io_ops = {
2185 .write = ioport80_write,
c02e1eac 2186 .read = ioport80_read,
258711c6
JG		 2187 .endianness = DEVICE_NATIVE_ENDIAN,
2188 .impl = {
2189 .min_access_size = 1,
2190 .max_access_size = 1,
2191 },
2192};
2193
2194static const MemoryRegionOps ioportF0_io_ops = {
2195 .write = ioportF0_write,
c02e1eac 2196 .read = ioportF0_read,
258711c6
JG		 2197 .endianness = DEVICE_NATIVE_ENDIAN,
2198 .impl = {
2199 .min_access_size = 1,
2200 .max_access_size = 1,
2201 },
2202};
2203
ac64273c
PMD		 2204static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
2205{
2206 int i;
2207 DriveInfo *fd[MAX_FD];
2208 qemu_irq *a20_line;
2209 ISADevice *i8042, *port92, *vmmouse;
2210
def337ff 2211 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
ac64273c
PMD		 2212 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
2213
2214 for (i = 0; i < MAX_FD; i++) {
2215 fd[i] = drive_get(IF_FLOPPY, 0, i);
2216 create_fdctrl |= !!fd[i];
2217 }
2218 if (create_fdctrl) {
2219 fdctrl_init_isa(isa_bus, fd);
2220 }
2221
2222 i8042 = isa_create_simple(isa_bus, "i8042");
2223 if (!no_vmport) {
2224 vmport_init(isa_bus);
2225 vmmouse = isa_try_create(isa_bus, "vmmouse");
2226 } else {
2227 vmmouse = NULL;
2228 }
2229 if (vmmouse) {
2230 DeviceState *dev = DEVICE(vmmouse);
2231 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
2232 qdev_init_nofail(dev);
2233 }
2234 port92 = isa_create_simple(isa_bus, "port92");
2235
2236 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
2237 i8042_setup_a20_line(i8042, a20_line[0]);
2238 port92_init(port92, a20_line[1]);
2239 g_free(a20_line);
2240}
2241
48a18b3c 2242void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1611977c 2243 ISADevice **rtc_state,
fd53c87c 2244 bool create_fdctrl,
7a10ef51 2245 bool no_vmport,
feddd2fd 2246 bool has_pit,
3a87d009 2247 uint32_t hpet_irqs)
ffe513da
IY		 2248{
2249 int i;
ce967e2f
JK		 2250 DeviceState *hpet = NULL;
2251 int pit_isa_irq = 0;
2252 qemu_irq pit_alt_irq = NULL;
7d932dfd 2253 qemu_irq rtc_irq = NULL;
ac64273c 2254 ISADevice *pit = NULL;
258711c6
JG		 2255 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
2256 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
ffe513da 2257
2c9b15ca 2258 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
258711c6 2259 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
ffe513da 2260
2c9b15ca 2261 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
258711c6 2262 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
ffe513da 2263
5d17c0d2
JK		 2264 /*
2265 * Check if an HPET shall be created.
2266 *
2267 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
2268 * when the HPET wants to take over. Thus we have to disable the latter.
2269 */
2270 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
7a10ef51 2271 /* In order to set property, here not using sysbus_try_create_simple */
51116102 2272 hpet = qdev_try_create(NULL, TYPE_HPET);
dd703b99 2273 if (hpet) {
7a10ef51
LPF		 2274 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
2275 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
2276 * IRQ8 and IRQ2.
2277 */
5d7fb0f2 2278 uint8_t compat = object_property_get_uint(OBJECT(hpet),
7a10ef51
LPF		 2279 HPET_INTCAP, NULL);
2280 if (!compat) {
2281 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
2282 }
2283 qdev_init_nofail(hpet);
2284 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
2285
b881fbe9 2286 for (i = 0; i < GSI_NUM_PINS; i++) {
1356b98d 2287 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
dd703b99 2288 }
ce967e2f
JK		 2289 pit_isa_irq = -1;
2290 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
2291 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
822557eb 2292 }
ffe513da 2293 }
6c646a11 2294 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
7d932dfd
JK		 2295
2296 qemu_register_boot_set(pc_boot_set, *rtc_state);
2297
feddd2fd 2298 if (!xen_enabled() && has_pit) {
15eafc2e 2299 if (kvm_pit_in_kernel()) {
c2d8d311
SS		 2300 pit = kvm_pit_init(isa_bus, 0x40);
2301 } else {
acf695ec 2302 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
c2d8d311
SS		 2303 }
2304 if (hpet) {
2305 /* connect PIT to output control line of the HPET */
4a17cc4f 2306 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
c2d8d311
SS		 2307 }
2308 pcspk_init(isa_bus, pit);
ce967e2f 2309 }
ffe513da 2310
55f613ac 2311 i8257_dma_init(isa_bus, 0);
ffe513da 2312
ac64273c
PMD		 2313 /* Super I/O */
2314 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
ffe513da
IY		 2315}
2316
4b9c264b 2317void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
9011a1a7
IY		 2318{
2319 int i;
2320
bab47d9a 2321 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
9011a1a7
IY		 2322 for (i = 0; i < nb_nics; i++) {
2323 NICInfo *nd = &nd_table[i];
4b9c264b 2324 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
9011a1a7 2325
4b9c264b 2326 if (g_str_equal(model, "ne2k_isa")) {
9011a1a7
IY		 2327 pc_init_ne2k_isa(isa_bus, nd);
2328 } else {
4b9c264b 2329 pci_nic_init_nofail(nd, pci_bus, model, NULL);
9011a1a7
IY		 2330 }
2331 }
bab47d9a 2332 rom_reset_order_override();
9011a1a7
IY		 2333}
2334
a39e3564
JB		 2335void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
2336{
2337 DeviceState *dev;
2338 SysBusDevice *d;
2339 unsigned int i;
2340
15eafc2e 2341 if (kvm_ioapic_in_kernel()) {
a39e3564
JB		 2342 dev = qdev_create(NULL, "kvm-ioapic");
2343 } else {
2344 dev = qdev_create(NULL, "ioapic");
2345 }
2346 if (parent_name) {
2347 object_property_add_child(object_resolve_path(parent_name, NULL),
2348 "ioapic", OBJECT(dev), NULL);
2349 }
2350 qdev_init_nofail(dev);
1356b98d 2351 d = SYS_BUS_DEVICE(dev);
3a4a4697 2352 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
a39e3564
JB		 2353
2354 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
2355 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
2356 }
2357}
d5747cac 2358
d468115b
DH		 2359static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2360 Error **errp)
2361{
2362 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
b0e62443 2363 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
d468115b 2364 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
b0e62443 2365 const uint64_t legacy_align = TARGET_PAGE_SIZE;
d468115b
DH		 2366
2367 /*
2368 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2369 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2370 * addition to cover this case.
2371 */
2372 if (!pcms->acpi_dev || !acpi_enabled) {
2373 error_setg(errp,
2374 "memory hotplug is not enabled: missing acpi device or acpi disabled");
2375 return;
2376 }
2377
2378 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) {
2379 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
2380 return;
2381 }
8f1ffe5b 2382
fd3416f5 2383 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
b0e62443 2384 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
d468115b
DH		 2385}
2386
bb6e2f7a
DH		 2387static void pc_memory_plug(HotplugHandler *hotplug_dev,
2388 DeviceState *dev, Error **errp)
95bee274 2389{
3fbcdc27 2390 HotplugHandlerClass *hhc;
95bee274
IM		 2391 Error *local_err = NULL;
2392 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
7f3cf2d6 2393 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
95bee274 2394
fd3416f5 2395 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
43bbb49e 2396 if (local_err) {
b8865591
IM		 2397 goto out;
2398 }
2399
7f3cf2d6 2400 if (is_nvdimm) {
284197e4 2401 nvdimm_plug(&pcms->acpi_nvdimm_state);
c7f8d0f3
XG		 2402 }
2403
3fbcdc27 2404 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
8e23184b 2405 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
95bee274
IM		 2406out:
2407 error_propagate(errp, local_err);
2408}
2409
bb6e2f7a
DH		 2410static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
2411 DeviceState *dev, Error **errp)
64fec58e
TC		 2412{
2413 HotplugHandlerClass *hhc;
2414 Error *local_err = NULL;
2415 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2416
8cd91ace
HZ		 2417 /*
2418 * When -no-acpi is used with Q35 machine type, no ACPI is built,
2419 * but pcms->acpi_dev is still created. Check !acpi_enabled in
2420 * addition to cover this case.
2421 */
2422 if (!pcms->acpi_dev || !acpi_enabled) {
64fec58e 2423 error_setg(&local_err,
8cd91ace 2424 "memory hotplug is not enabled: missing acpi device or acpi disabled");
64fec58e
TC		 2425 goto out;
2426 }
2427
b097cc52
XG		 2428 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2429 error_setg(&local_err,
2430 "nvdimm device hot unplug is not supported yet.");
2431 goto out;
2432 }
2433
64fec58e
TC		 2434 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2435 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2436
2437out:
2438 error_propagate(errp, local_err);
2439}
2440
bb6e2f7a
DH		 2441static void pc_memory_unplug(HotplugHandler *hotplug_dev,
2442 DeviceState *dev, Error **errp)
f7d3e29d
TC		 2443{
2444 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
f7d3e29d
TC		 2445 HotplugHandlerClass *hhc;
2446 Error *local_err = NULL;
2447
2448 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2449 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2450
2451 if (local_err) {
2452 goto out;
2453 }
2454
fd3416f5 2455 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
f7d3e29d
TC		 2456 object_unparent(OBJECT(dev));
2457
2458 out:
2459 error_propagate(errp, local_err);
2460}
2461
3811ef14
IM		 2462static int pc_apic_cmp(const void *a, const void *b)
2463{
2464 CPUArchId *apic_a = (CPUArchId *)a;
2465 CPUArchId *apic_b = (CPUArchId *)b;
2466
2467 return apic_a->arch_id - apic_b->arch_id;
2468}
2469
7baef5cf 2470/* returns pointer to CPUArchId descriptor that matches CPU's apic_id
38690a1c 2471 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
b12227af 2472 * entry corresponding to CPU's apic_id returns NULL.
7baef5cf 2473 */
1ea69c0e 2474static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
7baef5cf 2475{
7baef5cf
IM		 2476 CPUArchId apic_id, *found_cpu;
2477
1ea69c0e 2478 apic_id.arch_id = id;
38690a1c
IM		 2479 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
2480 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
7baef5cf
IM		 2481 pc_apic_cmp);
2482 if (found_cpu && idx) {
38690a1c 2483 *idx = found_cpu - ms->possible_cpus->cpus;
7baef5cf
IM		 2484 }
2485 return found_cpu;
2486}
2487
5279569e
GZ		 2488static void pc_cpu_plug(HotplugHandler *hotplug_dev,
2489 DeviceState *dev, Error **errp)
2490{
7baef5cf 2491 CPUArchId *found_cpu;
5279569e
GZ		 2492 HotplugHandlerClass *hhc;
2493 Error *local_err = NULL;
1ea69c0e 2494 X86CPU *cpu = X86_CPU(dev);
5279569e
GZ		 2495 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2496
a44a49db
IM		 2497 if (pcms->acpi_dev) {
2498 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2499 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2500 if (local_err) {
2501 goto out;
2502 }
5279569e
GZ		 2503 }
2504
e3cadac0
IM		 2505 /* increment the number of CPUs */
2506 pcms->boot_cpus++;
26ef65be 2507 if (pcms->rtc) {
e3cadac0 2508 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
26ef65be
IM		 2509 }
2510 if (pcms->fw_cfg) {
e3cadac0 2511 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
2d996150
GZ		 2512 }
2513
1ea69c0e 2514 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8aba3842 2515 found_cpu->cpu = OBJECT(dev);
5279569e
GZ		 2516out:
2517 error_propagate(errp, local_err);
2518}
8872c25a
IM		 2519static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
2520 DeviceState *dev, Error **errp)
2521{
73360e27 2522 int idx = -1;
8872c25a
IM		 2523 HotplugHandlerClass *hhc;
2524 Error *local_err = NULL;
1ea69c0e 2525 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2526 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2527
75ba2ddb
IM		 2528 if (!pcms->acpi_dev) {
2529 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
2530 goto out;
2531 }
2532
1ea69c0e 2533 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
73360e27
IM		 2534 assert(idx != -1);
2535 if (idx == 0) {
2536 error_setg(&local_err, "Boot CPU is unpluggable");
2537 goto out;
2538 }
2539
8872c25a
IM		 2540 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2541 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2542
2543 if (local_err) {
2544 goto out;
2545 }
2546
2547 out:
2548 error_propagate(errp, local_err);
2549
2550}
2551
2552static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
2553 DeviceState *dev, Error **errp)
2554{
8fe6374e 2555 CPUArchId *found_cpu;
8872c25a
IM		 2556 HotplugHandlerClass *hhc;
2557 Error *local_err = NULL;
1ea69c0e 2558 X86CPU *cpu = X86_CPU(dev);
8872c25a
IM		 2559 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
2560
2561 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev);
2562 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
2563
2564 if (local_err) {
2565 goto out;
2566 }
2567
1ea69c0e 2568 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
8fe6374e
IM		 2569 found_cpu->cpu = NULL;
2570 object_unparent(OBJECT(dev));
8872c25a 2571
e3cadac0
IM		 2572 /* decrement the number of CPUs */
2573 pcms->boot_cpus--;
2574 /* Update the number of CPUs in CMOS */
2575 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus);
2576 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
8872c25a
IM		 2577 out:
2578 error_propagate(errp, local_err);
2579}
5279569e 2580
4ec60c76
IM		 2581static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
2582 DeviceState *dev, Error **errp)
2583{
2584 int idx;
a15d2728 2585 CPUState *cs;
e8f7b83e 2586 CPUArchId *cpu_slot;
d89c2b8b 2587 X86CPUTopoInfo topo;
4ec60c76 2588 X86CPU *cpu = X86_CPU(dev);
6970c5ff 2589 MachineState *ms = MACHINE(hotplug_dev);
4ec60c76 2590 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
4ec60c76 2591
6970c5ff
IM		 2592 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
2593 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
2594 ms->cpu_type);
2595 return;
2596 }
2597
e8f7b83e
IM		 2598 /* if APIC ID is not set, set it based on socket/core/thread properties */
2599 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2600 int max_socket = (max_cpus - 1) / smp_threads / smp_cores;
2601
2602 if (cpu->socket_id < 0) {
2603 error_setg(errp, "CPU socket-id is not set");
2604 return;
2605 } else if (cpu->socket_id > max_socket) {
2606 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
2607 cpu->socket_id, max_socket);
2608 return;
2609 }
2610 if (cpu->core_id < 0) {
2611 error_setg(errp, "CPU core-id is not set");
2612 return;
2613 } else if (cpu->core_id > (smp_cores - 1)) {
2614 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
2615 cpu->core_id, smp_cores - 1);
2616 return;
2617 }
2618 if (cpu->thread_id < 0) {
2619 error_setg(errp, "CPU thread-id is not set");
2620 return;
2621 } else if (cpu->thread_id > (smp_threads - 1)) {
2622 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
2623 cpu->thread_id, smp_threads - 1);
2624 return;
2625 }
2626
2627 topo.pkg_id = cpu->socket_id;
2628 topo.core_id = cpu->core_id;
2629 topo.smt_id = cpu->thread_id;
2630 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo);
2631 }
2632
1ea69c0e 2633 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
4ec60c76 2634 if (!cpu_slot) {
38690a1c
IM		 2635 MachineState *ms = MACHINE(pcms);
2636
e8f7b83e
IM		 2637 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2638 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with"
2639 " APIC ID %" PRIu32 ", valid index range 0:%d",
2640 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id,
38690a1c 2641 ms->possible_cpus->len - 1);
4ec60c76
IM		 2642 return;
2643 }
2644
2645 if (cpu_slot->cpu) {
2646 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
2647 idx, cpu->apic_id);
2648 return;
2649 }
d89c2b8b
IM		 2650
2651 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
c5514d0e 2652 * so that machine_query_hotpluggable_cpus would show correct values
d89c2b8b
IM		 2653 */
2654 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
2655 * once -smp refactoring is complete and there will be CPU private
2656 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
2657 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo);
2658 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) {
2659 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
2660 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id);
2661 return;
2662 }
2663 cpu->socket_id = topo.pkg_id;
2664
2665 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) {
2666 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
2667 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id);
2668 return;
2669 }
2670 cpu->core_id = topo.core_id;
2671
2672 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) {
2673 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
2674 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id);
2675 return;
2676 }
2677 cpu->thread_id = topo.smt_id;
a15d2728 2678
e9688fab
RK		 2679 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) {
2680 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
2681 return;
2682 }
2683
a15d2728
IM		 2684 cs = CPU(cpu);
2685 cs->cpu_index = idx;
93b2a8cb 2686
a0ceb640 2687 numa_cpu_pre_plug(cpu_slot, dev, errp);
4ec60c76
IM		 2688}
2689
2690static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2691 DeviceState *dev, Error **errp)
2692{
d468115b
DH		 2693 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2694 pc_memory_pre_plug(hotplug_dev, dev, errp);
2695 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
4ec60c76
IM		 2696 pc_cpu_pre_plug(hotplug_dev, dev, errp);
2697 }
2698}
2699
95bee274
IM		 2700static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2701 DeviceState *dev, Error **errp)
2702{
2703 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2704 pc_memory_plug(hotplug_dev, dev, errp);
5279569e
GZ		 2705 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2706 pc_cpu_plug(hotplug_dev, dev, errp);
95bee274
IM		 2707 }
2708}
2709
d9c5c5b8
TC		 2710static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2711 DeviceState *dev, Error **errp)
2712{
64fec58e 2713 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2714 pc_memory_unplug_request(hotplug_dev, dev, errp);
8872c25a
IM		 2715 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2716 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
64fec58e
TC		 2717 } else {
2718 error_setg(errp, "acpi: device unplug request for not supported device"
2719 " type: %s", object_get_typename(OBJECT(dev)));
2720 }
d9c5c5b8
TC		 2721}
2722
232391c1
TC		 2723static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2724 DeviceState *dev, Error **errp)
2725{
f7d3e29d 2726 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
bb6e2f7a 2727 pc_memory_unplug(hotplug_dev, dev, errp);
8872c25a
IM		 2728 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
2729 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
f7d3e29d
TC		 2730 } else {
2731 error_setg(errp, "acpi: device unplug for not supported device"
2732 " type: %s", object_get_typename(OBJECT(dev)));
2733 }
232391c1
TC		 2734}
2735
95bee274
IM		 2736static HotplugHandler *pc_get_hotpug_handler(MachineState *machine,
2737 DeviceState *dev)
2738{
5279569e
GZ		 2739 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2740 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
95bee274
IM		 2741 return HOTPLUG_HANDLER(machine);
2742 }
2743
38aefb57 2744 return NULL;
95bee274
IM		 2745}
2746
bf1e8939 2747static void
f2ffbe2b
DH		 2748pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
2749 const char *name, void *opaque,
2750 Error **errp)
bf1e8939 2751{
b0c14ec4
DH		 2752 MachineState *ms = MACHINE(obj);
2753 int64_t value = memory_region_size(&ms->device_memory->mr);
bf1e8939 2754
51e72bc1 2755 visit_type_int(v, name, &value, errp);
bf1e8939
IM		 2756}
2757
c87b1520 2758static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2759 const char *name, void *opaque,
2760 Error **errp)
c87b1520
DS		 2761{
2762 PCMachineState *pcms = PC_MACHINE(obj);
2763 uint64_t value = pcms->max_ram_below_4g;
2764
51e72bc1 2765 visit_type_size(v, name, &value, errp);
c87b1520
DS		 2766}
2767
2768static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
d7bce999
EB		 2769 const char *name, void *opaque,
2770 Error **errp)
c87b1520
DS		 2771{
2772 PCMachineState *pcms = PC_MACHINE(obj);
2773 Error *error = NULL;
2774 uint64_t value;
2775
51e72bc1 2776 visit_type_size(v, name, &value, &error);
c87b1520
DS		 2777 if (error) {
2778 error_propagate(errp, error);
2779 return;
2780 }
d471bf3e 2781 if (value > 4 * GiB) {
455b0fde
EB		 2782 error_setg(&error,
2783 "Machine option 'max-ram-below-4g=%"PRIu64
2784 "' expects size less than or equal to 4G", value);
c87b1520
DS		 2785 error_propagate(errp, error);
2786 return;
2787 }
2788
d471bf3e 2789 if (value < 1 * MiB) {
9e5d2c52
AF		 2790 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
2791 "BIOS may not work with less than 1MiB", value);
c87b1520
DS		 2792 }
2793
2794 pcms->max_ram_below_4g = value;
2795}
2796
d7bce999
EB		 2797static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
2798 void *opaque, Error **errp)
9b23cfb7
DDAG		 2799{
2800 PCMachineState *pcms = PC_MACHINE(obj);
d1048bef 2801 OnOffAuto vmport = pcms->vmport;
9b23cfb7 2802
51e72bc1 2803 visit_type_OnOffAuto(v, name, &vmport, errp);
9b23cfb7
DDAG		 2804}
2805
d7bce999
EB		 2806static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
2807 void *opaque, Error **errp)
9b23cfb7
DDAG		 2808{
2809 PCMachineState *pcms = PC_MACHINE(obj);
2810
51e72bc1 2811 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
9b23cfb7
DDAG		 2812}
2813
355023f2
PB		 2814bool pc_machine_is_smm_enabled(PCMachineState *pcms)
2815{
2816 bool smm_available = false;
2817
2818 if (pcms->smm == ON_OFF_AUTO_OFF) {
2819 return false;
2820 }
2821
2822 if (tcg_enabled() || qtest_enabled()) {
2823 smm_available = true;
2824 } else if (kvm_enabled()) {
2825 smm_available = kvm_has_smm();
2826 }
2827
2828 if (smm_available) {
2829 return true;
2830 }
2831
2832 if (pcms->smm == ON_OFF_AUTO_ON) {
2833 error_report("System Management Mode not supported by this hypervisor.");
2834 exit(1);
2835 }
2836 return false;
2837}
2838
d7bce999
EB		 2839static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name,
2840 void *opaque, Error **errp)
355023f2
PB		 2841{
2842 PCMachineState *pcms = PC_MACHINE(obj);
2843 OnOffAuto smm = pcms->smm;
2844
51e72bc1 2845 visit_type_OnOffAuto(v, name, &smm, errp);
355023f2
PB		 2846}
2847
d7bce999
EB		 2848static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name,
2849 void *opaque, Error **errp)
355023f2
PB		 2850{
2851 PCMachineState *pcms = PC_MACHINE(obj);
2852
51e72bc1 2853 visit_type_OnOffAuto(v, name, &pcms->smm, errp);
355023f2
PB		 2854}
2855
87252e1b
XG		 2856static bool pc_machine_get_nvdimm(Object *obj, Error **errp)
2857{
2858 PCMachineState *pcms = PC_MACHINE(obj);
2859
5fe79386 2860 return pcms->acpi_nvdimm_state.is_enabled;
87252e1b
XG		 2861}
2862
2863static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp)
2864{
2865 PCMachineState *pcms = PC_MACHINE(obj);
2866
5fe79386 2867 pcms->acpi_nvdimm_state.is_enabled = value;
87252e1b
XG		 2868}
2869
11c39b5c 2870static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp)
9ab3aad2
RZ		 2871{
2872 PCMachineState *pcms = PC_MACHINE(obj);
9ab3aad2 2873
11c39b5c 2874 return g_strdup(pcms->acpi_nvdimm_state.persistence_string);
9ab3aad2
RZ		 2875}
2876
11c39b5c 2877static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value,
9ab3aad2
RZ		 2878 Error **errp)
2879{
2880 PCMachineState *pcms = PC_MACHINE(obj);
11c39b5c
RZ		 2881 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state;
2882
2883 if (strcmp(value, "cpu") == 0)
2884 nvdimm_state->persistence = 3;
2885 else if (strcmp(value, "mem-ctrl") == 0)
2886 nvdimm_state->persistence = 2;
2887 else {
d319e05d
MA		 2888 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option",
2889 value);
2890 return;
9ab3aad2
RZ		 2891 }
2892
11c39b5c
RZ		 2893 g_free(nvdimm_state->persistence_string);
2894 nvdimm_state->persistence_string = g_strdup(value);
9ab3aad2
RZ		 2895}
2896
be232eb0
CP		 2897static bool pc_machine_get_smbus(Object *obj, Error **errp)
2898{
2899 PCMachineState *pcms = PC_MACHINE(obj);
2900
f5878b03 2901 return pcms->smbus_enabled;
be232eb0
CP		 2902}
2903
2904static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
2905{
2906 PCMachineState *pcms = PC_MACHINE(obj);
2907
f5878b03 2908 pcms->smbus_enabled = value;
be232eb0
CP		 2909}
2910
272f0428
CP		 2911static bool pc_machine_get_sata(Object *obj, Error **errp)
2912{
2913 PCMachineState *pcms = PC_MACHINE(obj);
2914
f5878b03 2915 return pcms->sata_enabled;
272f0428
CP		 2916}
2917
2918static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
2919{
2920 PCMachineState *pcms = PC_MACHINE(obj);
2921
f5878b03 2922 pcms->sata_enabled = value;
272f0428
CP		 2923}
2924
feddd2fd
CP		 2925static bool pc_machine_get_pit(Object *obj, Error **errp)
2926{
2927 PCMachineState *pcms = PC_MACHINE(obj);
2928
f5878b03 2929 return pcms->pit_enabled;
feddd2fd
CP		 2930}
2931
2932static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
2933{
2934 PCMachineState *pcms = PC_MACHINE(obj);
2935
f5878b03 2936 pcms->pit_enabled = value;
feddd2fd
CP		 2937}
2938
bf1e8939
IM		 2939static void pc_machine_initfn(Object *obj)
2940{
c87b1520
DS		 2941 PCMachineState *pcms = PC_MACHINE(obj);
2942
5ec7d098 2943 pcms->max_ram_below_4g = 0; /* use default */
355023f2 2944 pcms->smm = ON_OFF_AUTO_AUTO;
d1048bef 2945 pcms->vmport = ON_OFF_AUTO_AUTO;
87252e1b 2946 /* nvdimm is disabled on default. */
5fe79386 2947 pcms->acpi_nvdimm_state.is_enabled = false;
021746c1
WL		 2948 /* acpi build is enabled by default if machine supports it */
2949 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
f5878b03
CM		 2950 pcms->smbus_enabled = true;
2951 pcms->sata_enabled = true;
2952 pcms->pit_enabled = true;
bf1e8939
IM		 2953}
2954
ae50c55a
ZG		 2955static void pc_machine_reset(void)
2956{
2957 CPUState *cs;
2958 X86CPU *cpu;
2959
2960 qemu_devices_reset();
2961
2962 /* Reset APIC after devices have been reset to cancel
2963 * any changes that qemu_devices_reset() might have done.
2964 */
2965 CPU_FOREACH(cs) {
2966 cpu = X86_CPU(cs);
2967
2968 if (cpu->apic_state) {
2969 device_reset(cpu->apic_state);
2970 }
2971 }
2972}
2973
ea089eeb
IM		 2974static CpuInstanceProperties
2975pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
fb43b73b 2976{
ea089eeb
IM		 2977 MachineClass *mc = MACHINE_GET_CLASS(ms);
2978 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2979
2980 assert(cpu_index < possible_cpus->len);
2981 return possible_cpus->cpus[cpu_index].props;
fb43b73b
IM		 2982}
2983
79e07936
IM		 2984static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx)
2985{
2986 X86CPUTopoInfo topo;
2987
2988 assert(idx < ms->possible_cpus->len);
2989 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id,
2990 smp_cores, smp_threads, &topo);
2991 return topo.pkg_id % nb_numa_nodes;
2992}
2993
c96a1c0b 2994static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
3811ef14 2995{
c96a1c0b
IM		 2996 int i;
2997
2998 if (ms->possible_cpus) {
2999 /*
3000 * make sure that max_cpus hasn't changed since the first use, i.e.
3001 * -smp hasn't been parsed after it
3002 */
3003 assert(ms->possible_cpus->len == max_cpus);
3004 return ms->possible_cpus;
3005 }
3006
3007 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3008 sizeof(CPUArchId) * max_cpus);
3009 ms->possible_cpus->len = max_cpus;
3010 for (i = 0; i < ms->possible_cpus->len; i++) {
c67ae933
IM		 3011 X86CPUTopoInfo topo;
3012
d342eb76 3013 ms->possible_cpus->cpus[i].type = ms->cpu_type;
f2d672c2 3014 ms->possible_cpus->cpus[i].vcpus_count = 1;
c96a1c0b 3015 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i);
c67ae933
IM		 3016 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id,
3017 smp_cores, smp_threads, &topo);
3018 ms->possible_cpus->cpus[i].props.has_socket_id = true;
3019 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id;
3020 ms->possible_cpus->cpus[i].props.has_core_id = true;
3021 ms->possible_cpus->cpus[i].props.core_id = topo.core_id;
3022 ms->possible_cpus->cpus[i].props.has_thread_id = true;
3023 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id;
c96a1c0b
IM		 3024 }
3025 return ms->possible_cpus;
3811ef14
IM		 3026}
3027
1255166b
BD		 3028static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
3029{
3030 /* cpu index isn't used */
3031 CPUState *cs;
3032
3033 CPU_FOREACH(cs) {
3034 X86CPU *cpu = X86_CPU(cs);
3035
3036 if (!cpu->apic_state) {
3037 cpu_interrupt(cs, CPU_INTERRUPT_NMI);
3038 } else {
3039 apic_deliver_nmi(cpu->apic_state);
3040 }
3041 }
3042}
3043
95bee274
IM		 3044static void pc_machine_class_init(ObjectClass *oc, void *data)
3045{
3046 MachineClass *mc = MACHINE_CLASS(oc);
3047 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
3048 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1255166b 3049 NMIClass *nc = NMI_CLASS(oc);
95bee274 3050
7102fa70
EH		 3051 pcmc->pci_enabled = true;
3052 pcmc->has_acpi_build = true;
3053 pcmc->rsdp_in_ram = true;
3054 pcmc->smbios_defaults = true;
3055 pcmc->smbios_uuid_encoded = true;
3056 pcmc->gigabyte_align = true;
3057 pcmc->has_reserved_memory = true;
3058 pcmc->kvmclock_enabled = true;
16a9e8a5 3059 pcmc->enforce_aligned_dimm = true;
cd4040ec
EH		 3060 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
3061 * to be used at the moment, 32K should be enough for a while. */
3062 pcmc->acpi_data_size = 0x20000 + 0x8000;
36f96c4b 3063 pcmc->save_tsc_khz = true;
98e753a6 3064 pcmc->linuxboot_dma_enabled = true;
debbdc00 3065 assert(!mc->get_hotplug_handler);
95bee274 3066 mc->get_hotplug_handler = pc_get_hotpug_handler;
ea089eeb 3067 mc->cpu_index_to_instance_props = pc_cpu_index_to_props;
79e07936 3068 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id;
3811ef14 3069 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids;
7b8be49d 3070 mc->auto_enable_numa_with_memhp = true;
c5514d0e 3071 mc->has_hotpluggable_cpus = true;
41742767 3072 mc->default_boot_order = "cad";
4458fb3a 3073 mc->hot_add_cpu = pc_hot_add_cpu;
2059839b 3074 mc->block_default_type = IF_IDE;
4458fb3a 3075 mc->max_cpus = 255;
ae50c55a 3076 mc->reset = pc_machine_reset;
4ec60c76 3077 hc->pre_plug = pc_machine_device_pre_plug_cb;
95bee274 3078 hc->plug = pc_machine_device_plug_cb;
d9c5c5b8 3079 hc->unplug_request = pc_machine_device_unplug_request_cb;
232391c1 3080 hc->unplug = pc_machine_device_unplug_cb;
1255166b 3081 nc->nmi_monitor_handler = x86_nmi;
311ca98d 3082 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
0efc257d 3083
f2ffbe2b
DH		 3084 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
3085 pc_machine_get_device_memory_region_size, NULL,
0efc257d
EH		 3086 NULL, NULL, &error_abort);
3087
3088 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
3089 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
3090 NULL, NULL, &error_abort);
3091
3092 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
3093 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort);
3094
3095 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto",
3096 pc_machine_get_smm, pc_machine_set_smm,
3097 NULL, NULL, &error_abort);
3098 object_class_property_set_description(oc, PC_MACHINE_SMM,
3099 "Enable SMM (pc & q35)", &error_abort);
3100
3101 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
3102 pc_machine_get_vmport, pc_machine_set_vmport,
3103 NULL, NULL, &error_abort);
3104 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
3105 "Enable vmport (pc & q35)", &error_abort);
3106
3107 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM,
3108 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort);
be232eb0 3109
11c39b5c
RZ		 3110 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST,
3111 pc_machine_get_nvdimm_persistence,
3112 pc_machine_set_nvdimm_persistence, &error_abort);
9ab3aad2 3113
be232eb0
CP		 3114 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
3115 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort);
272f0428
CP		 3116
3117 object_class_property_add_bool(oc, PC_MACHINE_SATA,
3118 pc_machine_get_sata, pc_machine_set_sata, &error_abort);
feddd2fd
CP		 3119
3120 object_class_property_add_bool(oc, PC_MACHINE_PIT,
3121 pc_machine_get_pit, pc_machine_set_pit, &error_abort);
95bee274
IM		 3122}
3123
d5747cac
IM		 3124static const TypeInfo pc_machine_info = {
3125 .name = TYPE_PC_MACHINE,
3126 .parent = TYPE_MACHINE,
3127 .abstract = true,
3128 .instance_size = sizeof(PCMachineState),
bf1e8939 3129 .instance_init = pc_machine_initfn,
d5747cac 3130 .class_size = sizeof(PCMachineClass),
95bee274
IM		 3131 .class_init = pc_machine_class_init,
3132 .interfaces = (InterfaceInfo[]) {
3133 { TYPE_HOTPLUG_HANDLER },
1255166b 3134 { TYPE_NMI },
95bee274
IM		 3135 { }
3136 },
d5747cac
IM		 3137};
3138
3139static void pc_machine_register_types(void)
3140{
3141 type_register_static(&pc_machine_info);
3142}
3143
3144type_init(pc_machine_register_types)
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