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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 | 30 | #include "cpu.h" |
9c17d615 | 31 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
32 | #include "hw/boards.h" |
33 | #include "hw/loader.h" | |
0200db65 | 34 | #include "elf.h" |
022c62cb PB |
35 | #include "exec/memory.h" |
36 | #include "exec/address-spaces.h" | |
0d09e41a | 37 | #include "hw/char/serial.h" |
1422e32d | 38 | #include "net/net.h" |
83c9f4ca | 39 | #include "hw/sysbus.h" |
0d09e41a | 40 | #include "hw/block/flash.h" |
8228e353 | 41 | #include "chardev/char.h" |
996dfe98 | 42 | #include "sysemu/device_tree.h" |
8488ab02 | 43 | #include "qemu/error-report.h" |
922a01a0 | 44 | #include "qemu/option.h" |
b707ab75 | 45 | #include "bootparam.h" |
e53fa62c | 46 | #include "xtensa_memory.h" |
82b25dc8 | 47 | |
740ad9f7 MF |
48 | typedef struct XtfpgaFlashDesc { |
49 | hwaddr base; | |
50 | size_t size; | |
51 | size_t boot_base; | |
52 | size_t sector_size; | |
53 | } XtfpgaFlashDesc; | |
54 | ||
188ce01d | 55 | typedef struct XtfpgaBoardDesc { |
740ad9f7 | 56 | const XtfpgaFlashDesc *flash; |
82b25dc8 | 57 | size_t sram_size; |
85e2d8d5 | 58 | const hwaddr *io; |
188ce01d | 59 | } XtfpgaBoardDesc; |
0200db65 | 60 | |
188ce01d | 61 | typedef struct XtfpgaFpgaState { |
0200db65 MF |
62 | MemoryRegion iomem; |
63 | uint32_t leds; | |
64 | uint32_t switches; | |
188ce01d | 65 | } XtfpgaFpgaState; |
0200db65 | 66 | |
188ce01d | 67 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 68 | { |
188ce01d | 69 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
70 | |
71 | s->leds = 0; | |
72 | s->switches = 0; | |
73 | } | |
74 | ||
188ce01d | 75 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
76 | unsigned size) |
77 | { | |
188ce01d | 78 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
79 | |
80 | switch (addr) { | |
81 | case 0x0: /*build date code*/ | |
556ba668 | 82 | return 0x09272011; |
0200db65 MF |
83 | |
84 | case 0x4: /*processor clock frequency, Hz*/ | |
85 | return 10000000; | |
86 | ||
87 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
88 | return s->leds; | |
89 | ||
90 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
91 | return s->switches; | |
92 | } | |
93 | return 0; | |
94 | } | |
95 | ||
188ce01d | 96 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
97 | uint64_t val, unsigned size) |
98 | { | |
188ce01d | 99 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
100 | |
101 | switch (addr) { | |
102 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
103 | s->leds = val; | |
104 | break; | |
105 | ||
106 | case 0x10: /*board reset*/ | |
107 | if (val == 0xdead) { | |
cf83f140 | 108 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
109 | } |
110 | break; | |
111 | } | |
112 | } | |
113 | ||
188ce01d MF |
114 | static const MemoryRegionOps xtfpga_fpga_ops = { |
115 | .read = xtfpga_fpga_read, | |
116 | .write = xtfpga_fpga_write, | |
0200db65 MF |
117 | .endianness = DEVICE_NATIVE_ENDIAN, |
118 | }; | |
119 | ||
188ce01d | 120 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
a8170e5e | 121 | hwaddr base) |
0200db65 | 122 | { |
188ce01d | 123 | XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); |
0200db65 | 124 | |
188ce01d MF |
125 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
126 | "xtfpga.fpga", 0x10000); | |
0200db65 | 127 | memory_region_add_subregion(address_space, base, &s->iomem); |
188ce01d MF |
128 | xtfpga_fpga_reset(s); |
129 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
130 | return s; |
131 | } | |
132 | ||
188ce01d | 133 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
134 | hwaddr base, |
135 | hwaddr descriptors, | |
136 | hwaddr buffers, | |
0200db65 MF |
137 | qemu_irq irq, NICInfo *nd) |
138 | { | |
139 | DeviceState *dev; | |
140 | SysBusDevice *s; | |
141 | MemoryRegion *ram; | |
142 | ||
143 | dev = qdev_create(NULL, "open_eth"); | |
144 | qdev_set_nic_properties(dev, nd); | |
145 | qdev_init_nofail(dev); | |
146 | ||
1356b98d | 147 | s = SYS_BUS_DEVICE(dev); |
0200db65 MF |
148 | sysbus_connect_irq(s, 0, irq); |
149 | memory_region_add_subregion(address_space, base, | |
150 | sysbus_mmio_get_region(s, 0)); | |
151 | memory_region_add_subregion(address_space, descriptors, | |
152 | sysbus_mmio_get_region(s, 1)); | |
153 | ||
154 | ram = g_malloc(sizeof(*ram)); | |
1cfe48c1 | 155 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384, |
f8ed85ac | 156 | &error_fatal); |
c5705a77 | 157 | vmstate_register_ram_global(ram); |
0200db65 MF |
158 | memory_region_add_subregion(address_space, buffers, ram); |
159 | } | |
160 | ||
68931a40 | 161 | static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, |
188ce01d | 162 | const XtfpgaBoardDesc *board, |
68931a40 MF |
163 | DriveInfo *dinfo, int be) |
164 | { | |
165 | SysBusDevice *s; | |
166 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
167 | ||
168 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
169 | &error_abort); | |
170 | qdev_prop_set_uint32(dev, "num-blocks", | |
740ad9f7 MF |
171 | board->flash->size / board->flash->sector_size); |
172 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); | |
f9a555e4 | 173 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 174 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 175 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 MF |
176 | qdev_init_nofail(dev); |
177 | s = SYS_BUS_DEVICE(dev); | |
740ad9f7 | 178 | memory_region_add_subregion(address_space, board->flash->base, |
68931a40 MF |
179 | sysbus_mmio_get_region(s, 0)); |
180 | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); | |
181 | } | |
182 | ||
00b941e5 | 183 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 184 | { |
00b941e5 AF |
185 | XtensaCPU *cpu = opaque; |
186 | ||
187 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
188 | } |
189 | ||
188ce01d | 190 | static void xtfpga_reset(void *opaque) |
0200db65 | 191 | { |
eded1267 | 192 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 193 | |
eded1267 | 194 | cpu_reset(CPU(cpu)); |
0200db65 MF |
195 | } |
196 | ||
188ce01d | 197 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
198 | unsigned size) |
199 | { | |
200 | return 0; | |
201 | } | |
202 | ||
188ce01d | 203 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
204 | uint64_t val, unsigned size) |
205 | { | |
206 | } | |
207 | ||
188ce01d MF |
208 | static const MemoryRegionOps xtfpga_io_ops = { |
209 | .read = xtfpga_io_read, | |
210 | .write = xtfpga_io_write, | |
8bb3b575 MF |
211 | .endianness = DEVICE_NATIVE_ENDIAN, |
212 | }; | |
213 | ||
188ce01d | 214 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 MF |
215 | { |
216 | #ifdef TARGET_WORDS_BIGENDIAN | |
217 | int be = 1; | |
218 | #else | |
219 | int be = 0; | |
220 | #endif | |
221 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 222 | XtensaCPU *cpu = NULL; |
5bfcb36e | 223 | CPUXtensaState *env = NULL; |
e53fa62c | 224 | MemoryRegion *system_io; |
82b25dc8 MF |
225 | DriveInfo *dinfo; |
226 | pflash_t *flash = NULL; | |
37b259d0 | 227 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
37b259d0 MF |
228 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
229 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 230 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 231 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
85e2d8d5 | 232 | const unsigned system_io_size = 224 * 1024 * 1024; |
0200db65 MF |
233 | int n; |
234 | ||
235 | for (n = 0; n < smp_cpus; n++) { | |
f83eb10d | 236 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
adbb0f75 AF |
237 | env = &cpu->env; |
238 | ||
0200db65 | 239 | env->sregs[PRID] = n; |
188ce01d | 240 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
241 | /* Need MMU initialized prior to ELF loading, |
242 | * so that ELF gets loaded into virtual addresses | |
243 | */ | |
adbb0f75 | 244 | cpu_reset(CPU(cpu)); |
0200db65 MF |
245 | } |
246 | ||
e53fa62c MF |
247 | if (env) { |
248 | XtensaMemory sysram = env->config->sysram; | |
249 | ||
250 | sysram.location[0].size = machine->ram_size; | |
251 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
252 | system_memory); | |
253 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
254 | system_memory); | |
255 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
256 | system_memory); | |
257 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
258 | system_memory); | |
259 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
260 | system_memory); | |
261 | } | |
0200db65 | 262 | |
0200db65 | 263 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 264 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
85e2d8d5 MF |
265 | system_io_size); |
266 | memory_region_add_subregion(system_memory, board->io[0], system_io); | |
267 | if (board->io[1]) { | |
268 | MemoryRegion *io = g_malloc(sizeof(*io)); | |
269 | ||
270 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", | |
271 | system_io, 0, system_io_size); | |
272 | memory_region_add_subregion(system_memory, board->io[1], io); | |
273 | } | |
188ce01d | 274 | xtfpga_fpga_init(system_io, 0x0d020000); |
a005d073 | 275 | if (nd_table[0].used) { |
188ce01d | 276 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
0200db65 MF |
277 | xtensa_get_extint(env, 1), nd_table); |
278 | } | |
279 | ||
0200db65 | 280 | serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), |
9bca0edb | 281 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
0200db65 | 282 | |
82b25dc8 MF |
283 | dinfo = drive_get(IF_PFLASH, 0, 0); |
284 | if (dinfo) { | |
68931a40 | 285 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
286 | } |
287 | ||
288 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 289 | if (kernel_filename) { |
364d4802 | 290 | uint32_t entry_point = env->pc; |
b6edea8b | 291 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
292 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
293 | board->sram_size; | |
a9a28591 | 294 | uint32_t cur_tagptr; |
b6edea8b MF |
295 | BpMemInfo memory_location = { |
296 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
297 | .start = tswap32(env->config->sysram.location[0].addr), |
298 | .end = tswap32(env->config->sysram.location[0].addr + | |
299 | machine->ram_size), | |
b6edea8b | 300 | }; |
996dfe98 MF |
301 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
302 | machine->ram_size : 0x08000000; | |
303 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 304 | |
e53fa62c MF |
305 | lowmem_end += env->config->sysram.location[0].addr; |
306 | cur_lowmem += env->config->sysram.location[0].addr; | |
307 | ||
308 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
309 | system_memory); | |
292627bb | 310 | |
a9a28591 MF |
311 | if (kernel_cmdline) { |
312 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
313 | } | |
996dfe98 MF |
314 | if (dtb_filename) { |
315 | bp_size += get_tag_size(sizeof(uint32_t)); | |
316 | } | |
f55b32e7 MF |
317 | if (initrd_filename) { |
318 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
319 | } | |
a9a28591 | 320 | |
292627bb | 321 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
322 | tagptr = (tagptr - bp_size) & ~0xff; |
323 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
324 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
325 | sizeof(memory_location), &memory_location); | |
a9a28591 | 326 | |
292627bb | 327 | if (kernel_cmdline) { |
a9a28591 MF |
328 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
329 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 330 | } |
0e80359e | 331 | #ifdef CONFIG_FDT |
996dfe98 MF |
332 | if (dtb_filename) { |
333 | int fdt_size; | |
334 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
335 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
336 | ||
337 | if (!fdt) { | |
ebbb419a | 338 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
339 | exit(EXIT_FAILURE); |
340 | } | |
341 | ||
342 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
343 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
344 | sizeof(dtb_addr), &dtb_addr); | |
345 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); | |
346 | } | |
0e80359e MF |
347 | #else |
348 | if (dtb_filename) { | |
349 | error_report("could not load DTB '%s': " | |
350 | "FDT support is not configured in QEMU", | |
351 | dtb_filename); | |
352 | exit(EXIT_FAILURE); | |
353 | } | |
354 | #endif | |
f55b32e7 MF |
355 | if (initrd_filename) { |
356 | BpMemInfo initrd_location = { 0 }; | |
357 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
358 | lowmem_end - cur_lowmem); | |
359 | ||
360 | if (initrd_size < 0) { | |
361 | initrd_size = load_image_targphys(initrd_filename, | |
362 | cur_lowmem, | |
363 | lowmem_end - cur_lowmem); | |
364 | } | |
365 | if (initrd_size < 0) { | |
ebbb419a | 366 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
367 | exit(EXIT_FAILURE); |
368 | } | |
369 | initrd_location.start = tswap32(cur_lowmem); | |
370 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
371 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
372 | sizeof(initrd_location), &initrd_location); | |
373 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); | |
374 | } | |
a9a28591 MF |
375 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
376 | env->regs[2] = tagptr; | |
377 | ||
0200db65 MF |
378 | uint64_t elf_entry; |
379 | uint64_t elf_lowaddr; | |
00b941e5 | 380 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
7ef295ea | 381 | &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); |
0200db65 | 382 | if (success > 0) { |
364d4802 MF |
383 | entry_point = elf_entry; |
384 | } else { | |
385 | hwaddr ep; | |
386 | int is_linux; | |
25bda50a | 387 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 388 | translate_phys_addr, cpu); |
364d4802 MF |
389 | if (success > 0 && is_linux) { |
390 | entry_point = ep; | |
391 | } else { | |
ebbb419a | 392 | error_report("could not load kernel '%s'", |
364d4802 MF |
393 | kernel_filename); |
394 | exit(EXIT_FAILURE); | |
395 | } | |
396 | } | |
397 | if (entry_point != env->pc) { | |
339ef8fb | 398 | uint8_t boot[] = { |
364d4802 | 399 | #ifdef TARGET_WORDS_BIGENDIAN |
339ef8fb MF |
400 | 0x60, 0x00, 0x08, /* j 1f */ |
401 | 0x00, /* .literal_position */ | |
402 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
403 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
404 | /* 1: */ | |
405 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
406 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
407 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 408 | #else |
339ef8fb MF |
409 | 0x06, 0x02, 0x00, /* j 1f */ |
410 | 0x00, /* .literal_position */ | |
411 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
412 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
413 | /* 1: */ | |
414 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
415 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
416 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
417 | #endif |
418 | }; | |
339ef8fb MF |
419 | uint32_t entry_pc = tswap32(entry_point); |
420 | uint32_t entry_a2 = tswap32(tagptr); | |
421 | ||
422 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
423 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
424 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 425 | } |
82b25dc8 MF |
426 | } else { |
427 | if (flash) { | |
428 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
429 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
430 | uint32_t size = env->config->sysrom.location[0].size; |
431 | ||
740ad9f7 MF |
432 | if (board->flash->size - board->flash->boot_base < size) { |
433 | size = board->flash->size - board->flash->boot_base; | |
e53fa62c | 434 | } |
82b25dc8 | 435 | |
188ce01d | 436 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
740ad9f7 | 437 | flash_mr, board->flash->boot_base, size); |
e53fa62c MF |
438 | memory_region_add_subregion(system_memory, |
439 | env->config->sysrom.location[0].addr, | |
440 | flash_io); | |
441 | } else { | |
442 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
443 | system_memory); | |
82b25dc8 | 444 | } |
0200db65 MF |
445 | } |
446 | } | |
447 | ||
85e2d8d5 MF |
448 | static const hwaddr xtfpga_mmu_io[2] = { |
449 | 0xf0000000, | |
450 | }; | |
451 | ||
452 | static const hwaddr xtfpga_nommu_io[2] = { | |
453 | 0x90000000, | |
454 | 0x70000000, | |
455 | }; | |
456 | ||
740ad9f7 MF |
457 | static const XtfpgaFlashDesc lx60_flash = { |
458 | .base = 0x08000000, | |
459 | .size = 0x00400000, | |
460 | .sector_size = 0x10000, | |
461 | }; | |
462 | ||
188ce01d | 463 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 464 | { |
188ce01d | 465 | static const XtfpgaBoardDesc lx60_board = { |
740ad9f7 | 466 | .flash = &lx60_flash, |
82b25dc8 | 467 | .sram_size = 0x20000, |
85e2d8d5 MF |
468 | .io = xtfpga_mmu_io, |
469 | }; | |
470 | xtfpga_init(&lx60_board, machine); | |
471 | } | |
472 | ||
473 | static void xtfpga_lx60_nommu_init(MachineState *machine) | |
474 | { | |
475 | static const XtfpgaBoardDesc lx60_board = { | |
476 | .flash = &lx60_flash, | |
477 | .sram_size = 0x20000, | |
478 | .io = xtfpga_nommu_io, | |
82b25dc8 | 479 | }; |
188ce01d | 480 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
481 | } |
482 | ||
740ad9f7 MF |
483 | static const XtfpgaFlashDesc lx200_flash = { |
484 | .base = 0x08000000, | |
485 | .size = 0x01000000, | |
486 | .sector_size = 0x20000, | |
487 | }; | |
488 | ||
188ce01d | 489 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 490 | { |
188ce01d | 491 | static const XtfpgaBoardDesc lx200_board = { |
740ad9f7 | 492 | .flash = &lx200_flash, |
82b25dc8 | 493 | .sram_size = 0x2000000, |
85e2d8d5 MF |
494 | .io = xtfpga_mmu_io, |
495 | }; | |
496 | xtfpga_init(&lx200_board, machine); | |
497 | } | |
498 | ||
499 | static void xtfpga_lx200_nommu_init(MachineState *machine) | |
500 | { | |
501 | static const XtfpgaBoardDesc lx200_board = { | |
502 | .flash = &lx200_flash, | |
503 | .sram_size = 0x2000000, | |
504 | .io = xtfpga_nommu_io, | |
82b25dc8 | 505 | }; |
188ce01d | 506 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
507 | } |
508 | ||
740ad9f7 MF |
509 | static const XtfpgaFlashDesc ml605_flash = { |
510 | .base = 0x08000000, | |
511 | .size = 0x01000000, | |
512 | .sector_size = 0x20000, | |
513 | }; | |
514 | ||
188ce01d | 515 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 516 | { |
188ce01d | 517 | static const XtfpgaBoardDesc ml605_board = { |
740ad9f7 | 518 | .flash = &ml605_flash, |
e0db904d | 519 | .sram_size = 0x2000000, |
85e2d8d5 MF |
520 | .io = xtfpga_mmu_io, |
521 | }; | |
522 | xtfpga_init(&ml605_board, machine); | |
523 | } | |
524 | ||
525 | static void xtfpga_ml605_nommu_init(MachineState *machine) | |
526 | { | |
527 | static const XtfpgaBoardDesc ml605_board = { | |
528 | .flash = &ml605_flash, | |
529 | .sram_size = 0x2000000, | |
530 | .io = xtfpga_nommu_io, | |
e0db904d | 531 | }; |
188ce01d | 532 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
533 | } |
534 | ||
740ad9f7 MF |
535 | static const XtfpgaFlashDesc kc705_flash = { |
536 | .base = 0x00000000, | |
537 | .size = 0x08000000, | |
538 | .boot_base = 0x06000000, | |
539 | .sector_size = 0x20000, | |
540 | }; | |
541 | ||
188ce01d | 542 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 543 | { |
188ce01d | 544 | static const XtfpgaBoardDesc kc705_board = { |
740ad9f7 | 545 | .flash = &kc705_flash, |
e0db904d | 546 | .sram_size = 0x2000000, |
85e2d8d5 MF |
547 | .io = xtfpga_mmu_io, |
548 | }; | |
549 | xtfpga_init(&kc705_board, machine); | |
550 | } | |
551 | ||
552 | static void xtfpga_kc705_nommu_init(MachineState *machine) | |
553 | { | |
554 | static const XtfpgaBoardDesc kc705_board = { | |
555 | .flash = &kc705_flash, | |
556 | .sram_size = 0x2000000, | |
557 | .io = xtfpga_nommu_io, | |
e0db904d | 558 | }; |
188ce01d | 559 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
560 | } |
561 | ||
188ce01d | 562 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 563 | { |
8a661aea AF |
564 | MachineClass *mc = MACHINE_CLASS(oc); |
565 | ||
e264d29d | 566 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 567 | mc->init = xtfpga_lx60_init; |
e264d29d | 568 | mc->max_cpus = 4; |
f83eb10d | 569 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d | 570 | } |
0200db65 | 571 | |
188ce01d | 572 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
573 | .name = MACHINE_TYPE_NAME("lx60"), |
574 | .parent = TYPE_MACHINE, | |
188ce01d | 575 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 576 | }; |
82b25dc8 | 577 | |
85e2d8d5 MF |
578 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) |
579 | { | |
580 | MachineClass *mc = MACHINE_CLASS(oc); | |
581 | ||
a3c5e49d | 582 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
583 | mc->init = xtfpga_lx60_nommu_init; |
584 | mc->max_cpus = 4; | |
a3c5e49d | 585 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
85e2d8d5 MF |
586 | } |
587 | ||
588 | static const TypeInfo xtfpga_lx60_nommu_type = { | |
589 | .name = MACHINE_TYPE_NAME("lx60-nommu"), | |
590 | .parent = TYPE_MACHINE, | |
591 | .class_init = xtfpga_lx60_nommu_class_init, | |
592 | }; | |
593 | ||
188ce01d | 594 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 595 | { |
8a661aea AF |
596 | MachineClass *mc = MACHINE_CLASS(oc); |
597 | ||
e264d29d | 598 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 599 | mc->init = xtfpga_lx200_init; |
e264d29d | 600 | mc->max_cpus = 4; |
f83eb10d | 601 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d | 602 | } |
e0db904d | 603 | |
188ce01d | 604 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
605 | .name = MACHINE_TYPE_NAME("lx200"), |
606 | .parent = TYPE_MACHINE, | |
188ce01d | 607 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 608 | }; |
e264d29d | 609 | |
85e2d8d5 MF |
610 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) |
611 | { | |
612 | MachineClass *mc = MACHINE_CLASS(oc); | |
613 | ||
a3c5e49d | 614 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
615 | mc->init = xtfpga_lx200_nommu_init; |
616 | mc->max_cpus = 4; | |
a3c5e49d | 617 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
85e2d8d5 MF |
618 | } |
619 | ||
620 | static const TypeInfo xtfpga_lx200_nommu_type = { | |
621 | .name = MACHINE_TYPE_NAME("lx200-nommu"), | |
622 | .parent = TYPE_MACHINE, | |
623 | .class_init = xtfpga_lx200_nommu_class_init, | |
624 | }; | |
625 | ||
188ce01d | 626 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 627 | { |
8a661aea AF |
628 | MachineClass *mc = MACHINE_CLASS(oc); |
629 | ||
e264d29d | 630 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 631 | mc->init = xtfpga_ml605_init; |
e264d29d | 632 | mc->max_cpus = 4; |
f83eb10d | 633 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d EH |
634 | } |
635 | ||
188ce01d | 636 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
637 | .name = MACHINE_TYPE_NAME("ml605"), |
638 | .parent = TYPE_MACHINE, | |
188ce01d | 639 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 640 | }; |
e0db904d | 641 | |
85e2d8d5 MF |
642 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) |
643 | { | |
644 | MachineClass *mc = MACHINE_CLASS(oc); | |
645 | ||
a3c5e49d | 646 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
647 | mc->init = xtfpga_ml605_nommu_init; |
648 | mc->max_cpus = 4; | |
a3c5e49d | 649 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
85e2d8d5 MF |
650 | } |
651 | ||
652 | static const TypeInfo xtfpga_ml605_nommu_type = { | |
653 | .name = MACHINE_TYPE_NAME("ml605-nommu"), | |
654 | .parent = TYPE_MACHINE, | |
655 | .class_init = xtfpga_ml605_nommu_class_init, | |
656 | }; | |
657 | ||
188ce01d | 658 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 659 | { |
8a661aea AF |
660 | MachineClass *mc = MACHINE_CLASS(oc); |
661 | ||
e264d29d | 662 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 663 | mc->init = xtfpga_kc705_init; |
e264d29d | 664 | mc->max_cpus = 4; |
f83eb10d | 665 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
0200db65 MF |
666 | } |
667 | ||
188ce01d | 668 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
669 | .name = MACHINE_TYPE_NAME("kc705"), |
670 | .parent = TYPE_MACHINE, | |
188ce01d | 671 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
672 | }; |
673 | ||
85e2d8d5 MF |
674 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) |
675 | { | |
676 | MachineClass *mc = MACHINE_CLASS(oc); | |
677 | ||
a3c5e49d | 678 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
85e2d8d5 MF |
679 | mc->init = xtfpga_kc705_nommu_init; |
680 | mc->max_cpus = 4; | |
a3c5e49d | 681 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
85e2d8d5 MF |
682 | } |
683 | ||
684 | static const TypeInfo xtfpga_kc705_nommu_type = { | |
685 | .name = MACHINE_TYPE_NAME("kc705-nommu"), | |
686 | .parent = TYPE_MACHINE, | |
687 | .class_init = xtfpga_kc705_nommu_class_init, | |
688 | }; | |
689 | ||
188ce01d | 690 | static void xtfpga_machines_init(void) |
8a661aea | 691 | { |
188ce01d MF |
692 | type_register_static(&xtfpga_lx60_type); |
693 | type_register_static(&xtfpga_lx200_type); | |
694 | type_register_static(&xtfpga_ml605_type); | |
695 | type_register_static(&xtfpga_kc705_type); | |
85e2d8d5 MF |
696 | type_register_static(&xtfpga_lx60_nommu_type); |
697 | type_register_static(&xtfpga_lx200_nommu_type); | |
698 | type_register_static(&xtfpga_ml605_nommu_type); | |
699 | type_register_static(&xtfpga_kc705_nommu_type); | |
8a661aea AF |
700 | } |
701 | ||
188ce01d | 702 | type_init(xtfpga_machines_init) |