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memory: dispatch unassigned accesses based on .valid.accepts
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CommitLineData
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1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
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12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
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14 */
15
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16#include "exec/memory.h"
17#include "exec/address-spaces.h"
18#include "exec/ioport.h"
1de7afc9 19#include "qemu/bitops.h"
9c17d615 20#include "sysemu/kvm.h"
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21#include <assert.h>
22
022c62cb 23#include "exec/memory-internal.h"
67d95c15 24
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25static unsigned memory_region_transaction_depth;
26static bool memory_region_update_pending;
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27static bool global_dirty_log = false;
28
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29static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
30 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
4ef4db86 31
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32static QTAILQ_HEAD(, AddressSpace) address_spaces
33 = QTAILQ_HEAD_INITIALIZER(address_spaces);
34
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35typedef struct AddrRange AddrRange;
36
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37/*
38 * Note using signed integers limits us to physical addresses at most
39 * 63 bits wide. They are needed for negative offsetting in aliases
40 * (large MemoryRegion::alias_offset).
41 */
093bc2cd 42struct AddrRange {
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43 Int128 start;
44 Int128 size;
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45};
46
08dafab4 47static AddrRange addrrange_make(Int128 start, Int128 size)
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48{
49 return (AddrRange) { start, size };
50}
51
52static bool addrrange_equal(AddrRange r1, AddrRange r2)
53{
08dafab4 54 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
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55}
56
08dafab4 57static Int128 addrrange_end(AddrRange r)
093bc2cd 58{
08dafab4 59 return int128_add(r.start, r.size);
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60}
61
08dafab4 62static AddrRange addrrange_shift(AddrRange range, Int128 delta)
093bc2cd 63{
08dafab4 64 int128_addto(&range.start, delta);
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65 return range;
66}
67
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68static bool addrrange_contains(AddrRange range, Int128 addr)
69{
70 return int128_ge(addr, range.start)
71 && int128_lt(addr, addrrange_end(range));
72}
73
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74static bool addrrange_intersects(AddrRange r1, AddrRange r2)
75{
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76 return addrrange_contains(r1, r2.start)
77 || addrrange_contains(r2, r1.start);
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78}
79
80static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
81{
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82 Int128 start = int128_max(r1.start, r2.start);
83 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
84 return addrrange_make(start, int128_sub(end, start));
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85}
86
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87enum ListenerDirection { Forward, Reverse };
88
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89static bool memory_listener_match(MemoryListener *listener,
90 MemoryRegionSection *section)
91{
92 return !listener->address_space_filter
93 || listener->address_space_filter == section->address_space;
94}
95
96#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
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97 do { \
98 MemoryListener *_listener; \
99 \
100 switch (_direction) { \
101 case Forward: \
102 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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103 if (_listener->_callback) { \
104 _listener->_callback(_listener, ##_args); \
105 } \
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106 } \
107 break; \
108 case Reverse: \
109 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
110 memory_listeners, link) { \
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111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
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114 } \
115 break; \
116 default: \
117 abort(); \
118 } \
119 } while (0)
120
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121#define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \
122 do { \
123 MemoryListener *_listener; \
124 \
125 switch (_direction) { \
126 case Forward: \
127 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
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128 if (_listener->_callback \
129 && memory_listener_match(_listener, _section)) { \
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130 _listener->_callback(_listener, _section, ##_args); \
131 } \
132 } \
133 break; \
134 case Reverse: \
135 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
136 memory_listeners, link) { \
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137 if (_listener->_callback \
138 && memory_listener_match(_listener, _section)) { \
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139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 default: \
144 abort(); \
145 } \
146 } while (0)
147
0e0d36b4 148#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \
7376e582 149 MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
0e0d36b4 150 .mr = (fr)->mr, \
f6790af6 151 .address_space = (as), \
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152 .offset_within_region = (fr)->offset_in_region, \
153 .size = int128_get64((fr)->addr.size), \
154 .offset_within_address_space = int128_get64((fr)->addr.start), \
7a8499e8 155 .readonly = (fr)->readonly, \
7376e582 156 }))
0e0d36b4 157
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158struct CoalescedMemoryRange {
159 AddrRange addr;
160 QTAILQ_ENTRY(CoalescedMemoryRange) link;
161};
162
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163struct MemoryRegionIoeventfd {
164 AddrRange addr;
165 bool match_data;
166 uint64_t data;
753d5e14 167 EventNotifier *e;
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168};
169
170static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
171 MemoryRegionIoeventfd b)
172{
08dafab4 173 if (int128_lt(a.addr.start, b.addr.start)) {
3e9d69e7 174 return true;
08dafab4 175 } else if (int128_gt(a.addr.start, b.addr.start)) {
3e9d69e7 176 return false;
08dafab4 177 } else if (int128_lt(a.addr.size, b.addr.size)) {
3e9d69e7 178 return true;
08dafab4 179 } else if (int128_gt(a.addr.size, b.addr.size)) {
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180 return false;
181 } else if (a.match_data < b.match_data) {
182 return true;
183 } else if (a.match_data > b.match_data) {
184 return false;
185 } else if (a.match_data) {
186 if (a.data < b.data) {
187 return true;
188 } else if (a.data > b.data) {
189 return false;
190 }
191 }
753d5e14 192 if (a.e < b.e) {
3e9d69e7 193 return true;
753d5e14 194 } else if (a.e > b.e) {
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195 return false;
196 }
197 return false;
198}
199
200static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
201 MemoryRegionIoeventfd b)
202{
203 return !memory_region_ioeventfd_before(a, b)
204 && !memory_region_ioeventfd_before(b, a);
205}
206
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207typedef struct FlatRange FlatRange;
208typedef struct FlatView FlatView;
209
210/* Range of memory in the global map. Addresses are absolute. */
211struct FlatRange {
212 MemoryRegion *mr;
a8170e5e 213 hwaddr offset_in_region;
093bc2cd 214 AddrRange addr;
5a583347 215 uint8_t dirty_log_mask;
5f9a5ea1 216 bool romd_mode;
fb1cd6f9 217 bool readonly;
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218};
219
220/* Flattened global view of current active memory hierarchy. Kept in sorted
221 * order.
222 */
223struct FlatView {
224 FlatRange *ranges;
225 unsigned nr;
226 unsigned nr_allocated;
227};
228
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229typedef struct AddressSpaceOps AddressSpaceOps;
230
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231#define FOR_EACH_FLAT_RANGE(var, view) \
232 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
233
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234static bool flatrange_equal(FlatRange *a, FlatRange *b)
235{
236 return a->mr == b->mr
237 && addrrange_equal(a->addr, b->addr)
d0a9b5bc 238 && a->offset_in_region == b->offset_in_region
5f9a5ea1 239 && a->romd_mode == b->romd_mode
fb1cd6f9 240 && a->readonly == b->readonly;
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241}
242
243static void flatview_init(FlatView *view)
244{
245 view->ranges = NULL;
246 view->nr = 0;
247 view->nr_allocated = 0;
248}
249
250/* Insert a range into a given position. Caller is responsible for maintaining
251 * sorting order.
252 */
253static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
254{
255 if (view->nr == view->nr_allocated) {
256 view->nr_allocated = MAX(2 * view->nr, 10);
7267c094 257 view->ranges = g_realloc(view->ranges,
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258 view->nr_allocated * sizeof(*view->ranges));
259 }
260 memmove(view->ranges + pos + 1, view->ranges + pos,
261 (view->nr - pos) * sizeof(FlatRange));
262 view->ranges[pos] = *range;
263 ++view->nr;
264}
265
266static void flatview_destroy(FlatView *view)
267{
7267c094 268 g_free(view->ranges);
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269}
270
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271static bool can_merge(FlatRange *r1, FlatRange *r2)
272{
08dafab4 273 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
3d8e6bf9 274 && r1->mr == r2->mr
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275 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
276 r1->addr.size),
277 int128_make64(r2->offset_in_region))
d0a9b5bc 278 && r1->dirty_log_mask == r2->dirty_log_mask
5f9a5ea1 279 && r1->romd_mode == r2->romd_mode
fb1cd6f9 280 && r1->readonly == r2->readonly;
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281}
282
283/* Attempt to simplify a view by merging ajacent ranges */
284static void flatview_simplify(FlatView *view)
285{
286 unsigned i, j;
287
288 i = 0;
289 while (i < view->nr) {
290 j = i + 1;
291 while (j < view->nr
292 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
08dafab4 293 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
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294 ++j;
295 }
296 ++i;
297 memmove(&view->ranges[i], &view->ranges[j],
298 (view->nr - j) * sizeof(view->ranges[j]));
299 view->nr -= j - i;
300 }
301}
302
164a4dcd 303static void memory_region_read_accessor(void *opaque,
a8170e5e 304 hwaddr addr,
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305 uint64_t *value,
306 unsigned size,
307 unsigned shift,
308 uint64_t mask)
309{
310 MemoryRegion *mr = opaque;
311 uint64_t tmp;
312
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313 if (mr->flush_coalesced_mmio) {
314 qemu_flush_coalesced_mmio_buffer();
315 }
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316 tmp = mr->ops->read(mr->opaque, addr, size);
317 *value |= (tmp & mask) << shift;
318}
319
320static void memory_region_write_accessor(void *opaque,
a8170e5e 321 hwaddr addr,
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322 uint64_t *value,
323 unsigned size,
324 unsigned shift,
325 uint64_t mask)
326{
327 MemoryRegion *mr = opaque;
328 uint64_t tmp;
329
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330 if (mr->flush_coalesced_mmio) {
331 qemu_flush_coalesced_mmio_buffer();
332 }
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333 tmp = (*value >> shift) & mask;
334 mr->ops->write(mr->opaque, addr, tmp, size);
335}
336
a8170e5e 337static void access_with_adjusted_size(hwaddr addr,
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338 uint64_t *value,
339 unsigned size,
340 unsigned access_size_min,
341 unsigned access_size_max,
342 void (*access)(void *opaque,
a8170e5e 343 hwaddr addr,
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344 uint64_t *value,
345 unsigned size,
346 unsigned shift,
347 uint64_t mask),
348 void *opaque)
349{
350 uint64_t access_mask;
351 unsigned access_size;
352 unsigned i;
353
354 if (!access_size_min) {
355 access_size_min = 1;
356 }
357 if (!access_size_max) {
358 access_size_max = 4;
359 }
360 access_size = MAX(MIN(size, access_size_max), access_size_min);
361 access_mask = -1ULL >> (64 - access_size * 8);
362 for (i = 0; i < size; i += access_size) {
363 /* FIXME: big-endian support */
364 access(opaque, addr + i, value, access_size, i * 8, access_mask);
365 }
366}
367
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368static const MemoryRegionPortio *find_portio(MemoryRegion *mr, uint64_t offset,
369 unsigned width, bool write)
370{
371 const MemoryRegionPortio *mrp;
372
373 for (mrp = mr->ops->old_portio; mrp->size; ++mrp) {
374 if (offset >= mrp->offset && offset < mrp->offset + mrp->len
375 && width == mrp->size
376 && (write ? (bool)mrp->write : (bool)mrp->read)) {
377 return mrp;
378 }
379 }
380 return NULL;
381}
382
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383static void memory_region_iorange_read(IORange *iorange,
384 uint64_t offset,
385 unsigned width,
386 uint64_t *data)
387{
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388 MemoryRegionIORange *mrio
389 = container_of(iorange, MemoryRegionIORange, iorange);
390 MemoryRegion *mr = mrio->mr;
658b2224 391
a2d33521 392 offset += mrio->offset;
627a0e90 393 if (mr->ops->old_portio) {
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394 const MemoryRegionPortio *mrp = find_portio(mr, offset - mrio->offset,
395 width, false);
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396
397 *data = ((uint64_t)1 << (width * 8)) - 1;
398 if (mrp) {
2b50aa1f 399 *data = mrp->read(mr->opaque, offset);
03808f58 400 } else if (width == 2) {
a2d33521 401 mrp = find_portio(mr, offset - mrio->offset, 1, false);
03808f58 402 assert(mrp);
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403 *data = mrp->read(mr->opaque, offset) |
404 (mrp->read(mr->opaque, offset + 1) << 8);
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405 }
406 return;
407 }
3a130f4e 408 *data = 0;
2b50aa1f 409 access_with_adjusted_size(offset, data, width,
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410 mr->ops->impl.min_access_size,
411 mr->ops->impl.max_access_size,
412 memory_region_read_accessor, mr);
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413}
414
415static void memory_region_iorange_write(IORange *iorange,
416 uint64_t offset,
417 unsigned width,
418 uint64_t data)
419{
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420 MemoryRegionIORange *mrio
421 = container_of(iorange, MemoryRegionIORange, iorange);
422 MemoryRegion *mr = mrio->mr;
658b2224 423
a2d33521 424 offset += mrio->offset;
627a0e90 425 if (mr->ops->old_portio) {
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426 const MemoryRegionPortio *mrp = find_portio(mr, offset - mrio->offset,
427 width, true);
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428
429 if (mrp) {
2b50aa1f 430 mrp->write(mr->opaque, offset, data);
03808f58 431 } else if (width == 2) {
7e2a62d8 432 mrp = find_portio(mr, offset - mrio->offset, 1, true);
03808f58 433 assert(mrp);
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434 mrp->write(mr->opaque, offset, data & 0xff);
435 mrp->write(mr->opaque, offset + 1, data >> 8);
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436 }
437 return;
438 }
2b50aa1f 439 access_with_adjusted_size(offset, &data, width,
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440 mr->ops->impl.min_access_size,
441 mr->ops->impl.max_access_size,
442 memory_region_write_accessor, mr);
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443}
444
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445static void memory_region_iorange_destructor(IORange *iorange)
446{
447 g_free(container_of(iorange, MemoryRegionIORange, iorange));
448}
449
93632747 450const IORangeOps memory_region_iorange_ops = {
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451 .read = memory_region_iorange_read,
452 .write = memory_region_iorange_write,
a2d33521 453 .destructor = memory_region_iorange_destructor,
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454};
455
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456static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
457{
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458 AddressSpace *as;
459
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460 while (mr->parent) {
461 mr = mr->parent;
462 }
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463 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
464 if (mr == as->root) {
465 return as;
466 }
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467 }
468 abort();
469}
470
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471/* Render a memory region into the global view. Ranges in @view obscure
472 * ranges in @mr.
473 */
474static void render_memory_region(FlatView *view,
475 MemoryRegion *mr,
08dafab4 476 Int128 base,
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477 AddrRange clip,
478 bool readonly)
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479{
480 MemoryRegion *subregion;
481 unsigned i;
a8170e5e 482 hwaddr offset_in_region;
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483 Int128 remain;
484 Int128 now;
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485 FlatRange fr;
486 AddrRange tmp;
487
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488 if (!mr->enabled) {
489 return;
490 }
491
08dafab4 492 int128_addto(&base, int128_make64(mr->addr));
fb1cd6f9 493 readonly |= mr->readonly;
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494
495 tmp = addrrange_make(base, mr->size);
496
497 if (!addrrange_intersects(tmp, clip)) {
498 return;
499 }
500
501 clip = addrrange_intersection(tmp, clip);
502
503 if (mr->alias) {
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504 int128_subfrom(&base, int128_make64(mr->alias->addr));
505 int128_subfrom(&base, int128_make64(mr->alias_offset));
fb1cd6f9 506 render_memory_region(view, mr->alias, base, clip, readonly);
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507 return;
508 }
509
510 /* Render subregions in priority order. */
511 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
fb1cd6f9 512 render_memory_region(view, subregion, base, clip, readonly);
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513 }
514
14a3c10a 515 if (!mr->terminates) {
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516 return;
517 }
518
08dafab4 519 offset_in_region = int128_get64(int128_sub(clip.start, base));
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520 base = clip.start;
521 remain = clip.size;
522
523 /* Render the region itself into any gaps left by the current view. */
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524 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
525 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
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526 continue;
527 }
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528 if (int128_lt(base, view->ranges[i].addr.start)) {
529 now = int128_min(remain,
530 int128_sub(view->ranges[i].addr.start, base));
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531 fr.mr = mr;
532 fr.offset_in_region = offset_in_region;
533 fr.addr = addrrange_make(base, now);
5a583347 534 fr.dirty_log_mask = mr->dirty_log_mask;
5f9a5ea1 535 fr.romd_mode = mr->romd_mode;
fb1cd6f9 536 fr.readonly = readonly;
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537 flatview_insert(view, i, &fr);
538 ++i;
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539 int128_addto(&base, now);
540 offset_in_region += int128_get64(now);
541 int128_subfrom(&remain, now);
093bc2cd 542 }
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543 now = int128_sub(int128_min(int128_add(base, remain),
544 addrrange_end(view->ranges[i].addr)),
545 base);
546 int128_addto(&base, now);
547 offset_in_region += int128_get64(now);
548 int128_subfrom(&remain, now);
093bc2cd 549 }
08dafab4 550 if (int128_nz(remain)) {
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551 fr.mr = mr;
552 fr.offset_in_region = offset_in_region;
553 fr.addr = addrrange_make(base, remain);
5a583347 554 fr.dirty_log_mask = mr->dirty_log_mask;
5f9a5ea1 555 fr.romd_mode = mr->romd_mode;
fb1cd6f9 556 fr.readonly = readonly;
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557 flatview_insert(view, i, &fr);
558 }
559}
560
561/* Render a memory topology into a list of disjoint absolute ranges. */
562static FlatView generate_memory_topology(MemoryRegion *mr)
563{
564 FlatView view;
565
566 flatview_init(&view);
567
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568 if (mr) {
569 render_memory_region(&view, mr, int128_zero(),
570 addrrange_make(int128_zero(), int128_2_64()), false);
571 }
3d8e6bf9 572 flatview_simplify(&view);
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573
574 return view;
575}
576
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577static void address_space_add_del_ioeventfds(AddressSpace *as,
578 MemoryRegionIoeventfd *fds_new,
579 unsigned fds_new_nb,
580 MemoryRegionIoeventfd *fds_old,
581 unsigned fds_old_nb)
582{
583 unsigned iold, inew;
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584 MemoryRegionIoeventfd *fd;
585 MemoryRegionSection section;
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586
587 /* Generate a symmetric difference of the old and new fd sets, adding
588 * and deleting as necessary.
589 */
590
591 iold = inew = 0;
592 while (iold < fds_old_nb || inew < fds_new_nb) {
593 if (iold < fds_old_nb
594 && (inew == fds_new_nb
595 || memory_region_ioeventfd_before(fds_old[iold],
596 fds_new[inew]))) {
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597 fd = &fds_old[iold];
598 section = (MemoryRegionSection) {
f6790af6 599 .address_space = as,
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600 .offset_within_address_space = int128_get64(fd->addr.start),
601 .size = int128_get64(fd->addr.size),
602 };
603 MEMORY_LISTENER_CALL(eventfd_del, Forward, &section,
753d5e14 604 fd->match_data, fd->data, fd->e);
3e9d69e7
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605 ++iold;
606 } else if (inew < fds_new_nb
607 && (iold == fds_old_nb
608 || memory_region_ioeventfd_before(fds_new[inew],
609 fds_old[iold]))) {
80a1ea37
AK
610 fd = &fds_new[inew];
611 section = (MemoryRegionSection) {
f6790af6 612 .address_space = as,
80a1ea37
AK
613 .offset_within_address_space = int128_get64(fd->addr.start),
614 .size = int128_get64(fd->addr.size),
615 };
616 MEMORY_LISTENER_CALL(eventfd_add, Reverse, &section,
753d5e14 617 fd->match_data, fd->data, fd->e);
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AK
618 ++inew;
619 } else {
620 ++iold;
621 ++inew;
622 }
623 }
624}
625
626static void address_space_update_ioeventfds(AddressSpace *as)
627{
628 FlatRange *fr;
629 unsigned ioeventfd_nb = 0;
630 MemoryRegionIoeventfd *ioeventfds = NULL;
631 AddrRange tmp;
632 unsigned i;
633
8786db7c 634 FOR_EACH_FLAT_RANGE(fr, as->current_map) {
3e9d69e7
AK
635 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
636 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
08dafab4
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637 int128_sub(fr->addr.start,
638 int128_make64(fr->offset_in_region)));
3e9d69e7
AK
639 if (addrrange_intersects(fr->addr, tmp)) {
640 ++ioeventfd_nb;
7267c094 641 ioeventfds = g_realloc(ioeventfds,
3e9d69e7
AK
642 ioeventfd_nb * sizeof(*ioeventfds));
643 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
644 ioeventfds[ioeventfd_nb-1].addr = tmp;
645 }
646 }
647 }
648
649 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
650 as->ioeventfds, as->ioeventfd_nb);
651
7267c094 652 g_free(as->ioeventfds);
3e9d69e7
AK
653 as->ioeventfds = ioeventfds;
654 as->ioeventfd_nb = ioeventfd_nb;
655}
656
b8af1afb
AK
657static void address_space_update_topology_pass(AddressSpace *as,
658 FlatView old_view,
659 FlatView new_view,
660 bool adding)
093bc2cd 661{
093bc2cd
AK
662 unsigned iold, inew;
663 FlatRange *frold, *frnew;
093bc2cd
AK
664
665 /* Generate a symmetric difference of the old and new memory maps.
666 * Kill ranges in the old map, and instantiate ranges in the new map.
667 */
668 iold = inew = 0;
669 while (iold < old_view.nr || inew < new_view.nr) {
670 if (iold < old_view.nr) {
671 frold = &old_view.ranges[iold];
672 } else {
673 frold = NULL;
674 }
675 if (inew < new_view.nr) {
676 frnew = &new_view.ranges[inew];
677 } else {
678 frnew = NULL;
679 }
680
681 if (frold
682 && (!frnew
08dafab4
AK
683 || int128_lt(frold->addr.start, frnew->addr.start)
684 || (int128_eq(frold->addr.start, frnew->addr.start)
093bc2cd
AK
685 && !flatrange_equal(frold, frnew)))) {
686 /* In old, but (not in new, or in new but attributes changed). */
687
b8af1afb 688 if (!adding) {
72e22d2f 689 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
b8af1afb
AK
690 }
691
093bc2cd
AK
692 ++iold;
693 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
694 /* In both (logging may have changed) */
695
b8af1afb 696 if (adding) {
50c1e149 697 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
b8af1afb 698 if (frold->dirty_log_mask && !frnew->dirty_log_mask) {
72e22d2f 699 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop);
b8af1afb 700 } else if (frnew->dirty_log_mask && !frold->dirty_log_mask) {
72e22d2f 701 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start);
b8af1afb 702 }
5a583347
AK
703 }
704
093bc2cd
AK
705 ++iold;
706 ++inew;
093bc2cd
AK
707 } else {
708 /* In new */
709
b8af1afb 710 if (adding) {
72e22d2f 711 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
b8af1afb
AK
712 }
713
093bc2cd
AK
714 ++inew;
715 }
716 }
b8af1afb
AK
717}
718
719
720static void address_space_update_topology(AddressSpace *as)
721{
8786db7c 722 FlatView old_view = *as->current_map;
b8af1afb
AK
723 FlatView new_view = generate_memory_topology(as->root);
724
725 address_space_update_topology_pass(as, old_view, new_view, false);
726 address_space_update_topology_pass(as, old_view, new_view, true);
727
8786db7c 728 *as->current_map = new_view;
093bc2cd 729 flatview_destroy(&old_view);
3e9d69e7 730 address_space_update_ioeventfds(as);
093bc2cd
AK
731}
732
4ef4db86
AK
733void memory_region_transaction_begin(void)
734{
bb880ded 735 qemu_flush_coalesced_mmio_buffer();
4ef4db86
AK
736 ++memory_region_transaction_depth;
737}
738
739void memory_region_transaction_commit(void)
740{
0d673e36
AK
741 AddressSpace *as;
742
4ef4db86
AK
743 assert(memory_region_transaction_depth);
744 --memory_region_transaction_depth;
22bde714
JK
745 if (!memory_region_transaction_depth && memory_region_update_pending) {
746 memory_region_update_pending = false;
02e2b95f
JK
747 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
748
0d673e36
AK
749 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
750 address_space_update_topology(as);
02e2b95f
JK
751 }
752
753 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
e87c099f 754 }
4ef4db86
AK
755}
756
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AK
757static void memory_region_destructor_none(MemoryRegion *mr)
758{
759}
760
761static void memory_region_destructor_ram(MemoryRegion *mr)
762{
763 qemu_ram_free(mr->ram_addr);
764}
765
766static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
767{
768 qemu_ram_free_from_ptr(mr->ram_addr);
769}
770
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AK
771static void memory_region_destructor_rom_device(MemoryRegion *mr)
772{
773 qemu_ram_free(mr->ram_addr & TARGET_PAGE_MASK);
d0a9b5bc
AK
774}
775
be675c97
AK
776static bool memory_region_wrong_endianness(MemoryRegion *mr)
777{
2c3579ab 778#ifdef TARGET_WORDS_BIGENDIAN
be675c97
AK
779 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
780#else
781 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
782#endif
783}
784
093bc2cd
AK
785void memory_region_init(MemoryRegion *mr,
786 const char *name,
787 uint64_t size)
788{
789 mr->ops = NULL;
790 mr->parent = NULL;
08dafab4
AK
791 mr->size = int128_make64(size);
792 if (size == UINT64_MAX) {
793 mr->size = int128_2_64();
794 }
093bc2cd 795 mr->addr = 0;
b3b00c78 796 mr->subpage = false;
6bba19ba 797 mr->enabled = true;
14a3c10a 798 mr->terminates = false;
8ea9252a 799 mr->ram = false;
5f9a5ea1 800 mr->romd_mode = true;
fb1cd6f9 801 mr->readonly = false;
75c578dc 802 mr->rom_device = false;
545e92e0 803 mr->destructor = memory_region_destructor_none;
093bc2cd
AK
804 mr->priority = 0;
805 mr->may_overlap = false;
806 mr->alias = NULL;
807 QTAILQ_INIT(&mr->subregions);
808 memset(&mr->subregions_link, 0, sizeof mr->subregions_link);
809 QTAILQ_INIT(&mr->coalesced);
7267c094 810 mr->name = g_strdup(name);
5a583347 811 mr->dirty_log_mask = 0;
3e9d69e7
AK
812 mr->ioeventfd_nb = 0;
813 mr->ioeventfds = NULL;
d410515e 814 mr->flush_coalesced_mmio = false;
093bc2cd
AK
815}
816
b018ddf6
PB
817static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
818 unsigned size)
819{
820#ifdef DEBUG_UNASSIGNED
821 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
822#endif
823#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
824 cpu_unassigned_access(cpu_single_env, addr, 0, 0, 0, size);
825#endif
826 return 0;
827}
828
829static void unassigned_mem_write(void *opaque, hwaddr addr,
830 uint64_t val, unsigned size)
831{
832#ifdef DEBUG_UNASSIGNED
833 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
834#endif
835#if defined(TARGET_ALPHA) || defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
836 cpu_unassigned_access(cpu_single_env, addr, 1, 0, 0, size);
837#endif
838}
839
093bc2cd 840static bool memory_region_access_valid(MemoryRegion *mr,
a8170e5e 841 hwaddr addr,
897fa7cf
AK
842 unsigned size,
843 bool is_write)
093bc2cd 844{
897fa7cf
AK
845 if (mr->ops->valid.accepts
846 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write)) {
847 return false;
848 }
849
093bc2cd
AK
850 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
851 return false;
852 }
853
854 /* Treat zero as compatibility all valid */
855 if (!mr->ops->valid.max_access_size) {
856 return true;
857 }
858
859 if (size > mr->ops->valid.max_access_size
860 || size < mr->ops->valid.min_access_size) {
861 return false;
862 }
863 return true;
864}
865
a621f38d 866static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
a8170e5e 867 hwaddr addr,
a621f38d 868 unsigned size)
093bc2cd 869{
164a4dcd 870 uint64_t data = 0;
093bc2cd 871
897fa7cf 872 if (!memory_region_access_valid(mr, addr, size, false)) {
b018ddf6 873 return unassigned_mem_read(mr, addr, size);
093bc2cd
AK
874 }
875
74901c3b 876 if (!mr->ops->read) {
5bbf90be 877 return mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
74901c3b
AK
878 }
879
093bc2cd 880 /* FIXME: support unaligned access */
2b50aa1f 881 access_with_adjusted_size(addr, &data, size,
164a4dcd
AK
882 mr->ops->impl.min_access_size,
883 mr->ops->impl.max_access_size,
884 memory_region_read_accessor, mr);
093bc2cd
AK
885
886 return data;
887}
888
a621f38d 889static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
093bc2cd 890{
a621f38d
AK
891 if (memory_region_wrong_endianness(mr)) {
892 switch (size) {
893 case 1:
894 break;
895 case 2:
896 *data = bswap16(*data);
897 break;
898 case 4:
899 *data = bswap32(*data);
1470a0cd 900 break;
a621f38d
AK
901 default:
902 abort();
903 }
904 }
905}
906
907static uint64_t memory_region_dispatch_read(MemoryRegion *mr,
a8170e5e 908 hwaddr addr,
a621f38d
AK
909 unsigned size)
910{
911 uint64_t ret;
912
913 ret = memory_region_dispatch_read1(mr, addr, size);
914 adjust_endianness(mr, &ret, size);
915 return ret;
916}
093bc2cd 917
a621f38d 918static void memory_region_dispatch_write(MemoryRegion *mr,
a8170e5e 919 hwaddr addr,
a621f38d
AK
920 uint64_t data,
921 unsigned size)
922{
897fa7cf 923 if (!memory_region_access_valid(mr, addr, size, true)) {
b018ddf6
PB
924 unassigned_mem_write(mr, addr, data, size);
925 return;
093bc2cd
AK
926 }
927
a621f38d
AK
928 adjust_endianness(mr, &data, size);
929
74901c3b 930 if (!mr->ops->write) {
5bbf90be 931 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, data);
74901c3b
AK
932 return;
933 }
934
093bc2cd 935 /* FIXME: support unaligned access */
2b50aa1f 936 access_with_adjusted_size(addr, &data, size,
164a4dcd
AK
937 mr->ops->impl.min_access_size,
938 mr->ops->impl.max_access_size,
939 memory_region_write_accessor, mr);
093bc2cd
AK
940}
941
093bc2cd
AK
942void memory_region_init_io(MemoryRegion *mr,
943 const MemoryRegionOps *ops,
944 void *opaque,
945 const char *name,
946 uint64_t size)
947{
948 memory_region_init(mr, name, size);
949 mr->ops = ops;
950 mr->opaque = opaque;
14a3c10a 951 mr->terminates = true;
97161e17 952 mr->ram_addr = ~(ram_addr_t)0;
093bc2cd
AK
953}
954
955void memory_region_init_ram(MemoryRegion *mr,
093bc2cd
AK
956 const char *name,
957 uint64_t size)
958{
959 memory_region_init(mr, name, size);
8ea9252a 960 mr->ram = true;
14a3c10a 961 mr->terminates = true;
545e92e0 962 mr->destructor = memory_region_destructor_ram;
c5705a77 963 mr->ram_addr = qemu_ram_alloc(size, mr);
093bc2cd
AK
964}
965
966void memory_region_init_ram_ptr(MemoryRegion *mr,
093bc2cd
AK
967 const char *name,
968 uint64_t size,
969 void *ptr)
970{
971 memory_region_init(mr, name, size);
8ea9252a 972 mr->ram = true;
14a3c10a 973 mr->terminates = true;
545e92e0 974 mr->destructor = memory_region_destructor_ram_from_ptr;
c5705a77 975 mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr);
093bc2cd
AK
976}
977
978void memory_region_init_alias(MemoryRegion *mr,
979 const char *name,
980 MemoryRegion *orig,
a8170e5e 981 hwaddr offset,
093bc2cd
AK
982 uint64_t size)
983{
984 memory_region_init(mr, name, size);
985 mr->alias = orig;
986 mr->alias_offset = offset;
987}
988
d0a9b5bc
AK
989void memory_region_init_rom_device(MemoryRegion *mr,
990 const MemoryRegionOps *ops,
75f5941c 991 void *opaque,
d0a9b5bc
AK
992 const char *name,
993 uint64_t size)
994{
995 memory_region_init(mr, name, size);
7bc2b9cd 996 mr->ops = ops;
75f5941c 997 mr->opaque = opaque;
d0a9b5bc 998 mr->terminates = true;
75c578dc 999 mr->rom_device = true;
d0a9b5bc 1000 mr->destructor = memory_region_destructor_rom_device;
c5705a77 1001 mr->ram_addr = qemu_ram_alloc(size, mr);
d0a9b5bc
AK
1002}
1003
a8170e5e 1004static uint64_t invalid_read(void *opaque, hwaddr addr,
1660e72d
JK
1005 unsigned size)
1006{
1007 MemoryRegion *mr = opaque;
1008
1009 if (!mr->warning_printed) {
1010 fprintf(stderr, "Invalid read from memory region %s\n", mr->name);
1011 mr->warning_printed = true;
1012 }
1013 return -1U;
1014}
1015
a8170e5e 1016static void invalid_write(void *opaque, hwaddr addr, uint64_t data,
1660e72d
JK
1017 unsigned size)
1018{
1019 MemoryRegion *mr = opaque;
1020
1021 if (!mr->warning_printed) {
1022 fprintf(stderr, "Invalid write to memory region %s\n", mr->name);
1023 mr->warning_printed = true;
1024 }
1025}
1026
1027static const MemoryRegionOps reservation_ops = {
1028 .read = invalid_read,
1029 .write = invalid_write,
1030 .endianness = DEVICE_NATIVE_ENDIAN,
1031};
1032
1033void memory_region_init_reservation(MemoryRegion *mr,
1034 const char *name,
1035 uint64_t size)
1036{
1037 memory_region_init_io(mr, &reservation_ops, mr, name, size);
1038}
1039
093bc2cd
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1040void memory_region_destroy(MemoryRegion *mr)
1041{
1042 assert(QTAILQ_EMPTY(&mr->subregions));
2be0e25f 1043 assert(memory_region_transaction_depth == 0);
545e92e0 1044 mr->destructor(mr);
093bc2cd 1045 memory_region_clear_coalescing(mr);
7267c094
AL
1046 g_free((char *)mr->name);
1047 g_free(mr->ioeventfds);
093bc2cd
AK
1048}
1049
1050uint64_t memory_region_size(MemoryRegion *mr)
1051{
08dafab4
AK
1052 if (int128_eq(mr->size, int128_2_64())) {
1053 return UINT64_MAX;
1054 }
1055 return int128_get64(mr->size);
093bc2cd
AK
1056}
1057
8991c79b
AK
1058const char *memory_region_name(MemoryRegion *mr)
1059{
1060 return mr->name;
1061}
1062
8ea9252a
AK
1063bool memory_region_is_ram(MemoryRegion *mr)
1064{
1065 return mr->ram;
1066}
1067
55043ba3
AK
1068bool memory_region_is_logging(MemoryRegion *mr)
1069{
1070 return mr->dirty_log_mask;
1071}
1072
ce7923da
AK
1073bool memory_region_is_rom(MemoryRegion *mr)
1074{
1075 return mr->ram && mr->readonly;
1076}
1077
093bc2cd
AK
1078void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1079{
5a583347
AK
1080 uint8_t mask = 1 << client;
1081
59023ef4 1082 memory_region_transaction_begin();
5a583347 1083 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
22bde714 1084 memory_region_update_pending |= mr->enabled;
59023ef4 1085 memory_region_transaction_commit();
093bc2cd
AK
1086}
1087
a8170e5e
AK
1088bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1089 hwaddr size, unsigned client)
093bc2cd 1090{
14a3c10a 1091 assert(mr->terminates);
cd7a45c9
BS
1092 return cpu_physical_memory_get_dirty(mr->ram_addr + addr, size,
1093 1 << client);
093bc2cd
AK
1094}
1095
a8170e5e
AK
1096void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1097 hwaddr size)
093bc2cd 1098{
14a3c10a 1099 assert(mr->terminates);
fd4aa979 1100 return cpu_physical_memory_set_dirty_range(mr->ram_addr + addr, size, -1);
093bc2cd
AK
1101}
1102
6c279db8
JQ
1103bool memory_region_test_and_clear_dirty(MemoryRegion *mr, hwaddr addr,
1104 hwaddr size, unsigned client)
1105{
1106 bool ret;
1107 assert(mr->terminates);
1108 ret = cpu_physical_memory_get_dirty(mr->ram_addr + addr, size,
1109 1 << client);
1110 if (ret) {
1111 cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
1112 mr->ram_addr + addr + size,
1113 1 << client);
1114 }
1115 return ret;
1116}
1117
1118
093bc2cd
AK
1119void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1120{
0d673e36 1121 AddressSpace *as;
5a583347
AK
1122 FlatRange *fr;
1123
0d673e36
AK
1124 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1125 FOR_EACH_FLAT_RANGE(fr, as->current_map) {
1126 if (fr->mr == mr) {
1127 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
1128 }
5a583347
AK
1129 }
1130 }
093bc2cd
AK
1131}
1132
1133void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
1134{
fb1cd6f9 1135 if (mr->readonly != readonly) {
59023ef4 1136 memory_region_transaction_begin();
fb1cd6f9 1137 mr->readonly = readonly;
22bde714 1138 memory_region_update_pending |= mr->enabled;
59023ef4 1139 memory_region_transaction_commit();
fb1cd6f9 1140 }
093bc2cd
AK
1141}
1142
5f9a5ea1 1143void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
d0a9b5bc 1144{
5f9a5ea1 1145 if (mr->romd_mode != romd_mode) {
59023ef4 1146 memory_region_transaction_begin();
5f9a5ea1 1147 mr->romd_mode = romd_mode;
22bde714 1148 memory_region_update_pending |= mr->enabled;
59023ef4 1149 memory_region_transaction_commit();
d0a9b5bc
AK
1150 }
1151}
1152
a8170e5e
AK
1153void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
1154 hwaddr size, unsigned client)
093bc2cd 1155{
14a3c10a 1156 assert(mr->terminates);
5a583347
AK
1157 cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
1158 mr->ram_addr + addr + size,
1159 1 << client);
093bc2cd
AK
1160}
1161
1162void *memory_region_get_ram_ptr(MemoryRegion *mr)
1163{
1164 if (mr->alias) {
1165 return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset;
1166 }
1167
14a3c10a 1168 assert(mr->terminates);
093bc2cd 1169
021d26d1 1170 return qemu_get_ram_ptr(mr->ram_addr & TARGET_PAGE_MASK);
093bc2cd
AK
1171}
1172
0d673e36 1173static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
093bc2cd
AK
1174{
1175 FlatRange *fr;
1176 CoalescedMemoryRange *cmr;
1177 AddrRange tmp;
95d2994a 1178 MemoryRegionSection section;
093bc2cd 1179
0d673e36 1180 FOR_EACH_FLAT_RANGE(fr, as->current_map) {
093bc2cd 1181 if (fr->mr == mr) {
95d2994a 1182 section = (MemoryRegionSection) {
f6790af6 1183 .address_space = as,
95d2994a
AK
1184 .offset_within_address_space = int128_get64(fr->addr.start),
1185 .size = int128_get64(fr->addr.size),
1186 };
1187
1188 MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, &section,
1189 int128_get64(fr->addr.start),
1190 int128_get64(fr->addr.size));
093bc2cd
AK
1191 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
1192 tmp = addrrange_shift(cmr->addr,
08dafab4
AK
1193 int128_sub(fr->addr.start,
1194 int128_make64(fr->offset_in_region)));
093bc2cd
AK
1195 if (!addrrange_intersects(tmp, fr->addr)) {
1196 continue;
1197 }
1198 tmp = addrrange_intersection(tmp, fr->addr);
95d2994a
AK
1199 MEMORY_LISTENER_CALL(coalesced_mmio_add, Forward, &section,
1200 int128_get64(tmp.start),
1201 int128_get64(tmp.size));
093bc2cd
AK
1202 }
1203 }
1204 }
1205}
1206
0d673e36
AK
1207static void memory_region_update_coalesced_range(MemoryRegion *mr)
1208{
1209 AddressSpace *as;
1210
1211 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1212 memory_region_update_coalesced_range_as(mr, as);
1213 }
1214}
1215
093bc2cd
AK
1216void memory_region_set_coalescing(MemoryRegion *mr)
1217{
1218 memory_region_clear_coalescing(mr);
08dafab4 1219 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
093bc2cd
AK
1220}
1221
1222void memory_region_add_coalescing(MemoryRegion *mr,
a8170e5e 1223 hwaddr offset,
093bc2cd
AK
1224 uint64_t size)
1225{
7267c094 1226 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
093bc2cd 1227
08dafab4 1228 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
093bc2cd
AK
1229 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
1230 memory_region_update_coalesced_range(mr);
d410515e 1231 memory_region_set_flush_coalesced(mr);
093bc2cd
AK
1232}
1233
1234void memory_region_clear_coalescing(MemoryRegion *mr)
1235{
1236 CoalescedMemoryRange *cmr;
1237
d410515e
JK
1238 qemu_flush_coalesced_mmio_buffer();
1239 mr->flush_coalesced_mmio = false;
1240
093bc2cd
AK
1241 while (!QTAILQ_EMPTY(&mr->coalesced)) {
1242 cmr = QTAILQ_FIRST(&mr->coalesced);
1243 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
7267c094 1244 g_free(cmr);
093bc2cd
AK
1245 }
1246 memory_region_update_coalesced_range(mr);
1247}
1248
d410515e
JK
1249void memory_region_set_flush_coalesced(MemoryRegion *mr)
1250{
1251 mr->flush_coalesced_mmio = true;
1252}
1253
1254void memory_region_clear_flush_coalesced(MemoryRegion *mr)
1255{
1256 qemu_flush_coalesced_mmio_buffer();
1257 if (QTAILQ_EMPTY(&mr->coalesced)) {
1258 mr->flush_coalesced_mmio = false;
1259 }
1260}
1261
3e9d69e7 1262void memory_region_add_eventfd(MemoryRegion *mr,
a8170e5e 1263 hwaddr addr,
3e9d69e7
AK
1264 unsigned size,
1265 bool match_data,
1266 uint64_t data,
753d5e14 1267 EventNotifier *e)
3e9d69e7
AK
1268{
1269 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1270 .addr.start = int128_make64(addr),
1271 .addr.size = int128_make64(size),
3e9d69e7
AK
1272 .match_data = match_data,
1273 .data = data,
753d5e14 1274 .e = e,
3e9d69e7
AK
1275 };
1276 unsigned i;
1277
28f362be 1278 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1279 memory_region_transaction_begin();
3e9d69e7
AK
1280 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1281 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
1282 break;
1283 }
1284 }
1285 ++mr->ioeventfd_nb;
7267c094 1286 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7
AK
1287 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
1288 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
1289 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
1290 mr->ioeventfds[i] = mrfd;
22bde714 1291 memory_region_update_pending |= mr->enabled;
59023ef4 1292 memory_region_transaction_commit();
3e9d69e7
AK
1293}
1294
1295void memory_region_del_eventfd(MemoryRegion *mr,
a8170e5e 1296 hwaddr addr,
3e9d69e7
AK
1297 unsigned size,
1298 bool match_data,
1299 uint64_t data,
753d5e14 1300 EventNotifier *e)
3e9d69e7
AK
1301{
1302 MemoryRegionIoeventfd mrfd = {
08dafab4
AK
1303 .addr.start = int128_make64(addr),
1304 .addr.size = int128_make64(size),
3e9d69e7
AK
1305 .match_data = match_data,
1306 .data = data,
753d5e14 1307 .e = e,
3e9d69e7
AK
1308 };
1309 unsigned i;
1310
28f362be 1311 adjust_endianness(mr, &mrfd.data, size);
59023ef4 1312 memory_region_transaction_begin();
3e9d69e7
AK
1313 for (i = 0; i < mr->ioeventfd_nb; ++i) {
1314 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
1315 break;
1316 }
1317 }
1318 assert(i != mr->ioeventfd_nb);
1319 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
1320 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
1321 --mr->ioeventfd_nb;
7267c094 1322 mr->ioeventfds = g_realloc(mr->ioeventfds,
3e9d69e7 1323 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
22bde714 1324 memory_region_update_pending |= mr->enabled;
59023ef4 1325 memory_region_transaction_commit();
3e9d69e7
AK
1326}
1327
093bc2cd 1328static void memory_region_add_subregion_common(MemoryRegion *mr,
a8170e5e 1329 hwaddr offset,
093bc2cd
AK
1330 MemoryRegion *subregion)
1331{
1332 MemoryRegion *other;
1333
59023ef4
JK
1334 memory_region_transaction_begin();
1335
093bc2cd
AK
1336 assert(!subregion->parent);
1337 subregion->parent = mr;
1338 subregion->addr = offset;
1339 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1340 if (subregion->may_overlap || other->may_overlap) {
1341 continue;
1342 }
2c7cfd65 1343 if (int128_ge(int128_make64(offset),
08dafab4
AK
1344 int128_add(int128_make64(other->addr), other->size))
1345 || int128_le(int128_add(int128_make64(offset), subregion->size),
1346 int128_make64(other->addr))) {
093bc2cd
AK
1347 continue;
1348 }
a5e1cbc8 1349#if 0
860329b2
MW
1350 printf("warning: subregion collision %llx/%llx (%s) "
1351 "vs %llx/%llx (%s)\n",
093bc2cd 1352 (unsigned long long)offset,
08dafab4 1353 (unsigned long long)int128_get64(subregion->size),
860329b2
MW
1354 subregion->name,
1355 (unsigned long long)other->addr,
08dafab4 1356 (unsigned long long)int128_get64(other->size),
860329b2 1357 other->name);
a5e1cbc8 1358#endif
093bc2cd
AK
1359 }
1360 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
1361 if (subregion->priority >= other->priority) {
1362 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
1363 goto done;
1364 }
1365 }
1366 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
1367done:
22bde714 1368 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1369 memory_region_transaction_commit();
093bc2cd
AK
1370}
1371
1372
1373void memory_region_add_subregion(MemoryRegion *mr,
a8170e5e 1374 hwaddr offset,
093bc2cd
AK
1375 MemoryRegion *subregion)
1376{
1377 subregion->may_overlap = false;
1378 subregion->priority = 0;
1379 memory_region_add_subregion_common(mr, offset, subregion);
1380}
1381
1382void memory_region_add_subregion_overlap(MemoryRegion *mr,
a8170e5e 1383 hwaddr offset,
093bc2cd
AK
1384 MemoryRegion *subregion,
1385 unsigned priority)
1386{
1387 subregion->may_overlap = true;
1388 subregion->priority = priority;
1389 memory_region_add_subregion_common(mr, offset, subregion);
1390}
1391
1392void memory_region_del_subregion(MemoryRegion *mr,
1393 MemoryRegion *subregion)
1394{
59023ef4 1395 memory_region_transaction_begin();
093bc2cd
AK
1396 assert(subregion->parent == mr);
1397 subregion->parent = NULL;
1398 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
22bde714 1399 memory_region_update_pending |= mr->enabled && subregion->enabled;
59023ef4 1400 memory_region_transaction_commit();
6bba19ba
AK
1401}
1402
1403void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
1404{
1405 if (enabled == mr->enabled) {
1406 return;
1407 }
59023ef4 1408 memory_region_transaction_begin();
6bba19ba 1409 mr->enabled = enabled;
22bde714 1410 memory_region_update_pending = true;
59023ef4 1411 memory_region_transaction_commit();
093bc2cd 1412}
1c0ffa58 1413
a8170e5e 1414void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2282e1af
AK
1415{
1416 MemoryRegion *parent = mr->parent;
1417 unsigned priority = mr->priority;
1418 bool may_overlap = mr->may_overlap;
1419
1420 if (addr == mr->addr || !parent) {
1421 mr->addr = addr;
1422 return;
1423 }
1424
1425 memory_region_transaction_begin();
1426 memory_region_del_subregion(parent, mr);
1427 if (may_overlap) {
1428 memory_region_add_subregion_overlap(parent, addr, mr, priority);
1429 } else {
1430 memory_region_add_subregion(parent, addr, mr);
1431 }
1432 memory_region_transaction_commit();
1433}
1434
a8170e5e 1435void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
4703359e 1436{
4703359e 1437 assert(mr->alias);
4703359e 1438
59023ef4 1439 if (offset == mr->alias_offset) {
4703359e
AK
1440 return;
1441 }
1442
59023ef4
JK
1443 memory_region_transaction_begin();
1444 mr->alias_offset = offset;
22bde714 1445 memory_region_update_pending |= mr->enabled;
59023ef4 1446 memory_region_transaction_commit();
4703359e
AK
1447}
1448
e34911c4
AK
1449ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
1450{
e34911c4
AK
1451 return mr->ram_addr;
1452}
1453
e2177955
AK
1454static int cmp_flatrange_addr(const void *addr_, const void *fr_)
1455{
1456 const AddrRange *addr = addr_;
1457 const FlatRange *fr = fr_;
1458
1459 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
1460 return -1;
1461 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
1462 return 1;
1463 }
1464 return 0;
1465}
1466
1467static FlatRange *address_space_lookup(AddressSpace *as, AddrRange addr)
1468{
8786db7c 1469 return bsearch(&addr, as->current_map->ranges, as->current_map->nr,
e2177955
AK
1470 sizeof(FlatRange), cmp_flatrange_addr);
1471}
1472
73034e9e 1473MemoryRegionSection memory_region_find(MemoryRegion *mr,
a8170e5e 1474 hwaddr addr, uint64_t size)
e2177955 1475{
e2177955 1476 MemoryRegionSection ret = { .mr = NULL, .size = 0 };
73034e9e
PB
1477 MemoryRegion *root;
1478 AddressSpace *as;
1479 AddrRange range;
1480 FlatRange *fr;
1481
1482 addr += mr->addr;
1483 for (root = mr; root->parent; ) {
1484 root = root->parent;
1485 addr += root->addr;
1486 }
e2177955 1487
73034e9e
PB
1488 as = memory_region_to_address_space(root);
1489 range = addrrange_make(int128_make64(addr), int128_make64(size));
1490 fr = address_space_lookup(as, range);
e2177955
AK
1491 if (!fr) {
1492 return ret;
1493 }
1494
8786db7c 1495 while (fr > as->current_map->ranges
e2177955
AK
1496 && addrrange_intersects(fr[-1].addr, range)) {
1497 --fr;
1498 }
1499
1500 ret.mr = fr->mr;
73034e9e 1501 ret.address_space = as;
e2177955
AK
1502 range = addrrange_intersection(range, fr->addr);
1503 ret.offset_within_region = fr->offset_in_region;
1504 ret.offset_within_region += int128_get64(int128_sub(range.start,
1505 fr->addr.start));
1506 ret.size = int128_get64(range.size);
1507 ret.offset_within_address_space = int128_get64(range.start);
7a8499e8 1508 ret.readonly = fr->readonly;
e2177955
AK
1509 return ret;
1510}
1511
1d671369 1512void address_space_sync_dirty_bitmap(AddressSpace *as)
86e775c6 1513{
7664e80c
AK
1514 FlatRange *fr;
1515
8786db7c 1516 FOR_EACH_FLAT_RANGE(fr, as->current_map) {
72e22d2f 1517 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, log_sync);
7664e80c
AK
1518 }
1519}
1520
1521void memory_global_dirty_log_start(void)
1522{
7664e80c 1523 global_dirty_log = true;
7376e582 1524 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
7664e80c
AK
1525}
1526
1527void memory_global_dirty_log_stop(void)
1528{
7664e80c 1529 global_dirty_log = false;
7376e582 1530 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
7664e80c
AK
1531}
1532
1533static void listener_add_address_space(MemoryListener *listener,
1534 AddressSpace *as)
1535{
1536 FlatRange *fr;
1537
221b3a3f 1538 if (listener->address_space_filter
f6790af6 1539 && listener->address_space_filter != as) {
221b3a3f
JG
1540 return;
1541 }
1542
7664e80c 1543 if (global_dirty_log) {
975aefe0
AK
1544 if (listener->log_global_start) {
1545 listener->log_global_start(listener);
1546 }
7664e80c 1547 }
975aefe0 1548
8786db7c 1549 FOR_EACH_FLAT_RANGE(fr, as->current_map) {
7664e80c
AK
1550 MemoryRegionSection section = {
1551 .mr = fr->mr,
f6790af6 1552 .address_space = as,
7664e80c
AK
1553 .offset_within_region = fr->offset_in_region,
1554 .size = int128_get64(fr->addr.size),
1555 .offset_within_address_space = int128_get64(fr->addr.start),
7a8499e8 1556 .readonly = fr->readonly,
7664e80c 1557 };
975aefe0
AK
1558 if (listener->region_add) {
1559 listener->region_add(listener, &section);
1560 }
7664e80c
AK
1561 }
1562}
1563
f6790af6 1564void memory_listener_register(MemoryListener *listener, AddressSpace *filter)
7664e80c 1565{
72e22d2f 1566 MemoryListener *other = NULL;
0d673e36 1567 AddressSpace *as;
72e22d2f 1568
7376e582 1569 listener->address_space_filter = filter;
72e22d2f
AK
1570 if (QTAILQ_EMPTY(&memory_listeners)
1571 || listener->priority >= QTAILQ_LAST(&memory_listeners,
1572 memory_listeners)->priority) {
1573 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
1574 } else {
1575 QTAILQ_FOREACH(other, &memory_listeners, link) {
1576 if (listener->priority < other->priority) {
1577 break;
1578 }
1579 }
1580 QTAILQ_INSERT_BEFORE(other, listener, link);
1581 }
0d673e36
AK
1582
1583 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1584 listener_add_address_space(listener, as);
1585 }
7664e80c
AK
1586}
1587
1588void memory_listener_unregister(MemoryListener *listener)
1589{
72e22d2f 1590 QTAILQ_REMOVE(&memory_listeners, listener, link);
86e775c6 1591}
e2177955 1592
9ad2bbc1 1593void address_space_init(AddressSpace *as, MemoryRegion *root)
1c0ffa58 1594{
59023ef4 1595 memory_region_transaction_begin();
8786db7c
AK
1596 as->root = root;
1597 as->current_map = g_new(FlatView, 1);
1598 flatview_init(as->current_map);
4c19eb72
AK
1599 as->ioeventfd_nb = 0;
1600 as->ioeventfds = NULL;
0d673e36
AK
1601 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
1602 as->name = NULL;
ac1970fb 1603 address_space_init_dispatch(as);
f43793c7
PB
1604 memory_region_update_pending |= root->enabled;
1605 memory_region_transaction_commit();
1c0ffa58 1606}
658b2224 1607
83f3c251
AK
1608void address_space_destroy(AddressSpace *as)
1609{
1610 /* Flush out anything from MemoryListeners listening in on this */
1611 memory_region_transaction_begin();
1612 as->root = NULL;
1613 memory_region_transaction_commit();
1614 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
1615 address_space_destroy_dispatch(as);
1616 flatview_destroy(as->current_map);
1617 g_free(as->current_map);
4c19eb72 1618 g_free(as->ioeventfds);
83f3c251
AK
1619}
1620
a8170e5e 1621uint64_t io_mem_read(MemoryRegion *mr, hwaddr addr, unsigned size)
acbbec5d 1622{
37ec01d4 1623 return memory_region_dispatch_read(mr, addr, size);
acbbec5d
AK
1624}
1625
a8170e5e 1626void io_mem_write(MemoryRegion *mr, hwaddr addr,
acbbec5d
AK
1627 uint64_t val, unsigned size)
1628{
37ec01d4 1629 memory_region_dispatch_write(mr, addr, val, size);
acbbec5d
AK
1630}
1631
314e2987
BS
1632typedef struct MemoryRegionList MemoryRegionList;
1633
1634struct MemoryRegionList {
1635 const MemoryRegion *mr;
1636 bool printed;
1637 QTAILQ_ENTRY(MemoryRegionList) queue;
1638};
1639
1640typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead;
1641
1642static void mtree_print_mr(fprintf_function mon_printf, void *f,
1643 const MemoryRegion *mr, unsigned int level,
a8170e5e 1644 hwaddr base,
9479c57a 1645 MemoryRegionListHead *alias_print_queue)
314e2987 1646{
9479c57a
JK
1647 MemoryRegionList *new_ml, *ml, *next_ml;
1648 MemoryRegionListHead submr_print_queue;
314e2987
BS
1649 const MemoryRegion *submr;
1650 unsigned int i;
1651
7ea692b2 1652 if (!mr || !mr->enabled) {
314e2987
BS
1653 return;
1654 }
1655
1656 for (i = 0; i < level; i++) {
1657 mon_printf(f, " ");
1658 }
1659
1660 if (mr->alias) {
1661 MemoryRegionList *ml;
1662 bool found = false;
1663
1664 /* check if the alias is already in the queue */
9479c57a 1665 QTAILQ_FOREACH(ml, alias_print_queue, queue) {
314e2987
BS
1666 if (ml->mr == mr->alias && !ml->printed) {
1667 found = true;
1668 }
1669 }
1670
1671 if (!found) {
1672 ml = g_new(MemoryRegionList, 1);
1673 ml->mr = mr->alias;
1674 ml->printed = false;
9479c57a 1675 QTAILQ_INSERT_TAIL(alias_print_queue, ml, queue);
314e2987 1676 }
4896d74b
JK
1677 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
1678 " (prio %d, %c%c): alias %s @%s " TARGET_FMT_plx
1679 "-" TARGET_FMT_plx "\n",
314e2987 1680 base + mr->addr,
08dafab4 1681 base + mr->addr
a8170e5e 1682 + (hwaddr)int128_get64(mr->size) - 1,
4b474ba7 1683 mr->priority,
5f9a5ea1
JK
1684 mr->romd_mode ? 'R' : '-',
1685 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1686 : '-',
314e2987
BS
1687 mr->name,
1688 mr->alias->name,
1689 mr->alias_offset,
08dafab4 1690 mr->alias_offset
a8170e5e 1691 + (hwaddr)int128_get64(mr->size) - 1);
314e2987 1692 } else {
4896d74b
JK
1693 mon_printf(f,
1694 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %c%c): %s\n",
314e2987 1695 base + mr->addr,
08dafab4 1696 base + mr->addr
a8170e5e 1697 + (hwaddr)int128_get64(mr->size) - 1,
4b474ba7 1698 mr->priority,
5f9a5ea1
JK
1699 mr->romd_mode ? 'R' : '-',
1700 !mr->readonly && !(mr->rom_device && mr->romd_mode) ? 'W'
1701 : '-',
314e2987
BS
1702 mr->name);
1703 }
9479c57a
JK
1704
1705 QTAILQ_INIT(&submr_print_queue);
1706
314e2987 1707 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
9479c57a
JK
1708 new_ml = g_new(MemoryRegionList, 1);
1709 new_ml->mr = submr;
1710 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1711 if (new_ml->mr->addr < ml->mr->addr ||
1712 (new_ml->mr->addr == ml->mr->addr &&
1713 new_ml->mr->priority > ml->mr->priority)) {
1714 QTAILQ_INSERT_BEFORE(ml, new_ml, queue);
1715 new_ml = NULL;
1716 break;
1717 }
1718 }
1719 if (new_ml) {
1720 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, queue);
1721 }
1722 }
1723
1724 QTAILQ_FOREACH(ml, &submr_print_queue, queue) {
1725 mtree_print_mr(mon_printf, f, ml->mr, level + 1, base + mr->addr,
1726 alias_print_queue);
1727 }
1728
88365e47 1729 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, queue, next_ml) {
9479c57a 1730 g_free(ml);
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1731 }
1732}
1733
1734void mtree_info(fprintf_function mon_printf, void *f)
1735{
1736 MemoryRegionListHead ml_head;
1737 MemoryRegionList *ml, *ml2;
0d673e36 1738 AddressSpace *as;
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1739
1740 QTAILQ_INIT(&ml_head);
1741
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1742 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1743 if (!as->name) {
1744 continue;
1745 }
1746 mon_printf(f, "%s\n", as->name);
1747 mtree_print_mr(mon_printf, f, as->root, 0, 0, &ml_head);
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1748 }
1749
1750 mon_printf(f, "aliases\n");
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1751 /* print aliased regions */
1752 QTAILQ_FOREACH(ml, &ml_head, queue) {
1753 if (!ml->printed) {
1754 mon_printf(f, "%s\n", ml->mr->name);
1755 mtree_print_mr(mon_printf, f, ml->mr, 0, 0, &ml_head);
1756 }
1757 }
1758
1759 QTAILQ_FOREACH_SAFE(ml, &ml_head, queue, ml2) {
88365e47 1760 g_free(ml);
314e2987 1761 }
314e2987 1762}