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target-i386: Show host and VM TSC frequencies on mismatch
[mirror_qemu.git] / target-i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c
AS		 28#include "hyperv.h"
29
022c62cb 30#include "exec/gdbstub.h"
1de7afc9
PB		 31#include "qemu/host-utils.h"
32#include "qemu/config-file.h"
1c4a55db 33#include "qemu/error-report.h"
0d09e41a
PB		 34#include "hw/i386/pc.h"
35#include "hw/i386/apic.h"
e0723c45
PB		 36#include "hw/i386/apic_internal.h"
37#include "hw/i386/apic-msidef.h"
50efe82c 38
022c62cb 39#include "exec/ioport.h"
73aa529a 40#include "standard-headers/asm-x86/hyperv.h"
a2cb15b0 41#include "hw/pci/pci.h"
15eafc2e 42#include "hw/pci/msi.h"
68bfd0ad 43#include "migration/migration.h"
4c663752 44#include "exec/memattrs.h"
05330448
AL		 45
46//#define DEBUG_KVM
47
48#ifdef DEBUG_KVM
8c0d577e 49#define DPRINTF(fmt, ...) \
05330448
AL		 50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51#else
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { } while (0)
54#endif
55
1a03675d
GC		 56#define MSR_KVM_WALL_CLOCK 0x11
57#define MSR_KVM_SYSTEM_TIME 0x12
58
d1138251
EH		 59/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
60 * 255 kvm_msr_entry structs */
61#define MSR_BUF_SIZE 4096
d71b62a1 62
c0532a76
MT		 63#ifndef BUS_MCEERR_AR
64#define BUS_MCEERR_AR 4
65#endif
66#ifndef BUS_MCEERR_AO
67#define BUS_MCEERR_AO 5
68#endif
69
94a8d39a
JK		 70const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75};
25d2e361 76
c3a3a7d3
JK		 77static bool has_msr_star;
78static bool has_msr_hsave_pa;
c9b8f6b6 79static bool has_msr_tsc_aux;
f28558d3 80static bool has_msr_tsc_adjust;
aa82ba54 81static bool has_msr_tsc_deadline;
df67696e 82static bool has_msr_feature_control;
c5999bfc 83static bool has_msr_async_pf_en;
bc9a839d 84static bool has_msr_pv_eoi_en;
21e87c46 85static bool has_msr_misc_enable;
fc12d72e 86static bool has_msr_smbase;
79e9ebeb 87static bool has_msr_bndcfgs;
917367aa 88static bool has_msr_kvm_steal_time;
25d2e361 89static int lm_capable_kernel;
7bc3d711
PB		 90static bool has_msr_hv_hypercall;
91static bool has_msr_hv_vapic;
48a5f3bc 92static bool has_msr_hv_tsc;
f2a53c9e 93static bool has_msr_hv_crash;
744b8a94 94static bool has_msr_hv_reset;
8c145d7c 95static bool has_msr_hv_vpindex;
46eb8f98 96static bool has_msr_hv_runtime;
866eea9a 97static bool has_msr_hv_synic;
ff99aa64 98static bool has_msr_hv_stimer;
d1ae67f6 99static bool has_msr_mtrr;
18cd2c17 100static bool has_msr_xss;
b827df58 101
0d894367
PB		 102static bool has_msr_architectural_pmu;
103static uint32_t num_architectural_pmu_counters;
104
28143b40
TH		 105static int has_xsave;
106static int has_xcrs;
107static int has_pit_state2;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
1d31f66b
PM		 121bool kvm_allows_irq0_override(void)
122{
123 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
124}
125
0fd7e098
LL		 126static int kvm_get_tsc(CPUState *cs)
127{
128 X86CPU *cpu = X86_CPU(cs);
129 CPUX86State *env = &cpu->env;
130 struct {
131 struct kvm_msrs info;
132 struct kvm_msr_entry entries[1];
133 } msr_data;
134 int ret;
135
136 if (env->tsc_valid) {
137 return 0;
138 }
139
140 msr_data.info.nmsrs = 1;
141 msr_data.entries[0].index = MSR_IA32_TSC;
142 env->tsc_valid = !runstate_is_running();
143
144 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
145 if (ret < 0) {
146 return ret;
147 }
148
48e1a45c 149 assert(ret == 1);
0fd7e098
LL		 150 env->tsc = msr_data.entries[0].data;
151 return 0;
152}
153
154static inline void do_kvm_synchronize_tsc(void *arg)
155{
156 CPUState *cpu = arg;
157
158 kvm_get_tsc(cpu);
159}
160
161void kvm_synchronize_all_tsc(void)
162{
163 CPUState *cpu;
164
165 if (kvm_enabled()) {
166 CPU_FOREACH(cpu) {
167 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
168 }
169 }
170}
171
b827df58
AK		 172static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
173{
174 struct kvm_cpuid2 *cpuid;
175 int r, size;
176
177 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 178 cpuid = g_malloc0(size);
b827df58
AK		 179 cpuid->nent = max;
180 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 181 if (r == 0 && cpuid->nent >= max) {
182 r = -E2BIG;
183 }
b827df58
AK		 184 if (r < 0) {
185 if (r == -E2BIG) {
7267c094 186 g_free(cpuid);
b827df58
AK		 187 return NULL;
188 } else {
189 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
190 strerror(-r));
191 exit(1);
192 }
193 }
194 return cpuid;
195}
196
dd87f8a6
EH		 197/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
198 * for all entries.
199 */
200static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
201{
202 struct kvm_cpuid2 *cpuid;
203 int max = 1;
494e95e9
CP		 204
205 if (cpuid_cache != NULL) {
206 return cpuid_cache;
207 }
dd87f8a6
EH		 208 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
209 max *= 2;
210 }
494e95e9 211 cpuid_cache = cpuid;
dd87f8a6
EH		 212 return cpuid;
213}
214
a443bc34 215static const struct kvm_para_features {
0c31b744
GC		 216 int cap;
217 int feature;
218} para_features[] = {
219 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
220 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
221 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 222 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 223};
224
ba9bc59e 225static int get_para_features(KVMState *s)
0c31b744
GC		 226{
227 int i, features = 0;
228
8e03c100 229 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 230 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 231 features |= (1 << para_features[i].feature);
232 }
233 }
234
235 return features;
236}
0c31b744
GC		 237
238
829ae2f9
EH		 239/* Returns the value for a specific register on the cpuid entry
240 */
241static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
242{
243 uint32_t ret = 0;
244 switch (reg) {
245 case R_EAX:
246 ret = entry->eax;
247 break;
248 case R_EBX:
249 ret = entry->ebx;
250 break;
251 case R_ECX:
252 ret = entry->ecx;
253 break;
254 case R_EDX:
255 ret = entry->edx;
256 break;
257 }
258 return ret;
259}
260
4fb73f1d
EH		 261/* Find matching entry for function/index on kvm_cpuid2 struct
262 */
263static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
264 uint32_t function,
265 uint32_t index)
266{
267 int i;
268 for (i = 0; i < cpuid->nent; ++i) {
269 if (cpuid->entries[i].function == function &&
270 cpuid->entries[i].index == index) {
271 return &cpuid->entries[i];
272 }
273 }
274 /* not found: */
275 return NULL;
276}
277
ba9bc59e 278uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 279 uint32_t index, int reg)
b827df58
AK		 280{
281 struct kvm_cpuid2 *cpuid;
b827df58
AK		 282 uint32_t ret = 0;
283 uint32_t cpuid_1_edx;
8c723b79 284 bool found = false;
b827df58 285
dd87f8a6 286 cpuid = get_supported_cpuid(s);
b827df58 287
4fb73f1d
EH		 288 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
289 if (entry) {
290 found = true;
291 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 292 }
293
7b46e5ce
EH		 294 /* Fixups for the data returned by KVM, below */
295
c2acb022
EH		 296 if (function == 1 && reg == R_EDX) {
297 /* KVM before 2.6.30 misreports the following features */
298 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 299 } else if (function == 1 && reg == R_ECX) {
300 /* We can set the hypervisor flag, even if KVM does not return it on
301 * GET_SUPPORTED_CPUID
302 */
303 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 304 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
305 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
306 * and the irqchip is in the kernel.
307 */
308 if (kvm_irqchip_in_kernel() &&
309 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
310 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
311 }
41e5e76d
EH		 312
313 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
314 * without the in-kernel irqchip
315 */
316 if (!kvm_irqchip_in_kernel()) {
317 ret &= ~CPUID_EXT_X2APIC;
b827df58 318 }
28b8e4d0
JK		 319 } else if (function == 6 && reg == R_EAX) {
320 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
c2acb022
EH		 321 } else if (function == 0x80000001 && reg == R_EDX) {
322 /* On Intel, kvm returns cpuid according to the Intel spec,
323 * so add missing bits according to the AMD spec:
324 */
325 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
326 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
b827df58
AK		 327 }
328
0c31b744 329 /* fallback for older kernels */
8c723b79 330 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 331 ret = get_para_features(s);
b9bec74b 332 }
0c31b744
GC		 333
334 return ret;
bb0300dc 335}
bb0300dc 336
3c85e74f
HY		 337typedef struct HWPoisonPage {
338 ram_addr_t ram_addr;
339 QLIST_ENTRY(HWPoisonPage) list;
340} HWPoisonPage;
341
342static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
343 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
344
345static void kvm_unpoison_all(void *param)
346{
347 HWPoisonPage *page, *next_page;
348
349 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
350 QLIST_REMOVE(page, list);
351 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 352 g_free(page);
3c85e74f
HY		 353 }
354}
355
3c85e74f
HY		 356static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
357{
358 HWPoisonPage *page;
359
360 QLIST_FOREACH(page, &hwpoison_page_list, list) {
361 if (page->ram_addr == ram_addr) {
362 return;
363 }
364 }
ab3ad07f 365 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 366 page->ram_addr = ram_addr;
367 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
368}
369
e7701825
MT		 370static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
371 int *max_banks)
372{
373 int r;
374
14a09518 375 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 376 if (r > 0) {
377 *max_banks = r;
378 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
379 }
380 return -ENOSYS;
381}
382
bee615d4 383static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 384{
bee615d4 385 CPUX86State *env = &cpu->env;
c34d440a
JK		 386 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
387 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
388 uint64_t mcg_status = MCG_STATUS_MCIP;
e7701825 389
c34d440a
JK		 390 if (code == BUS_MCEERR_AR) {
391 status |= MCI_STATUS_AR | 0x134;
392 mcg_status |= MCG_STATUS_EIPV;
393 } else {
394 status |= 0xc0;
395 mcg_status |= MCG_STATUS_RIPV;
419fb20a 396 }
8c5cf3b6 397 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
c34d440a
JK		 398 (MCM_ADDR_PHYS << 6) | 0xc,
399 cpu_x86_support_mca_broadcast(env) ?
400 MCE_INJECT_BROADCAST : 0);
419fb20a 401}
419fb20a
JK		 402
403static void hardware_memory_error(void)
404{
405 fprintf(stderr, "Hardware memory error!\n");
406 exit(1);
407}
408
20d695a9 409int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 410{
20d695a9
AF		 411 X86CPU *cpu = X86_CPU(c);
412 CPUX86State *env = &cpu->env;
419fb20a 413 ram_addr_t ram_addr;
a8170e5e 414 hwaddr paddr;
419fb20a
JK		 415
416 if ((env->mcg_cap & MCG_SER_P) && addr
c34d440a 417 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
07bdaa41
PB		 418 ram_addr = qemu_ram_addr_from_host(addr);
419 if (ram_addr == RAM_ADDR_INVALID ||
a60f24b5 420 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
419fb20a
JK		 421 fprintf(stderr, "Hardware memory error for memory used by "
422 "QEMU itself instead of guest system!\n");
423 /* Hope we are lucky for AO MCE */
424 if (code == BUS_MCEERR_AO) {
425 return 0;
426 } else {
427 hardware_memory_error();
428 }
429 }
3c85e74f 430 kvm_hwpoison_page_add(ram_addr);
bee615d4 431 kvm_mce_inject(cpu, paddr, code);
e56ff191 432 } else {
419fb20a
JK		 433 if (code == BUS_MCEERR_AO) {
434 return 0;
435 } else if (code == BUS_MCEERR_AR) {
436 hardware_memory_error();
437 } else {
438 return 1;
439 }
440 }
441 return 0;
442}
443
444int kvm_arch_on_sigbus(int code, void *addr)
445{
182735ef
AF		 446 X86CPU *cpu = X86_CPU(first_cpu);
447
448 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
419fb20a 449 ram_addr_t ram_addr;
a8170e5e 450 hwaddr paddr;
419fb20a
JK		 451
452 /* Hope we are lucky for AO MCE */
07bdaa41
PB		 453 ram_addr = qemu_ram_addr_from_host(addr);
454 if (ram_addr == RAM_ADDR_INVALID ||
182735ef 455 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
a60f24b5 456 addr, &paddr)) {
419fb20a
JK		 457 fprintf(stderr, "Hardware memory error for memory used by "
458 "QEMU itself instead of guest system!: %p\n", addr);
459 return 0;
460 }
3c85e74f 461 kvm_hwpoison_page_add(ram_addr);
182735ef 462 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
e56ff191 463 } else {
419fb20a
JK		 464 if (code == BUS_MCEERR_AO) {
465 return 0;
466 } else if (code == BUS_MCEERR_AR) {
467 hardware_memory_error();
468 } else {
469 return 1;
470 }
471 }
472 return 0;
473}
e7701825 474
1bc22652 475static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 476{
1bc22652
AF		 477 CPUX86State *env = &cpu->env;
478
ab443475
JK		 479 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
480 unsigned int bank, bank_num = env->mcg_cap & 0xff;
481 struct kvm_x86_mce mce;
482
483 env->exception_injected = -1;
484
485 /*
486 * There must be at least one bank in use if an MCE is pending.
487 * Find it and use its values for the event injection.
488 */
489 for (bank = 0; bank < bank_num; bank++) {
490 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
491 break;
492 }
493 }
494 assert(bank < bank_num);
495
496 mce.bank = bank;
497 mce.status = env->mce_banks[bank * 4 + 1];
498 mce.mcg_status = env->mcg_status;
499 mce.addr = env->mce_banks[bank * 4 + 2];
500 mce.misc = env->mce_banks[bank * 4 + 3];
501
1bc22652 502 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 503 }
ab443475
JK		 504 return 0;
505}
506
1dfb4dd9 507static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 508{
317ac620 509 CPUX86State *env = opaque;
b8cc45d6
GC		 510
511 if (running) {
512 env->tsc_valid = false;
513 }
514}
515
83b17af5 516unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 517{
83b17af5 518 X86CPU *cpu = X86_CPU(cs);
7e72a45c 519 return cpu->apic_id;
b164e48e
EH		 520}
521
92067bf4
IM		 522#ifndef KVM_CPUID_SIGNATURE_NEXT
523#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
524#endif
525
526static bool hyperv_hypercall_available(X86CPU *cpu)
527{
528 return cpu->hyperv_vapic ||
529 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
530}
531
532static bool hyperv_enabled(X86CPU *cpu)
533{
7bc3d711
PB		 534 CPUState *cs = CPU(cpu);
535 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
536 (hyperv_hypercall_available(cpu) ||
48a5f3bc 537 cpu->hyperv_time ||
f2a53c9e 538 cpu->hyperv_relaxed_timing ||
744b8a94 539 cpu->hyperv_crash ||
8c145d7c 540 cpu->hyperv_reset ||
46eb8f98 541 cpu->hyperv_vpindex ||
866eea9a 542 cpu->hyperv_runtime ||
ff99aa64
AS		 543 cpu->hyperv_synic ||
544 cpu->hyperv_stimer);
92067bf4
IM		 545}
546
5031283d
HZ		 547static int kvm_arch_set_tsc_khz(CPUState *cs)
548{
549 X86CPU *cpu = X86_CPU(cs);
550 CPUX86State *env = &cpu->env;
551 int r;
552
553 if (!env->tsc_khz) {
554 return 0;
555 }
556
557 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
558 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
559 -ENOTSUP;
560 if (r < 0) {
561 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
562 * TSC frequency doesn't match the one we want.
563 */
564 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
565 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
566 -ENOTSUP;
567 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
568 error_report("warning: TSC frequency mismatch between "
d6276d26
EH		 569 "VM (%" PRId64 " kHz) and host (%d kHz), "
570 "and TSC scaling unavailable",
571 env->tsc_khz, cur_freq);
5031283d
HZ		 572 return r;
573 }
574 }
575
576 return 0;
577}
578
68bfd0ad
MT		 579static Error *invtsc_mig_blocker;
580
f8bb0565 581#define KVM_MAX_CPUID_ENTRIES 100
0893d460 582
20d695a9 583int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 584{
585 struct {
486bd5a2 586 struct kvm_cpuid2 cpuid;
f8bb0565 587 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 588 } QEMU_PACKED cpuid_data;
20d695a9
AF		 589 X86CPU *cpu = X86_CPU(cs);
590 CPUX86State *env = &cpu->env;
486bd5a2 591 uint32_t limit, i, j, cpuid_i;
a33609ca 592 uint32_t unused;
bb0300dc 593 struct kvm_cpuid_entry2 *c;
bb0300dc 594 uint32_t signature[3];
234cc647 595 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 596 int r;
05330448 597
ef4cbe14
SW		 598 memset(&cpuid_data, 0, sizeof(cpuid_data));
599
05330448
AL		 600 cpuid_i = 0;
601
bb0300dc 602 /* Paravirtualization CPUIDs */
234cc647
PB		 603 if (hyperv_enabled(cpu)) {
604 c = &cpuid_data.entries[cpuid_i++];
605 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 606 if (!cpu->hyperv_vendor_id) {
607 memcpy(signature, "Microsoft Hv", 12);
608 } else {
609 size_t len = strlen(cpu->hyperv_vendor_id);
610
611 if (len > 12) {
612 error_report("hv-vendor-id truncated to 12 characters");
613 len = 12;
614 }
615 memset(signature, 0, 12);
616 memcpy(signature, cpu->hyperv_vendor_id, len);
617 }
eab70139 618 c->eax = HYPERV_CPUID_MIN;
234cc647
PB		 619 c->ebx = signature[0];
620 c->ecx = signature[1];
621 c->edx = signature[2];
0c31b744 622
234cc647
PB		 623 c = &cpuid_data.entries[cpuid_i++];
624 c->function = HYPERV_CPUID_INTERFACE;
eab70139
VR		 625 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
626 c->eax = signature[0];
234cc647
PB		 627 c->ebx = 0;
628 c->ecx = 0;
629 c->edx = 0;
eab70139
VR		 630
631 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 632 c->function = HYPERV_CPUID_VERSION;
633 c->eax = 0x00001bbc;
634 c->ebx = 0x00060001;
635
636 c = &cpuid_data.entries[cpuid_i++];
eab70139 637 c->function = HYPERV_CPUID_FEATURES;
92067bf4 638 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 639 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
640 }
92067bf4 641 if (cpu->hyperv_vapic) {
eab70139
VR		 642 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
643 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
7bc3d711 644 has_msr_hv_vapic = true;
eab70139 645 }
48a5f3bc
VR		 646 if (cpu->hyperv_time &&
647 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
648 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
649 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
650 c->eax |= 0x200;
651 has_msr_hv_tsc = true;
652 }
f2a53c9e
AS		 653 if (cpu->hyperv_crash && has_msr_hv_crash) {
654 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
655 }
4467c6c1 656 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
744b8a94
AS		 657 if (cpu->hyperv_reset && has_msr_hv_reset) {
658 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
659 }
8c145d7c
AS		 660 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
661 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
662 }
46eb8f98
AS		 663 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
664 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
665 }
866eea9a
AS		 666 if (cpu->hyperv_synic) {
667 int sint;
668
669 if (!has_msr_hv_synic ||
670 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
671 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
672 return -ENOSYS;
673 }
674
675 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
676 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
677 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
678 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
679 }
680 }
ff99aa64
AS		 681 if (cpu->hyperv_stimer) {
682 if (!has_msr_hv_stimer) {
683 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
684 return -ENOSYS;
685 }
686 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
687 }
eab70139 688 c = &cpuid_data.entries[cpuid_i++];
eab70139 689 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
92067bf4 690 if (cpu->hyperv_relaxed_timing) {
eab70139
VR		 691 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
692 }
7bc3d711 693 if (has_msr_hv_vapic) {
eab70139
VR		 694 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
695 }
92067bf4 696 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 697
698 c = &cpuid_data.entries[cpuid_i++];
eab70139
VR		 699 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
700 c->eax = 0x40;
701 c->ebx = 0x40;
702
234cc647 703 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 704 has_msr_hv_hypercall = true;
eab70139
VR		 705 }
706
f522d2ac
AW		 707 if (cpu->expose_kvm) {
708 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
709 c = &cpuid_data.entries[cpuid_i++];
710 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 711 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 712 c->ebx = signature[0];
713 c->ecx = signature[1];
714 c->edx = signature[2];
234cc647 715
f522d2ac
AW		 716 c = &cpuid_data.entries[cpuid_i++];
717 c->function = KVM_CPUID_FEATURES | kvm_base;
718 c->eax = env->features[FEAT_KVM];
234cc647 719
f522d2ac 720 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
bb0300dc 721
f522d2ac 722 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
bc9a839d 723
f522d2ac
AW		 724 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
725 }
917367aa 726
a33609ca 727 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 728
729 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 730 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
731 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
732 abort();
733 }
bb0300dc 734 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 735
736 switch (i) {
a36b1029
AL		 737 case 2: {
738 /* Keep reading function 2 till all the input is received */
739 int times;
740
a36b1029 741 c->function = i;
a33609ca
AL		 742 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
743 KVM_CPUID_FLAG_STATE_READ_NEXT;
744 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
745 times = c->eax & 0xff;
a36b1029
AL		 746
747 for (j = 1; j < times; ++j) {
f8bb0565
IM		 748 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
749 fprintf(stderr, "cpuid_data is full, no space for "
750 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
751 abort();
752 }
a33609ca 753 c = &cpuid_data.entries[cpuid_i++];
a36b1029 754 c->function = i;
a33609ca
AL		 755 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
756 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 757 }
758 break;
759 }
486bd5a2
AL		 760 case 4:
761 case 0xb:
762 case 0xd:
763 for (j = 0; ; j++) {
31e8c696
AP		 764 if (i == 0xd && j == 64) {
765 break;
766 }
486bd5a2
AL		 767 c->function = i;
768 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
769 c->index = j;
a33609ca 770 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 771
b9bec74b 772 if (i == 4 && c->eax == 0) {
486bd5a2 773 break;
b9bec74b
JK		 774 }
775 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 776 break;
b9bec74b
JK		 777 }
778 if (i == 0xd && c->eax == 0) {
31e8c696 779 continue;
b9bec74b 780 }
f8bb0565
IM		 781 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
782 fprintf(stderr, "cpuid_data is full, no space for "
783 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
784 abort();
785 }
a33609ca 786 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 787 }
788 break;
789 default:
486bd5a2 790 c->function = i;
a33609ca
AL		 791 c->flags = 0;
792 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 793 break;
794 }
05330448 795 }
0d894367
PB		 796
797 if (limit >= 0x0a) {
798 uint32_t ver;
799
800 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
801 if ((ver & 0xff) > 0) {
802 has_msr_architectural_pmu = true;
803 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
804
805 /* Shouldn't be more than 32, since that's the number of bits
806 * available in EBX to tell us _which_ counters are available.
807 * Play it safe.
808 */
809 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
810 num_architectural_pmu_counters = MAX_GP_COUNTERS;
811 }
812 }
813 }
814
a33609ca 815 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 816
817 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 818 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
819 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
820 abort();
821 }
bb0300dc 822 c = &cpuid_data.entries[cpuid_i++];
05330448 823
05330448 824 c->function = i;
a33609ca
AL		 825 c->flags = 0;
826 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 827 }
828
b3baa152
BW		 829 /* Call Centaur's CPUID instructions they are supported. */
830 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 831 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
832
833 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 834 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
835 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
836 abort();
837 }
b3baa152
BW		 838 c = &cpuid_data.entries[cpuid_i++];
839
840 c->function = i;
841 c->flags = 0;
842 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
843 }
844 }
845
05330448
AL		 846 cpuid_data.cpuid.nent = cpuid_i;
847
e7701825 848 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 849 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 850 (CPUID_MCE | CPUID_MCA)
a60f24b5 851 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 852 uint64_t mcg_cap, unsupported_caps;
e7701825 853 int banks;
32a42024 854 int ret;
e7701825 855
a60f24b5 856 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 857 if (ret < 0) {
858 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
859 return ret;
e7701825 860 }
75d49497 861
2590f15b 862 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 863 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 864 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 865 return -ENOTSUP;
75d49497 866 }
49b69cbf 867
5120901a
EH		 868 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
869 if (unsupported_caps) {
870 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
871 unsupported_caps);
872 }
873
2590f15b
EH		 874 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
875 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 876 if (ret < 0) {
877 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
878 return ret;
879 }
e7701825 880 }
e7701825 881
b8cc45d6
GC		 882 qemu_add_vm_change_state_handler(cpu_update_state, env);
883
df67696e
LJ		 884 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
885 if (c) {
886 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
887 !!(c->ecx & CPUID_EXT_SMX);
888 }
889
68bfd0ad
MT		 890 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
891 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
892 /* for migration */
893 error_setg(&invtsc_mig_blocker,
894 "State blocked by non-migratable CPU device"
895 " (invtsc flag)");
896 migrate_add_blocker(invtsc_mig_blocker);
897 /* for savevm */
898 vmstate_x86_cpu.unmigratable = 1;
899 }
900
7e680753 901 cpuid_data.cpuid.padding = 0;
1bc22652 902 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
fdc9c41a
JK		 903 if (r) {
904 return r;
905 }
e7429073 906
5031283d
HZ		 907 r = kvm_arch_set_tsc_khz(cs);
908 if (r < 0) {
909 return r;
e7429073 910 }
e7429073 911
bcffbeeb
HZ		 912 /* vcpu's TSC frequency is either specified by user, or following
913 * the value used by KVM if the former is not present. In the
914 * latter case, we query it from KVM and record in env->tsc_khz,
915 * so that vcpu's TSC frequency can be migrated later via this field.
916 */
917 if (!env->tsc_khz) {
918 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
919 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
920 -ENOTSUP;
921 if (r > 0) {
922 env->tsc_khz = r;
923 }
924 }
925
28143b40 926 if (has_xsave) {
fabacc0f
JK		 927 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
928 }
d71b62a1 929 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 930
d1ae67f6
AW		 931 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
932 has_msr_mtrr = true;
933 }
273c515c
PB		 934 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
935 has_msr_tsc_aux = false;
936 }
d1ae67f6 937
e7429073 938 return 0;
05330448
AL		 939}
940
50a2c6e5 941void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 942{
20d695a9 943 CPUX86State *env = &cpu->env;
dd673288 944
e73223a5 945 env->exception_injected = -1;
0e607a80 946 env->interrupt_injected = -1;
1a5e9d2f 947 env->xcr0 = 1;
ddced198 948 if (kvm_irqchip_in_kernel()) {
dd673288 949 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 950 KVM_MP_STATE_UNINITIALIZED;
951 } else {
952 env->mp_state = KVM_MP_STATE_RUNNABLE;
953 }
caa5af0f
JK		 954}
955
e0723c45
PB		 956void kvm_arch_do_init_vcpu(X86CPU *cpu)
957{
958 CPUX86State *env = &cpu->env;
959
960 /* APs get directly into wait-for-SIPI state. */
961 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
962 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
963 }
964}
965
c3a3a7d3 966static int kvm_get_supported_msrs(KVMState *s)
05330448 967{
75b10c43 968 static int kvm_supported_msrs;
c3a3a7d3 969 int ret = 0;
05330448
AL		 970
971 /* first time */
75b10c43 972 if (kvm_supported_msrs == 0) {
05330448
AL		 973 struct kvm_msr_list msr_list, *kvm_msr_list;
974
75b10c43 975 kvm_supported_msrs = -1;
05330448
AL		 976
977 /* Obtain MSR list from KVM. These are the MSRs that we must
978 * save/restore */
4c9f7372 979 msr_list.nmsrs = 0;
c3a3a7d3 980 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 981 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 982 return ret;
6fb6d245 983 }
d9db889f
JK		 984 /* Old kernel modules had a bug and could write beyond the provided
985 memory. Allocate at least a safe amount of 1K. */
7267c094 986 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 987 msr_list.nmsrs *
988 sizeof(msr_list.indices[0])));
05330448 989
55308450 990 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 991 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 992 if (ret >= 0) {
993 int i;
994
995 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
996 if (kvm_msr_list->indices[i] == MSR_STAR) {
c3a3a7d3 997 has_msr_star = true;
75b10c43
MT		 998 continue;
999 }
1000 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
c3a3a7d3 1001 has_msr_hsave_pa = true;
75b10c43 1002 continue;
05330448 1003 }
c9b8f6b6
AS		 1004 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1005 has_msr_tsc_aux = true;
1006 continue;
1007 }
f28558d3
WA		 1008 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1009 has_msr_tsc_adjust = true;
1010 continue;
1011 }
aa82ba54
LJ		 1012 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1013 has_msr_tsc_deadline = true;
1014 continue;
1015 }
fc12d72e
PB		 1016 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1017 has_msr_smbase = true;
1018 continue;
1019 }
21e87c46
AK		 1020 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1021 has_msr_misc_enable = true;
1022 continue;
1023 }
79e9ebeb
LJ		 1024 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1025 has_msr_bndcfgs = true;
1026 continue;
1027 }
18cd2c17
WL		 1028 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1029 has_msr_xss = true;
1030 continue;
1031 }
f2a53c9e
AS		 1032 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1033 has_msr_hv_crash = true;
1034 continue;
1035 }
744b8a94
AS		 1036 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1037 has_msr_hv_reset = true;
1038 continue;
1039 }
8c145d7c
AS		 1040 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1041 has_msr_hv_vpindex = true;
1042 continue;
1043 }
46eb8f98
AS		 1044 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1045 has_msr_hv_runtime = true;
1046 continue;
1047 }
866eea9a
AS		 1048 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1049 has_msr_hv_synic = true;
1050 continue;
1051 }
ff99aa64
AS		 1052 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1053 has_msr_hv_stimer = true;
1054 continue;
1055 }
05330448
AL		 1056 }
1057 }
1058
7267c094 1059 g_free(kvm_msr_list);
05330448
AL		 1060 }
1061
c3a3a7d3 1062 return ret;
05330448
AL		 1063}
1064
6410848b
PB		 1065static Notifier smram_machine_done;
1066static KVMMemoryListener smram_listener;
1067static AddressSpace smram_address_space;
1068static MemoryRegion smram_as_root;
1069static MemoryRegion smram_as_mem;
1070
1071static void register_smram_listener(Notifier *n, void *unused)
1072{
1073 MemoryRegion *smram =
1074 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1075
1076 /* Outer container... */
1077 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1078 memory_region_set_enabled(&smram_as_root, true);
1079
1080 /* ... with two regions inside: normal system memory with low
1081 * priority, and...
1082 */
1083 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1084 get_system_memory(), 0, ~0ull);
1085 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1086 memory_region_set_enabled(&smram_as_mem, true);
1087
1088 if (smram) {
1089 /* ... SMRAM with higher priority */
1090 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1091 memory_region_set_enabled(smram, true);
1092 }
1093
1094 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1095 kvm_memory_listener_register(kvm_state, &smram_listener,
1096 &smram_address_space, 1);
1097}
1098
b16565b3 1099int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1100{
11076198 1101 uint64_t identity_base = 0xfffbc000;
39d6960a 1102 uint64_t shadow_mem;
20420430 1103 int ret;
25d2e361 1104 struct utsname utsname;
20420430 1105
28143b40
TH		 1106#ifdef KVM_CAP_XSAVE
1107 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1108#endif
1109
1110#ifdef KVM_CAP_XCRS
1111 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1112#endif
1113
1114#ifdef KVM_CAP_PIT_STATE2
1115 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1116#endif
1117
c3a3a7d3 1118 ret = kvm_get_supported_msrs(s);
20420430 1119 if (ret < 0) {
20420430
SY		 1120 return ret;
1121 }
25d2e361
MT		 1122
1123 uname(&utsname);
1124 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1125
4c5b10b7 1126 /*
11076198
JK		 1127 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1128 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1129 * Since these must be part of guest physical memory, we need to allocate
1130 * them, both by setting their start addresses in the kernel and by
1131 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1132 *
1133 * Older KVM versions may not support setting the identity map base. In
1134 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1135 * size.
4c5b10b7 1136 */
11076198
JK		 1137 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1138 /* Allows up to 16M BIOSes. */
1139 identity_base = 0xfeffc000;
1140
1141 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1142 if (ret < 0) {
1143 return ret;
1144 }
4c5b10b7 1145 }
e56ff191 1146
11076198
JK		 1147 /* Set TSS base one page after EPT identity map. */
1148 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1149 if (ret < 0) {
1150 return ret;
1151 }
1152
11076198
JK		 1153 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1154 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1155 if (ret < 0) {
11076198 1156 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1157 return ret;
1158 }
3c85e74f 1159 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1160
4689b77b 1161 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1162 if (shadow_mem != -1) {
1163 shadow_mem /= 4096;
1164 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1165 if (ret < 0) {
1166 return ret;
39d6960a
JK		 1167 }
1168 }
6410848b
PB		 1169
1170 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1171 smram_machine_done.notify = register_smram_listener;
1172 qemu_add_machine_init_done_notifier(&smram_machine_done);
1173 }
11076198 1174 return 0;
05330448 1175}
b9bec74b 1176
05330448
AL		 1177static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1178{
1179 lhs->selector = rhs->selector;
1180 lhs->base = rhs->base;
1181 lhs->limit = rhs->limit;
1182 lhs->type = 3;
1183 lhs->present = 1;
1184 lhs->dpl = 3;
1185 lhs->db = 0;
1186 lhs->s = 1;
1187 lhs->l = 0;
1188 lhs->g = 0;
1189 lhs->avl = 0;
1190 lhs->unusable = 0;
1191}
1192
1193static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1194{
1195 unsigned flags = rhs->flags;
1196 lhs->selector = rhs->selector;
1197 lhs->base = rhs->base;
1198 lhs->limit = rhs->limit;
1199 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1200 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1201 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1202 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1203 lhs->s = (flags & DESC_S_MASK) != 0;
1204 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1205 lhs->g = (flags & DESC_G_MASK) != 0;
1206 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1207 lhs->unusable = !lhs->present;
7e680753 1208 lhs->padding = 0;
05330448
AL		 1209}
1210
1211static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1212{
1213 lhs->selector = rhs->selector;
1214 lhs->base = rhs->base;
1215 lhs->limit = rhs->limit;
4cae9c97
MC		 1216 if (rhs->unusable) {
1217 lhs->flags = 0;
1218 } else {
1219 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1220 (rhs->present * DESC_P_MASK) |
1221 (rhs->dpl << DESC_DPL_SHIFT) |
1222 (rhs->db << DESC_B_SHIFT) |
1223 (rhs->s * DESC_S_MASK) |
1224 (rhs->l << DESC_L_SHIFT) |
1225 (rhs->g * DESC_G_MASK) |
1226 (rhs->avl * DESC_AVL_MASK);
1227 }
05330448
AL		 1228}
1229
1230static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1231{
b9bec74b 1232 if (set) {
05330448 1233 *kvm_reg = *qemu_reg;
b9bec74b 1234 } else {
05330448 1235 *qemu_reg = *kvm_reg;
b9bec74b 1236 }
05330448
AL		 1237}
1238
1bc22652 1239static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1240{
1bc22652 1241 CPUX86State *env = &cpu->env;
05330448
AL		 1242 struct kvm_regs regs;
1243 int ret = 0;
1244
1245 if (!set) {
1bc22652 1246 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1247 if (ret < 0) {
05330448 1248 return ret;
b9bec74b 1249 }
05330448
AL		 1250 }
1251
1252 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1253 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1254 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1255 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1256 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1257 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1258 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1259 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1260#ifdef TARGET_X86_64
1261 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1262 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1263 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1264 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1265 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1266 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1267 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1268 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1269#endif
1270
1271 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1272 kvm_getput_reg(&regs.rip, &env->eip, set);
1273
b9bec74b 1274 if (set) {
1bc22652 1275 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1276 }
05330448
AL		 1277
1278 return ret;
1279}
1280
1bc22652 1281static int kvm_put_fpu(X86CPU *cpu)
05330448 1282{
1bc22652 1283 CPUX86State *env = &cpu->env;
05330448
AL		 1284 struct kvm_fpu fpu;
1285 int i;
1286
1287 memset(&fpu, 0, sizeof fpu);
1288 fpu.fsw = env->fpus & ~(7 << 11);
1289 fpu.fsw |= (env->fpstt & 7) << 11;
1290 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1291 fpu.last_opcode = env->fpop;
1292 fpu.last_ip = env->fpip;
1293 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1294 for (i = 0; i < 8; ++i) {
1295 fpu.ftwx |= (!env->fptags[i]) << i;
1296 }
05330448 1297 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1298 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1299 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1300 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1301 }
05330448
AL		 1302 fpu.mxcsr = env->mxcsr;
1303
1bc22652 1304 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1305}
1306
6b42494b
JK		 1307#define XSAVE_FCW_FSW 0
1308#define XSAVE_FTW_FOP 1
f1665b21
SY		 1309#define XSAVE_CWD_RIP 2
1310#define XSAVE_CWD_RDP 4
1311#define XSAVE_MXCSR 6
1312#define XSAVE_ST_SPACE 8
1313#define XSAVE_XMM_SPACE 40
1314#define XSAVE_XSTATE_BV 128
1315#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1316#define XSAVE_BNDREGS 240
1317#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1318#define XSAVE_OPMASK 272
1319#define XSAVE_ZMM_Hi256 288
1320#define XSAVE_Hi16_ZMM 416
f74eefe0 1321#define XSAVE_PKRU 672
f1665b21 1322
b503717d
EH		 1323#define XSAVE_BYTE_OFFSET(word_offset) \
1324 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1325
1326#define ASSERT_OFFSET(word_offset, field) \
1327 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1328 offsetof(X86XSaveArea, field))
1329
1330ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1331ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1332ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1333ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1334ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1335ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1336ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1337ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1338ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1339ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1340ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1341ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1342ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1343ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1344ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1345
1bc22652 1346static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1347{
1bc22652 1348 CPUX86State *env = &cpu->env;
86cd2ea0 1349 X86XSaveArea *xsave = env->kvm_xsave_buf;
42cc8fa6 1350 uint16_t cwd, swd, twd;
9be38598 1351 int i;
f1665b21 1352
28143b40 1353 if (!has_xsave) {
1bc22652 1354 return kvm_put_fpu(cpu);
b9bec74b 1355 }
f1665b21 1356
f1665b21 1357 memset(xsave, 0, sizeof(struct kvm_xsave));
6115c0a8 1358 twd = 0;
f1665b21
SY		 1359 swd = env->fpus & ~(7 << 11);
1360 swd |= (env->fpstt & 7) << 11;
1361 cwd = env->fpuc;
b9bec74b 1362 for (i = 0; i < 8; ++i) {
f1665b21 1363 twd |= (!env->fptags[i]) << i;
b9bec74b 1364 }
86cd2ea0
EH		 1365 xsave->legacy.fcw = cwd;
1366 xsave->legacy.fsw = swd;
1367 xsave->legacy.ftw = twd;
1368 xsave->legacy.fpop = env->fpop;
1369 xsave->legacy.fpip = env->fpip;
1370 xsave->legacy.fpdp = env->fpdp;
1371 memcpy(&xsave->legacy.fpregs, env->fpregs,
f1665b21 1372 sizeof env->fpregs);
86cd2ea0
EH		 1373 xsave->legacy.mxcsr = env->mxcsr;
1374 xsave->header.xstate_bv = env->xstate_bv;
1375 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
79e9ebeb 1376 sizeof env->bnd_regs);
86cd2ea0
EH		 1377 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1378 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
9aecd6f8 1379 sizeof env->opmask_regs);
bee81887 1380
86cd2ea0
EH		 1381 for (i = 0; i < CPU_NB_REGS; i++) {
1382 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1383 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1384 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1385 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1386 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1387 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1388 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1389 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1390 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1391 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1392 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
bee81887
PB		 1393 }
1394
9aecd6f8 1395#ifdef TARGET_X86_64
86cd2ea0 1396 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
b7711471 1397 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1398 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
9aecd6f8 1399#endif
9be38598 1400 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1401}
1402
1bc22652 1403static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1404{
1bc22652 1405 CPUX86State *env = &cpu->env;
bdfc8480 1406 struct kvm_xcrs xcrs = {};
f1665b21 1407
28143b40 1408 if (!has_xcrs) {
f1665b21 1409 return 0;
b9bec74b 1410 }
f1665b21
SY		 1411
1412 xcrs.nr_xcrs = 1;
1413 xcrs.flags = 0;
1414 xcrs.xcrs[0].xcr = 0;
1415 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1416 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1417}
1418
1bc22652 1419static int kvm_put_sregs(X86CPU *cpu)
05330448 1420{
1bc22652 1421 CPUX86State *env = &cpu->env;
05330448
AL		 1422 struct kvm_sregs sregs;
1423
0e607a80
JK		 1424 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1425 if (env->interrupt_injected >= 0) {
1426 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1427 (uint64_t)1 << (env->interrupt_injected % 64);
1428 }
05330448
AL		 1429
1430 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1431 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1432 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1433 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1434 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1435 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1436 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1437 } else {
b9bec74b
JK		 1438 set_seg(&sregs.cs, &env->segs[R_CS]);
1439 set_seg(&sregs.ds, &env->segs[R_DS]);
1440 set_seg(&sregs.es, &env->segs[R_ES]);
1441 set_seg(&sregs.fs, &env->segs[R_FS]);
1442 set_seg(&sregs.gs, &env->segs[R_GS]);
1443 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1444 }
1445
1446 set_seg(&sregs.tr, &env->tr);
1447 set_seg(&sregs.ldt, &env->ldt);
1448
1449 sregs.idt.limit = env->idt.limit;
1450 sregs.idt.base = env->idt.base;
7e680753 1451 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1452 sregs.gdt.limit = env->gdt.limit;
1453 sregs.gdt.base = env->gdt.base;
7e680753 1454 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1455
1456 sregs.cr0 = env->cr[0];
1457 sregs.cr2 = env->cr[2];
1458 sregs.cr3 = env->cr[3];
1459 sregs.cr4 = env->cr[4];
1460
02e51483
CF		 1461 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1462 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1463
1464 sregs.efer = env->efer;
1465
1bc22652 1466 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1467}
1468
d71b62a1
EH		 1469static void kvm_msr_buf_reset(X86CPU *cpu)
1470{
1471 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1472}
1473
9c600a84
EH		 1474static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1475{
1476 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1477 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1478 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1479
1480 assert((void *)(entry + 1) <= limit);
1481
1abc2cae
EH		 1482 entry->index = index;
1483 entry->reserved = 0;
1484 entry->data = value;
9c600a84
EH		 1485 msrs->nmsrs++;
1486}
1487
7477cd38
MT		 1488static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1489{
1490 CPUX86State *env = &cpu->env;
48e1a45c 1491 int ret;
7477cd38
MT		 1492
1493 if (!has_msr_tsc_deadline) {
1494 return 0;
1495 }
1496
e25ffda7
EH		 1497 kvm_msr_buf_reset(cpu);
1498 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
7477cd38 1499
e25ffda7 1500 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1501 if (ret < 0) {
1502 return ret;
1503 }
1504
1505 assert(ret == 1);
1506 return 0;
7477cd38
MT		 1507}
1508
6bdf863d
JK		 1509/*
1510 * Provide a separate write service for the feature control MSR in order to
1511 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1512 * before writing any other state because forcibly leaving nested mode
1513 * invalidates the VCPU state.
1514 */
1515static int kvm_put_msr_feature_control(X86CPU *cpu)
1516{
48e1a45c
PB		 1517 int ret;
1518
1519 if (!has_msr_feature_control) {
1520 return 0;
1521 }
6bdf863d 1522
e25ffda7
EH		 1523 kvm_msr_buf_reset(cpu);
1524 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
6bdf863d 1525 cpu->env.msr_ia32_feature_control);
c7fe4b12 1526
e25ffda7 1527 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1528 if (ret < 0) {
1529 return ret;
1530 }
1531
1532 assert(ret == 1);
1533 return 0;
6bdf863d
JK		 1534}
1535
1bc22652 1536static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1537{
1bc22652 1538 CPUX86State *env = &cpu->env;
9c600a84 1539 int i;
48e1a45c 1540 int ret;
05330448 1541
d71b62a1
EH		 1542 kvm_msr_buf_reset(cpu);
1543
9c600a84
EH		 1544 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1545 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1546 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1547 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1548 if (has_msr_star) {
9c600a84 1549 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1550 }
c3a3a7d3 1551 if (has_msr_hsave_pa) {
9c600a84 1552 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1553 }
c9b8f6b6 1554 if (has_msr_tsc_aux) {
9c600a84 1555 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1556 }
f28558d3 1557 if (has_msr_tsc_adjust) {
9c600a84 1558 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1559 }
21e87c46 1560 if (has_msr_misc_enable) {
9c600a84 1561 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1562 env->msr_ia32_misc_enable);
1563 }
fc12d72e 1564 if (has_msr_smbase) {
9c600a84 1565 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1566 }
439d19f2 1567 if (has_msr_bndcfgs) {
9c600a84 1568 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1569 }
18cd2c17 1570 if (has_msr_xss) {
9c600a84 1571 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1572 }
05330448 1573#ifdef TARGET_X86_64
25d2e361 1574 if (lm_capable_kernel) {
9c600a84
EH		 1575 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1576 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1577 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1578 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1579 }
05330448 1580#endif
ff5c186b 1581 /*
0d894367
PB		 1582 * The following MSRs have side effects on the guest or are too heavy
1583 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1584 */
1585 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1586 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1587 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1588 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
c5999bfc 1589 if (has_msr_async_pf_en) {
9c600a84 1590 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1591 }
bc9a839d 1592 if (has_msr_pv_eoi_en) {
9c600a84 1593 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1594 }
917367aa 1595 if (has_msr_kvm_steal_time) {
9c600a84 1596 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1597 }
0d894367
PB		 1598 if (has_msr_architectural_pmu) {
1599 /* Stop the counter. */
9c600a84
EH		 1600 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1601 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
0d894367
PB		 1602
1603 /* Set the counter values. */
1604 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 1605 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1606 env->msr_fixed_counters[i]);
1607 }
1608 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84 1609 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1610 env->msr_gp_counters[i]);
9c600a84 1611 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1612 env->msr_gp_evtsel[i]);
1613 }
9c600a84 1614 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
0d894367 1615 env->msr_global_status);
9c600a84 1616 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
0d894367
PB		 1617 env->msr_global_ovf_ctrl);
1618
1619 /* Now start the PMU. */
9c600a84 1620 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
0d894367 1621 env->msr_fixed_ctr_ctrl);
9c600a84 1622 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
0d894367
PB		 1623 env->msr_global_ctrl);
1624 }
7bc3d711 1625 if (has_msr_hv_hypercall) {
9c600a84 1626 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1c90ef26 1627 env->msr_hv_guest_os_id);
9c600a84 1628 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1c90ef26 1629 env->msr_hv_hypercall);
eab70139 1630 }
7bc3d711 1631 if (has_msr_hv_vapic) {
9c600a84 1632 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1633 env->msr_hv_vapic);
eab70139 1634 }
48a5f3bc 1635 if (has_msr_hv_tsc) {
9c600a84 1636 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
48a5f3bc 1637 }
f2a53c9e
AS		 1638 if (has_msr_hv_crash) {
1639 int j;
1640
1641 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
9c600a84 1642 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1643 env->msr_hv_crash_params[j]);
1644
9c600a84 1645 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
f2a53c9e
AS		 1646 HV_X64_MSR_CRASH_CTL_NOTIFY);
1647 }
46eb8f98 1648 if (has_msr_hv_runtime) {
9c600a84 1649 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1650 }
866eea9a
AS		 1651 if (cpu->hyperv_synic) {
1652 int j;
1653
9c600a84 1654 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1655 env->msr_hv_synic_control);
9c600a84 1656 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
866eea9a 1657 env->msr_hv_synic_version);
9c600a84 1658 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1659 env->msr_hv_synic_evt_page);
9c600a84 1660 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1661 env->msr_hv_synic_msg_page);
1662
1663 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1664 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1665 env->msr_hv_synic_sint[j]);
1666 }
1667 }
ff99aa64
AS		 1668 if (has_msr_hv_stimer) {
1669 int j;
1670
1671 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1672 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1673 env->msr_hv_stimer_config[j]);
1674 }
1675
1676 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1677 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1678 env->msr_hv_stimer_count[j]);
1679 }
1680 }
d1ae67f6 1681 if (has_msr_mtrr) {
9c600a84
EH		 1682 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1683 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1684 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1685 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1686 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1687 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1688 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1689 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1690 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1691 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1692 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1693 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1694 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 1695 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1696 env->mtrr_var[i].base);
1697 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1698 env->mtrr_var[i].mask);
d1ae67f6
AW		 1699 }
1700 }
6bdf863d
JK		 1701
1702 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1703 * kvm_put_msr_feature_control. */
ea643051 1704 }
57780495 1705 if (env->mcg_cap) {
d8da8574 1706 int i;
b9bec74b 1707
9c600a84
EH		 1708 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1709 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
c34d440a 1710 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1711 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1712 }
1713 }
1a03675d 1714
d71b62a1 1715 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1716 if (ret < 0) {
1717 return ret;
1718 }
05330448 1719
9c600a84 1720 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1721 return 0;
05330448
AL		 1722}
1723
1724
1bc22652 1725static int kvm_get_fpu(X86CPU *cpu)
05330448 1726{
1bc22652 1727 CPUX86State *env = &cpu->env;
05330448
AL		 1728 struct kvm_fpu fpu;
1729 int i, ret;
1730
1bc22652 1731 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1732 if (ret < 0) {
05330448 1733 return ret;
b9bec74b 1734 }
05330448
AL		 1735
1736 env->fpstt = (fpu.fsw >> 11) & 7;
1737 env->fpus = fpu.fsw;
1738 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1739 env->fpop = fpu.last_opcode;
1740 env->fpip = fpu.last_ip;
1741 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1742 for (i = 0; i < 8; ++i) {
1743 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1744 }
05330448 1745 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1746 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1747 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1748 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1749 }
05330448
AL		 1750 env->mxcsr = fpu.mxcsr;
1751
1752 return 0;
1753}
1754
1bc22652 1755static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1756{
1bc22652 1757 CPUX86State *env = &cpu->env;
86cd2ea0 1758 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1759 int ret, i;
42cc8fa6 1760 uint16_t cwd, swd, twd;
f1665b21 1761
28143b40 1762 if (!has_xsave) {
1bc22652 1763 return kvm_get_fpu(cpu);
b9bec74b 1764 }
f1665b21 1765
1bc22652 1766 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1767 if (ret < 0) {
f1665b21 1768 return ret;
0f53994f 1769 }
f1665b21 1770
86cd2ea0
EH		 1771 cwd = xsave->legacy.fcw;
1772 swd = xsave->legacy.fsw;
1773 twd = xsave->legacy.ftw;
1774 env->fpop = xsave->legacy.fpop;
f1665b21
SY		 1775 env->fpstt = (swd >> 11) & 7;
1776 env->fpus = swd;
1777 env->fpuc = cwd;
b9bec74b 1778 for (i = 0; i < 8; ++i) {
f1665b21 1779 env->fptags[i] = !((twd >> i) & 1);
b9bec74b 1780 }
86cd2ea0
EH		 1781 env->fpip = xsave->legacy.fpip;
1782 env->fpdp = xsave->legacy.fpdp;
1783 env->mxcsr = xsave->legacy.mxcsr;
1784 memcpy(env->fpregs, &xsave->legacy.fpregs,
f1665b21 1785 sizeof env->fpregs);
86cd2ea0
EH		 1786 env->xstate_bv = xsave->header.xstate_bv;
1787 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
79e9ebeb 1788 sizeof env->bnd_regs);
86cd2ea0
EH		 1789 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1790 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
9aecd6f8 1791 sizeof env->opmask_regs);
bee81887 1792
86cd2ea0
EH		 1793 for (i = 0; i < CPU_NB_REGS; i++) {
1794 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1795 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1796 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
19cbd87c
EH		 1797 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1798 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1799 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1800 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1801 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1802 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1803 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1804 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
bee81887
PB		 1805 }
1806
9aecd6f8 1807#ifdef TARGET_X86_64
86cd2ea0 1808 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
b7711471 1809 16 * sizeof env->xmm_regs[16]);
86cd2ea0 1810 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
9aecd6f8 1811#endif
f1665b21 1812 return 0;
f1665b21
SY		 1813}
1814
1bc22652 1815static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1816{
1bc22652 1817 CPUX86State *env = &cpu->env;
f1665b21
SY		 1818 int i, ret;
1819 struct kvm_xcrs xcrs;
1820
28143b40 1821 if (!has_xcrs) {
f1665b21 1822 return 0;
b9bec74b 1823 }
f1665b21 1824
1bc22652 1825 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1826 if (ret < 0) {
f1665b21 1827 return ret;
b9bec74b 1828 }
f1665b21 1829
b9bec74b 1830 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1831 /* Only support xcr0 now */
0fd53fec
PB		 1832 if (xcrs.xcrs[i].xcr == 0) {
1833 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1834 break;
1835 }
b9bec74b 1836 }
f1665b21 1837 return 0;
f1665b21
SY		 1838}
1839
1bc22652 1840static int kvm_get_sregs(X86CPU *cpu)
05330448 1841{
1bc22652 1842 CPUX86State *env = &cpu->env;
05330448
AL		 1843 struct kvm_sregs sregs;
1844 uint32_t hflags;
0e607a80 1845 int bit, i, ret;
05330448 1846
1bc22652 1847 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1848 if (ret < 0) {
05330448 1849 return ret;
b9bec74b 1850 }
05330448 1851
0e607a80
JK		 1852 /* There can only be one pending IRQ set in the bitmap at a time, so try
1853 to find it and save its number instead (-1 for none). */
1854 env->interrupt_injected = -1;
1855 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1856 if (sregs.interrupt_bitmap[i]) {
1857 bit = ctz64(sregs.interrupt_bitmap[i]);
1858 env->interrupt_injected = i * 64 + bit;
1859 break;
1860 }
1861 }
05330448
AL		 1862
1863 get_seg(&env->segs[R_CS], &sregs.cs);
1864 get_seg(&env->segs[R_DS], &sregs.ds);
1865 get_seg(&env->segs[R_ES], &sregs.es);
1866 get_seg(&env->segs[R_FS], &sregs.fs);
1867 get_seg(&env->segs[R_GS], &sregs.gs);
1868 get_seg(&env->segs[R_SS], &sregs.ss);
1869
1870 get_seg(&env->tr, &sregs.tr);
1871 get_seg(&env->ldt, &sregs.ldt);
1872
1873 env->idt.limit = sregs.idt.limit;
1874 env->idt.base = sregs.idt.base;
1875 env->gdt.limit = sregs.gdt.limit;
1876 env->gdt.base = sregs.gdt.base;
1877
1878 env->cr[0] = sregs.cr0;
1879 env->cr[2] = sregs.cr2;
1880 env->cr[3] = sregs.cr3;
1881 env->cr[4] = sregs.cr4;
1882
05330448 1883 env->efer = sregs.efer;
cce47516
JK		 1884
1885 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
05330448 1886
b9bec74b
JK		 1887#define HFLAG_COPY_MASK \
1888 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1889 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1890 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1891 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
05330448 1892
19dc85db
RH		 1893 hflags = env->hflags & HFLAG_COPY_MASK;
1894 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
05330448
AL		 1895 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1896 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
b9bec74b 1897 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
05330448 1898 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
19dc85db
RH		 1899
1900 if (env->cr[4] & CR4_OSFXSR_MASK) {
1901 hflags |= HF_OSFXSR_MASK;
1902 }
05330448
AL		 1903
1904 if (env->efer & MSR_EFER_LMA) {
1905 hflags |= HF_LMA_MASK;
1906 }
1907
1908 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1909 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1910 } else {
1911 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
b9bec74b 1912 (DESC_B_SHIFT - HF_CS32_SHIFT);
05330448 1913 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
b9bec74b
JK		 1914 (DESC_B_SHIFT - HF_SS32_SHIFT);
1915 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1916 !(hflags & HF_CS32_MASK)) {
1917 hflags |= HF_ADDSEG_MASK;
1918 } else {
1919 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1920 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1921 }
05330448 1922 }
19dc85db 1923 env->hflags = hflags;
05330448
AL		 1924
1925 return 0;
1926}
1927
1bc22652 1928static int kvm_get_msrs(X86CPU *cpu)
05330448 1929{
1bc22652 1930 CPUX86State *env = &cpu->env;
d71b62a1 1931 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1932 int ret, i;
05330448 1933
d71b62a1
EH		 1934 kvm_msr_buf_reset(cpu);
1935
9c600a84
EH		 1936 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1937 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1938 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1939 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1940 if (has_msr_star) {
9c600a84 1941 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1942 }
c3a3a7d3 1943 if (has_msr_hsave_pa) {
9c600a84 1944 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1945 }
c9b8f6b6 1946 if (has_msr_tsc_aux) {
9c600a84 1947 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1948 }
f28558d3 1949 if (has_msr_tsc_adjust) {
9c600a84 1950 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1951 }
aa82ba54 1952 if (has_msr_tsc_deadline) {
9c600a84 1953 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1954 }
21e87c46 1955 if (has_msr_misc_enable) {
9c600a84 1956 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1957 }
fc12d72e 1958 if (has_msr_smbase) {
9c600a84 1959 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1960 }
df67696e 1961 if (has_msr_feature_control) {
9c600a84 1962 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1963 }
79e9ebeb 1964 if (has_msr_bndcfgs) {
9c600a84 1965 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1966 }
18cd2c17 1967 if (has_msr_xss) {
9c600a84 1968 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 1969 }
1970
b8cc45d6
GC		 1971
1972 if (!env->tsc_valid) {
9c600a84 1973 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 1974 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1975 }
1976
05330448 1977#ifdef TARGET_X86_64
25d2e361 1978 if (lm_capable_kernel) {
9c600a84
EH		 1979 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1980 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1981 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1982 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 1983 }
05330448 1984#endif
9c600a84
EH		 1985 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
1986 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
c5999bfc 1987 if (has_msr_async_pf_en) {
9c600a84 1988 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 1989 }
bc9a839d 1990 if (has_msr_pv_eoi_en) {
9c600a84 1991 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 1992 }
917367aa 1993 if (has_msr_kvm_steal_time) {
9c600a84 1994 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 1995 }
0d894367 1996 if (has_msr_architectural_pmu) {
9c600a84
EH		 1997 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1998 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1999 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2000 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
0d894367 2001 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
9c600a84 2002 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367
PB		 2003 }
2004 for (i = 0; i < num_architectural_pmu_counters; i++) {
9c600a84
EH		 2005 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2006 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2007 }
2008 }
1a03675d 2009
57780495 2010 if (env->mcg_cap) {
9c600a84
EH		 2011 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2012 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
b9bec74b 2013 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2014 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2015 }
57780495 2016 }
57780495 2017
1c90ef26 2018 if (has_msr_hv_hypercall) {
9c600a84
EH		 2019 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2020 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2021 }
5ef68987 2022 if (has_msr_hv_vapic) {
9c600a84 2023 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2024 }
48a5f3bc 2025 if (has_msr_hv_tsc) {
9c600a84 2026 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2027 }
f2a53c9e
AS		 2028 if (has_msr_hv_crash) {
2029 int j;
2030
2031 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
9c600a84 2032 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2033 }
2034 }
46eb8f98 2035 if (has_msr_hv_runtime) {
9c600a84 2036 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2037 }
866eea9a
AS		 2038 if (cpu->hyperv_synic) {
2039 uint32_t msr;
2040
9c600a84
EH		 2041 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2042 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2043 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2044 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2045 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2046 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2047 }
2048 }
ff99aa64
AS		 2049 if (has_msr_hv_stimer) {
2050 uint32_t msr;
2051
2052 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2053 msr++) {
9c600a84 2054 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2055 }
2056 }
d1ae67f6 2057 if (has_msr_mtrr) {
9c600a84
EH		 2058 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2059 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2060 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2061 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2062 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2063 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2064 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2065 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2066 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2067 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2068 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2069 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2070 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2071 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2072 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2073 }
2074 }
5ef68987 2075
d71b62a1 2076 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2077 if (ret < 0) {
05330448 2078 return ret;
b9bec74b 2079 }
05330448 2080
9c600a84 2081 assert(ret == cpu->kvm_msr_buf->nmsrs);
05330448 2082 for (i = 0; i < ret; i++) {
0d894367
PB		 2083 uint32_t index = msrs[i].index;
2084 switch (index) {
05330448
AL		 2085 case MSR_IA32_SYSENTER_CS:
2086 env->sysenter_cs = msrs[i].data;
2087 break;
2088 case MSR_IA32_SYSENTER_ESP:
2089 env->sysenter_esp = msrs[i].data;
2090 break;
2091 case MSR_IA32_SYSENTER_EIP:
2092 env->sysenter_eip = msrs[i].data;
2093 break;
0c03266a
JK		 2094 case MSR_PAT:
2095 env->pat = msrs[i].data;
2096 break;
05330448
AL		 2097 case MSR_STAR:
2098 env->star = msrs[i].data;
2099 break;
2100#ifdef TARGET_X86_64
2101 case MSR_CSTAR:
2102 env->cstar = msrs[i].data;
2103 break;
2104 case MSR_KERNELGSBASE:
2105 env->kernelgsbase = msrs[i].data;
2106 break;
2107 case MSR_FMASK:
2108 env->fmask = msrs[i].data;
2109 break;
2110 case MSR_LSTAR:
2111 env->lstar = msrs[i].data;
2112 break;
2113#endif
2114 case MSR_IA32_TSC:
2115 env->tsc = msrs[i].data;
2116 break;
c9b8f6b6
AS		 2117 case MSR_TSC_AUX:
2118 env->tsc_aux = msrs[i].data;
2119 break;
f28558d3
WA		 2120 case MSR_TSC_ADJUST:
2121 env->tsc_adjust = msrs[i].data;
2122 break;
aa82ba54
LJ		 2123 case MSR_IA32_TSCDEADLINE:
2124 env->tsc_deadline = msrs[i].data;
2125 break;
aa851e36
MT		 2126 case MSR_VM_HSAVE_PA:
2127 env->vm_hsave = msrs[i].data;
2128 break;
1a03675d
GC		 2129 case MSR_KVM_SYSTEM_TIME:
2130 env->system_time_msr = msrs[i].data;
2131 break;
2132 case MSR_KVM_WALL_CLOCK:
2133 env->wall_clock_msr = msrs[i].data;
2134 break;
57780495
MT		 2135 case MSR_MCG_STATUS:
2136 env->mcg_status = msrs[i].data;
2137 break;
2138 case MSR_MCG_CTL:
2139 env->mcg_ctl = msrs[i].data;
2140 break;
21e87c46
AK		 2141 case MSR_IA32_MISC_ENABLE:
2142 env->msr_ia32_misc_enable = msrs[i].data;
2143 break;
fc12d72e
PB		 2144 case MSR_IA32_SMBASE:
2145 env->smbase = msrs[i].data;
2146 break;
0779caeb
ACL		 2147 case MSR_IA32_FEATURE_CONTROL:
2148 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2149 break;
79e9ebeb
LJ		 2150 case MSR_IA32_BNDCFGS:
2151 env->msr_bndcfgs = msrs[i].data;
2152 break;
18cd2c17
WL		 2153 case MSR_IA32_XSS:
2154 env->xss = msrs[i].data;
2155 break;
57780495 2156 default:
57780495
MT		 2157 if (msrs[i].index >= MSR_MC0_CTL &&
2158 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2159 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2160 }
d8da8574 2161 break;
f6584ee2
GN		 2162 case MSR_KVM_ASYNC_PF_EN:
2163 env->async_pf_en_msr = msrs[i].data;
2164 break;
bc9a839d
MT		 2165 case MSR_KVM_PV_EOI_EN:
2166 env->pv_eoi_en_msr = msrs[i].data;
2167 break;
917367aa
MT		 2168 case MSR_KVM_STEAL_TIME:
2169 env->steal_time_msr = msrs[i].data;
2170 break;
0d894367
PB		 2171 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2172 env->msr_fixed_ctr_ctrl = msrs[i].data;
2173 break;
2174 case MSR_CORE_PERF_GLOBAL_CTRL:
2175 env->msr_global_ctrl = msrs[i].data;
2176 break;
2177 case MSR_CORE_PERF_GLOBAL_STATUS:
2178 env->msr_global_status = msrs[i].data;
2179 break;
2180 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2181 env->msr_global_ovf_ctrl = msrs[i].data;
2182 break;
2183 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2184 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2185 break;
2186 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2187 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2188 break;
2189 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2190 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2191 break;
1c90ef26
VR		 2192 case HV_X64_MSR_HYPERCALL:
2193 env->msr_hv_hypercall = msrs[i].data;
2194 break;
2195 case HV_X64_MSR_GUEST_OS_ID:
2196 env->msr_hv_guest_os_id = msrs[i].data;
2197 break;
5ef68987
VR		 2198 case HV_X64_MSR_APIC_ASSIST_PAGE:
2199 env->msr_hv_vapic = msrs[i].data;
2200 break;
48a5f3bc
VR		 2201 case HV_X64_MSR_REFERENCE_TSC:
2202 env->msr_hv_tsc = msrs[i].data;
2203 break;
f2a53c9e
AS		 2204 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2205 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2206 break;
46eb8f98
AS		 2207 case HV_X64_MSR_VP_RUNTIME:
2208 env->msr_hv_runtime = msrs[i].data;
2209 break;
866eea9a
AS		 2210 case HV_X64_MSR_SCONTROL:
2211 env->msr_hv_synic_control = msrs[i].data;
2212 break;
2213 case HV_X64_MSR_SVERSION:
2214 env->msr_hv_synic_version = msrs[i].data;
2215 break;
2216 case HV_X64_MSR_SIEFP:
2217 env->msr_hv_synic_evt_page = msrs[i].data;
2218 break;
2219 case HV_X64_MSR_SIMP:
2220 env->msr_hv_synic_msg_page = msrs[i].data;
2221 break;
2222 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2223 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2224 break;
2225 case HV_X64_MSR_STIMER0_CONFIG:
2226 case HV_X64_MSR_STIMER1_CONFIG:
2227 case HV_X64_MSR_STIMER2_CONFIG:
2228 case HV_X64_MSR_STIMER3_CONFIG:
2229 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2230 msrs[i].data;
2231 break;
2232 case HV_X64_MSR_STIMER0_COUNT:
2233 case HV_X64_MSR_STIMER1_COUNT:
2234 case HV_X64_MSR_STIMER2_COUNT:
2235 case HV_X64_MSR_STIMER3_COUNT:
2236 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2237 msrs[i].data;
866eea9a 2238 break;
d1ae67f6
AW		 2239 case MSR_MTRRdefType:
2240 env->mtrr_deftype = msrs[i].data;
2241 break;
2242 case MSR_MTRRfix64K_00000:
2243 env->mtrr_fixed[0] = msrs[i].data;
2244 break;
2245 case MSR_MTRRfix16K_80000:
2246 env->mtrr_fixed[1] = msrs[i].data;
2247 break;
2248 case MSR_MTRRfix16K_A0000:
2249 env->mtrr_fixed[2] = msrs[i].data;
2250 break;
2251 case MSR_MTRRfix4K_C0000:
2252 env->mtrr_fixed[3] = msrs[i].data;
2253 break;
2254 case MSR_MTRRfix4K_C8000:
2255 env->mtrr_fixed[4] = msrs[i].data;
2256 break;
2257 case MSR_MTRRfix4K_D0000:
2258 env->mtrr_fixed[5] = msrs[i].data;
2259 break;
2260 case MSR_MTRRfix4K_D8000:
2261 env->mtrr_fixed[6] = msrs[i].data;
2262 break;
2263 case MSR_MTRRfix4K_E0000:
2264 env->mtrr_fixed[7] = msrs[i].data;
2265 break;
2266 case MSR_MTRRfix4K_E8000:
2267 env->mtrr_fixed[8] = msrs[i].data;
2268 break;
2269 case MSR_MTRRfix4K_F0000:
2270 env->mtrr_fixed[9] = msrs[i].data;
2271 break;
2272 case MSR_MTRRfix4K_F8000:
2273 env->mtrr_fixed[10] = msrs[i].data;
2274 break;
2275 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2276 if (index & 1) {
2277 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2278 } else {
2279 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2280 }
2281 break;
05330448
AL		 2282 }
2283 }
2284
2285 return 0;
2286}
2287
1bc22652 2288static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2289{
1bc22652 2290 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2291
1bc22652 2292 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2293}
2294
23d02d9b 2295static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2296{
259186a7 2297 CPUState *cs = CPU(cpu);
23d02d9b 2298 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2299 struct kvm_mp_state mp_state;
2300 int ret;
2301
259186a7 2302 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2303 if (ret < 0) {
2304 return ret;
2305 }
2306 env->mp_state = mp_state.mp_state;
c14750e8 2307 if (kvm_irqchip_in_kernel()) {
259186a7 2308 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2309 }
9bdbe550
HB		 2310 return 0;
2311}
2312
1bc22652 2313static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2314{
02e51483 2315 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2316 struct kvm_lapic_state kapic;
2317 int ret;
2318
3d4b2649 2319 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2320 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2321 if (ret < 0) {
2322 return ret;
2323 }
2324
2325 kvm_get_apic_state(apic, &kapic);
2326 }
2327 return 0;
2328}
2329
1bc22652 2330static int kvm_put_apic(X86CPU *cpu)
680c1c6f 2331{
02e51483 2332 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2333 struct kvm_lapic_state kapic;
2334
3d4b2649 2335 if (apic && kvm_irqchip_in_kernel()) {
680c1c6f
JK		 2336 kvm_put_apic_state(apic, &kapic);
2337
1bc22652 2338 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
680c1c6f
JK		 2339 }
2340 return 0;
2341}
2342
1bc22652 2343static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2344{
fc12d72e 2345 CPUState *cs = CPU(cpu);
1bc22652 2346 CPUX86State *env = &cpu->env;
076796f8 2347 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2348
2349 if (!kvm_has_vcpu_events()) {
2350 return 0;
2351 }
2352
31827373
JK		 2353 events.exception.injected = (env->exception_injected >= 0);
2354 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2355 events.exception.has_error_code = env->has_error_code;
2356 events.exception.error_code = env->error_code;
7e680753 2357 events.exception.pad = 0;
a0fb002c
JK		 2358
2359 events.interrupt.injected = (env->interrupt_injected >= 0);
2360 events.interrupt.nr = env->interrupt_injected;
2361 events.interrupt.soft = env->soft_interrupt;
2362
2363 events.nmi.injected = env->nmi_injected;
2364 events.nmi.pending = env->nmi_pending;
2365 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2366 events.nmi.pad = 0;
a0fb002c
JK		 2367
2368 events.sipi_vector = env->sipi_vector;
2369
fc12d72e
PB		 2370 if (has_msr_smbase) {
2371 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2372 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2373 if (kvm_irqchip_in_kernel()) {
2374 /* As soon as these are moved to the kernel, remove them
2375 * from cs->interrupt_request.
2376 */
2377 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2378 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2379 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2380 } else {
2381 /* Keep these in cs->interrupt_request. */
2382 events.smi.pending = 0;
2383 events.smi.latched_init = 0;
2384 }
2385 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2386 }
2387
ea643051
JK		 2388 events.flags = 0;
2389 if (level >= KVM_PUT_RESET_STATE) {
2390 events.flags |=
2391 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2392 }
aee028b9 2393
1bc22652 2394 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2395}
2396
1bc22652 2397static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2398{
1bc22652 2399 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2400 struct kvm_vcpu_events events;
2401 int ret;
2402
2403 if (!kvm_has_vcpu_events()) {
2404 return 0;
2405 }
2406
fc12d72e 2407 memset(&events, 0, sizeof(events));
1bc22652 2408 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2409 if (ret < 0) {
2410 return ret;
2411 }
31827373 2412 env->exception_injected =
a0fb002c
JK		 2413 events.exception.injected ? events.exception.nr : -1;
2414 env->has_error_code = events.exception.has_error_code;
2415 env->error_code = events.exception.error_code;
2416
2417 env->interrupt_injected =
2418 events.interrupt.injected ? events.interrupt.nr : -1;
2419 env->soft_interrupt = events.interrupt.soft;
2420
2421 env->nmi_injected = events.nmi.injected;
2422 env->nmi_pending = events.nmi.pending;
2423 if (events.nmi.masked) {
2424 env->hflags2 |= HF2_NMI_MASK;
2425 } else {
2426 env->hflags2 &= ~HF2_NMI_MASK;
2427 }
2428
fc12d72e
PB		 2429 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2430 if (events.smi.smm) {
2431 env->hflags |= HF_SMM_MASK;
2432 } else {
2433 env->hflags &= ~HF_SMM_MASK;
2434 }
2435 if (events.smi.pending) {
2436 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2437 } else {
2438 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2439 }
2440 if (events.smi.smm_inside_nmi) {
2441 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2442 } else {
2443 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2444 }
2445 if (events.smi.latched_init) {
2446 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2447 } else {
2448 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2449 }
2450 }
2451
a0fb002c 2452 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2453
2454 return 0;
2455}
2456
1bc22652 2457static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2458{
ed2803da 2459 CPUState *cs = CPU(cpu);
1bc22652 2460 CPUX86State *env = &cpu->env;
b0b1d690 2461 int ret = 0;
b0b1d690
JK		 2462 unsigned long reinject_trap = 0;
2463
2464 if (!kvm_has_vcpu_events()) {
2465 if (env->exception_injected == 1) {
2466 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2467 } else if (env->exception_injected == 3) {
2468 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2469 }
2470 env->exception_injected = -1;
2471 }
2472
2473 /*
2474 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2475 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2476 * by updating the debug state once again if single-stepping is on.
2477 * Another reason to call kvm_update_guest_debug here is a pending debug
2478 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2479 * reinject them via SET_GUEST_DEBUG.
2480 */
2481 if (reinject_trap ||
ed2803da 2482 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2483 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2484 }
b0b1d690
JK		 2485 return ret;
2486}
2487
1bc22652 2488static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2489{
1bc22652 2490 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2491 struct kvm_debugregs dbgregs;
2492 int i;
2493
2494 if (!kvm_has_debugregs()) {
2495 return 0;
2496 }
2497
2498 for (i = 0; i < 4; i++) {
2499 dbgregs.db[i] = env->dr[i];
2500 }
2501 dbgregs.dr6 = env->dr[6];
2502 dbgregs.dr7 = env->dr[7];
2503 dbgregs.flags = 0;
2504
1bc22652 2505 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2506}
2507
1bc22652 2508static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2509{
1bc22652 2510 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2511 struct kvm_debugregs dbgregs;
2512 int i, ret;
2513
2514 if (!kvm_has_debugregs()) {
2515 return 0;
2516 }
2517
1bc22652 2518 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2519 if (ret < 0) {
b9bec74b 2520 return ret;
ff44f1a3
JK		 2521 }
2522 for (i = 0; i < 4; i++) {
2523 env->dr[i] = dbgregs.db[i];
2524 }
2525 env->dr[4] = env->dr[6] = dbgregs.dr6;
2526 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2527
2528 return 0;
2529}
2530
20d695a9 2531int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2532{
20d695a9 2533 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2534 int ret;
2535
2fa45344 2536 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2537
48e1a45c 2538 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2539 ret = kvm_put_msr_feature_control(x86_cpu);
2540 if (ret < 0) {
2541 return ret;
2542 }
2543 }
2544
36f96c4b
HZ		 2545 if (level == KVM_PUT_FULL_STATE) {
2546 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2547 * because TSC frequency mismatch shouldn't abort migration,
2548 * unless the user explicitly asked for a more strict TSC
2549 * setting (e.g. using an explicit "tsc-freq" option).
2550 */
2551 kvm_arch_set_tsc_khz(cpu);
2552 }
2553
1bc22652 2554 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2555 if (ret < 0) {
05330448 2556 return ret;
b9bec74b 2557 }
1bc22652 2558 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2559 if (ret < 0) {
f1665b21 2560 return ret;
b9bec74b 2561 }
1bc22652 2562 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2563 if (ret < 0) {
05330448 2564 return ret;
b9bec74b 2565 }
1bc22652 2566 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2567 if (ret < 0) {
05330448 2568 return ret;
b9bec74b 2569 }
ab443475 2570 /* must be before kvm_put_msrs */
1bc22652 2571 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2572 if (ret < 0) {
2573 return ret;
2574 }
1bc22652 2575 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2576 if (ret < 0) {
05330448 2577 return ret;
b9bec74b 2578 }
ea643051 2579 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2580 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2581 if (ret < 0) {
ea643051 2582 return ret;
b9bec74b 2583 }
1bc22652 2584 ret = kvm_put_apic(x86_cpu);
680c1c6f
JK		 2585 if (ret < 0) {
2586 return ret;
2587 }
ea643051 2588 }
7477cd38
MT		 2589
2590 ret = kvm_put_tscdeadline_msr(x86_cpu);
2591 if (ret < 0) {
2592 return ret;
2593 }
2594
1bc22652 2595 ret = kvm_put_vcpu_events(x86_cpu, level);
b9bec74b 2596 if (ret < 0) {
a0fb002c 2597 return ret;
b9bec74b 2598 }
1bc22652 2599 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2600 if (ret < 0) {
b0b1d690 2601 return ret;
b9bec74b 2602 }
b0b1d690 2603 /* must be last */
1bc22652 2604 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2605 if (ret < 0) {
ff44f1a3 2606 return ret;
b9bec74b 2607 }
05330448
AL		 2608 return 0;
2609}
2610
20d695a9 2611int kvm_arch_get_registers(CPUState *cs)
05330448 2612{
20d695a9 2613 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2614 int ret;
2615
20d695a9 2616 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2617
1bc22652 2618 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2619 if (ret < 0) {
f4f1110e 2620 goto out;
b9bec74b 2621 }
1bc22652 2622 ret = kvm_get_xsave(cpu);
b9bec74b 2623 if (ret < 0) {
f4f1110e 2624 goto out;
b9bec74b 2625 }
1bc22652 2626 ret = kvm_get_xcrs(cpu);
b9bec74b 2627 if (ret < 0) {
f4f1110e 2628 goto out;
b9bec74b 2629 }
1bc22652 2630 ret = kvm_get_sregs(cpu);
b9bec74b 2631 if (ret < 0) {
f4f1110e 2632 goto out;
b9bec74b 2633 }
1bc22652 2634 ret = kvm_get_msrs(cpu);
b9bec74b 2635 if (ret < 0) {
f4f1110e 2636 goto out;
b9bec74b 2637 }
23d02d9b 2638 ret = kvm_get_mp_state(cpu);
b9bec74b 2639 if (ret < 0) {
f4f1110e 2640 goto out;
b9bec74b 2641 }
1bc22652 2642 ret = kvm_get_apic(cpu);
680c1c6f 2643 if (ret < 0) {
f4f1110e 2644 goto out;
680c1c6f 2645 }
1bc22652 2646 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2647 if (ret < 0) {
f4f1110e 2648 goto out;
b9bec74b 2649 }
1bc22652 2650 ret = kvm_get_debugregs(cpu);
b9bec74b 2651 if (ret < 0) {
f4f1110e 2652 goto out;
b9bec74b 2653 }
f4f1110e
RH		 2654 ret = 0;
2655 out:
2656 cpu_sync_bndcs_hflags(&cpu->env);
2657 return ret;
05330448
AL		 2658}
2659
20d695a9 2660void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2661{
20d695a9
AF		 2662 X86CPU *x86_cpu = X86_CPU(cpu);
2663 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2664 int ret;
2665
276ce815 2666 /* Inject NMI */
fc12d72e
PB		 2667 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2668 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2669 qemu_mutex_lock_iothread();
2670 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2671 qemu_mutex_unlock_iothread();
2672 DPRINTF("injected NMI\n");
2673 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2674 if (ret < 0) {
2675 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2676 strerror(-ret));
2677 }
2678 }
2679 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2680 qemu_mutex_lock_iothread();
2681 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2682 qemu_mutex_unlock_iothread();
2683 DPRINTF("injected SMI\n");
2684 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2685 if (ret < 0) {
2686 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2687 strerror(-ret));
2688 }
ce377af3 2689 }
276ce815
LJ		 2690 }
2691
15eafc2e 2692 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2693 qemu_mutex_lock_iothread();
2694 }
2695
e0723c45
PB		 2696 /* Force the VCPU out of its inner loop to process any INIT requests
2697 * or (for userspace APIC, but it is cheap to combine the checks here)
2698 * pending TPR access reports.
2699 */
2700 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2701 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2702 !(env->hflags & HF_SMM_MASK)) {
2703 cpu->exit_request = 1;
2704 }
2705 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2706 cpu->exit_request = 1;
2707 }
e0723c45 2708 }
05330448 2709
15eafc2e 2710 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2711 /* Try to inject an interrupt if the guest can accept it */
2712 if (run->ready_for_interrupt_injection &&
259186a7 2713 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2714 (env->eflags & IF_MASK)) {
2715 int irq;
2716
259186a7 2717 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2718 irq = cpu_get_pic_interrupt(env);
2719 if (irq >= 0) {
2720 struct kvm_interrupt intr;
2721
2722 intr.irq = irq;
db1669bc 2723 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2724 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2725 if (ret < 0) {
2726 fprintf(stderr,
2727 "KVM: injection failed, interrupt lost (%s)\n",
2728 strerror(-ret));
2729 }
db1669bc
JK		 2730 }
2731 }
05330448 2732
db1669bc
JK		 2733 /* If we have an interrupt but the guest is not ready to receive an
2734 * interrupt, request an interrupt window exit. This will
2735 * cause a return to userspace as soon as the guest is ready to
2736 * receive interrupts. */
259186a7 2737 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2738 run->request_interrupt_window = 1;
2739 } else {
2740 run->request_interrupt_window = 0;
2741 }
2742
2743 DPRINTF("setting tpr\n");
02e51483 2744 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2745
2746 qemu_mutex_unlock_iothread();
db1669bc 2747 }
05330448
AL		 2748}
2749
4c663752 2750MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2751{
20d695a9
AF		 2752 X86CPU *x86_cpu = X86_CPU(cpu);
2753 CPUX86State *env = &x86_cpu->env;
2754
fc12d72e
PB		 2755 if (run->flags & KVM_RUN_X86_SMM) {
2756 env->hflags |= HF_SMM_MASK;
2757 } else {
2758 env->hflags &= HF_SMM_MASK;
2759 }
b9bec74b 2760 if (run->if_flag) {
05330448 2761 env->eflags |= IF_MASK;
b9bec74b 2762 } else {
05330448 2763 env->eflags &= ~IF_MASK;
b9bec74b 2764 }
4b8523ee
JK		 2765
2766 /* We need to protect the apic state against concurrent accesses from
2767 * different threads in case the userspace irqchip is used. */
2768 if (!kvm_irqchip_in_kernel()) {
2769 qemu_mutex_lock_iothread();
2770 }
02e51483
CF		 2771 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2772 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2773 if (!kvm_irqchip_in_kernel()) {
2774 qemu_mutex_unlock_iothread();
2775 }
f794aa4a 2776 return cpu_get_mem_attrs(env);
05330448
AL		 2777}
2778
20d695a9 2779int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2780{
20d695a9
AF		 2781 X86CPU *cpu = X86_CPU(cs);
2782 CPUX86State *env = &cpu->env;
232fc23b 2783
259186a7 2784 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2785 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2786 assert(env->mcg_cap);
2787
259186a7 2788 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2789
dd1750d7 2790 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2791
2792 if (env->exception_injected == EXCP08_DBLE) {
2793 /* this means triple fault */
2794 qemu_system_reset_request();
fcd7d003 2795 cs->exit_request = 1;
ab443475
JK		 2796 return 0;
2797 }
2798 env->exception_injected = EXCP12_MCHK;
2799 env->has_error_code = 0;
2800
259186a7 2801 cs->halted = 0;
ab443475
JK		 2802 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2803 env->mp_state = KVM_MP_STATE_RUNNABLE;
2804 }
2805 }
2806
fc12d72e
PB		 2807 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2808 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2809 kvm_cpu_synchronize_state(cs);
2810 do_cpu_init(cpu);
2811 }
2812
db1669bc
JK		 2813 if (kvm_irqchip_in_kernel()) {
2814 return 0;
2815 }
2816
259186a7
AF		 2817 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2818 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2819 apic_poll_irq(cpu->apic_state);
5d62c43a 2820 }
259186a7 2821 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2822 (env->eflags & IF_MASK)) ||
259186a7
AF		 2823 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2824 cs->halted = 0;
6792a57b 2825 }
259186a7 2826 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2827 kvm_cpu_synchronize_state(cs);
232fc23b 2828 do_cpu_sipi(cpu);
0af691d7 2829 }
259186a7
AF		 2830 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2831 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2832 kvm_cpu_synchronize_state(cs);
02e51483 2833 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2834 env->tpr_access_type);
2835 }
0af691d7 2836
259186a7 2837 return cs->halted;
0af691d7
MT		 2838}
2839
839b5630 2840static int kvm_handle_halt(X86CPU *cpu)
05330448 2841{
259186a7 2842 CPUState *cs = CPU(cpu);
839b5630
AF		 2843 CPUX86State *env = &cpu->env;
2844
259186a7 2845 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2846 (env->eflags & IF_MASK)) &&
259186a7
AF		 2847 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2848 cs->halted = 1;
bb4ea393 2849 return EXCP_HLT;
05330448
AL		 2850 }
2851
bb4ea393 2852 return 0;
05330448
AL		 2853}
2854
f7575c96 2855static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2856{
f7575c96
AF		 2857 CPUState *cs = CPU(cpu);
2858 struct kvm_run *run = cs->kvm_run;
d362e757 2859
02e51483 2860 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2861 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2862 : TPR_ACCESS_READ);
2863 return 1;
2864}
2865
f17ec444 2866int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2867{
38972938 2868 static const uint8_t int3 = 0xcc;
64bf3f4e 2869
f17ec444
AF		 2870 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2871 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2872 return -EINVAL;
b9bec74b 2873 }
e22a25c9
AL		 2874 return 0;
2875}
2876
f17ec444 2877int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2878{
2879 uint8_t int3;
2880
f17ec444
AF		 2881 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2882 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2883 return -EINVAL;
b9bec74b 2884 }
e22a25c9
AL		 2885 return 0;
2886}
2887
2888static struct {
2889 target_ulong addr;
2890 int len;
2891 int type;
2892} hw_breakpoint[4];
2893
2894static int nb_hw_breakpoint;
2895
2896static int find_hw_breakpoint(target_ulong addr, int len, int type)
2897{
2898 int n;
2899
b9bec74b 2900 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2901 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2902 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2903 return n;
b9bec74b
JK		 2904 }
2905 }
e22a25c9
AL		 2906 return -1;
2907}
2908
2909int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2910 target_ulong len, int type)
2911{
2912 switch (type) {
2913 case GDB_BREAKPOINT_HW:
2914 len = 1;
2915 break;
2916 case GDB_WATCHPOINT_WRITE:
2917 case GDB_WATCHPOINT_ACCESS:
2918 switch (len) {
2919 case 1:
2920 break;
2921 case 2:
2922 case 4:
2923 case 8:
b9bec74b 2924 if (addr & (len - 1)) {
e22a25c9 2925 return -EINVAL;
b9bec74b 2926 }
e22a25c9
AL		 2927 break;
2928 default:
2929 return -EINVAL;
2930 }
2931 break;
2932 default:
2933 return -ENOSYS;
2934 }
2935
b9bec74b 2936 if (nb_hw_breakpoint == 4) {
e22a25c9 2937 return -ENOBUFS;
b9bec74b
JK		 2938 }
2939 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2940 return -EEXIST;
b9bec74b 2941 }
e22a25c9
AL		 2942 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2943 hw_breakpoint[nb_hw_breakpoint].len = len;
2944 hw_breakpoint[nb_hw_breakpoint].type = type;
2945 nb_hw_breakpoint++;
2946
2947 return 0;
2948}
2949
2950int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2951 target_ulong len, int type)
2952{
2953 int n;
2954
2955 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2956 if (n < 0) {
e22a25c9 2957 return -ENOENT;
b9bec74b 2958 }
e22a25c9
AL		 2959 nb_hw_breakpoint--;
2960 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2961
2962 return 0;
2963}
2964
2965void kvm_arch_remove_all_hw_breakpoints(void)
2966{
2967 nb_hw_breakpoint = 0;
2968}
2969
2970static CPUWatchpoint hw_watchpoint;
2971
a60f24b5 2972static int kvm_handle_debug(X86CPU *cpu,
48405526 2973 struct kvm_debug_exit_arch *arch_info)
e22a25c9 2974{
ed2803da 2975 CPUState *cs = CPU(cpu);
a60f24b5 2976 CPUX86State *env = &cpu->env;
f2574737 2977 int ret = 0;
e22a25c9
AL		 2978 int n;
2979
2980 if (arch_info->exception == 1) {
2981 if (arch_info->dr6 & (1 << 14)) {
ed2803da 2982 if (cs->singlestep_enabled) {
f2574737 2983 ret = EXCP_DEBUG;
b9bec74b 2984 }
e22a25c9 2985 } else {
b9bec74b
JK		 2986 for (n = 0; n < 4; n++) {
2987 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 2988 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2989 case 0x0:
f2574737 2990 ret = EXCP_DEBUG;
e22a25c9
AL		 2991 break;
2992 case 0x1:
f2574737 2993 ret = EXCP_DEBUG;
ff4700b0 2994 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 2995 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2996 hw_watchpoint.flags = BP_MEM_WRITE;
2997 break;
2998 case 0x3:
f2574737 2999 ret = EXCP_DEBUG;
ff4700b0 3000 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3001 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3002 hw_watchpoint.flags = BP_MEM_ACCESS;
3003 break;
3004 }
b9bec74b
JK		 3005 }
3006 }
e22a25c9 3007 }
ff4700b0 3008 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3009 ret = EXCP_DEBUG;
b9bec74b 3010 }
f2574737 3011 if (ret == 0) {
ff4700b0 3012 cpu_synchronize_state(cs);
48405526 3013 assert(env->exception_injected == -1);
b0b1d690 3014
f2574737 3015 /* pass to guest */
48405526
BS		 3016 env->exception_injected = arch_info->exception;
3017 env->has_error_code = 0;
b0b1d690 3018 }
e22a25c9 3019
f2574737 3020 return ret;
e22a25c9
AL		 3021}
3022
20d695a9 3023void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3024{
3025 const uint8_t type_code[] = {
3026 [GDB_BREAKPOINT_HW] = 0x0,
3027 [GDB_WATCHPOINT_WRITE] = 0x1,
3028 [GDB_WATCHPOINT_ACCESS] = 0x3
3029 };
3030 const uint8_t len_code[] = {
3031 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3032 };
3033 int n;
3034
a60f24b5 3035 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3036 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3037 }
e22a25c9
AL		 3038 if (nb_hw_breakpoint > 0) {
3039 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3040 dbg->arch.debugreg[7] = 0x0600;
3041 for (n = 0; n < nb_hw_breakpoint; n++) {
3042 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3043 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3044 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3045 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3046 }
3047 }
3048}
4513d923 3049
2a4dac83
JK		 3050static bool host_supports_vmx(void)
3051{
3052 uint32_t ecx, unused;
3053
3054 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3055 return ecx & CPUID_EXT_VMX;
3056}
3057
3058#define VMX_INVALID_GUEST_STATE 0x80000021
3059
20d695a9 3060int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3061{
20d695a9 3062 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3063 uint64_t code;
3064 int ret;
3065
3066 switch (run->exit_reason) {
3067 case KVM_EXIT_HLT:
3068 DPRINTF("handle_hlt\n");
4b8523ee 3069 qemu_mutex_lock_iothread();
839b5630 3070 ret = kvm_handle_halt(cpu);
4b8523ee 3071 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3072 break;
3073 case KVM_EXIT_SET_TPR:
3074 ret = 0;
3075 break;
d362e757 3076 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3077 qemu_mutex_lock_iothread();
f7575c96 3078 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3079 qemu_mutex_unlock_iothread();
d362e757 3080 break;
2a4dac83
JK		 3081 case KVM_EXIT_FAIL_ENTRY:
3082 code = run->fail_entry.hardware_entry_failure_reason;
3083 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3084 code);
3085 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3086 fprintf(stderr,
12619721 3087 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3088 "unrestricted mode\n"
3089 "support, the failure can be most likely due to the guest "
3090 "entering an invalid\n"
3091 "state for Intel VT. For example, the guest maybe running "
3092 "in big real mode\n"
3093 "which is not supported on less recent Intel processors."
3094 "\n\n");
3095 }
3096 ret = -1;
3097 break;
3098 case KVM_EXIT_EXCEPTION:
3099 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3100 run->ex.exception, run->ex.error_code);
3101 ret = -1;
3102 break;
f2574737
JK		 3103 case KVM_EXIT_DEBUG:
3104 DPRINTF("kvm_exit_debug\n");
4b8523ee 3105 qemu_mutex_lock_iothread();
a60f24b5 3106 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3107 qemu_mutex_unlock_iothread();
f2574737 3108 break;
50efe82c
AS		 3109 case KVM_EXIT_HYPERV:
3110 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3111 break;
15eafc2e
PB		 3112 case KVM_EXIT_IOAPIC_EOI:
3113 ioapic_eoi_broadcast(run->eoi.vector);
3114 ret = 0;
3115 break;
2a4dac83
JK		 3116 default:
3117 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3118 ret = -1;
3119 break;
3120 }
3121
3122 return ret;
3123}
3124
20d695a9 3125bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3126{
20d695a9
AF		 3127 X86CPU *cpu = X86_CPU(cs);
3128 CPUX86State *env = &cpu->env;
3129
dd1750d7 3130 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3131 return !(env->cr[0] & CR0_PE_MASK) ||
3132 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3133}
84b058d7
JK		 3134
3135void kvm_arch_init_irq_routing(KVMState *s)
3136{
3137 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3138 /* If kernel can't do irq routing, interrupt source
3139 * override 0->2 cannot be set up as required by HPET.
3140 * So we have to disable it.
3141 */
3142 no_hpet = 1;
3143 }
cc7e0ddf 3144 /* We know at this point that we're using the in-kernel
614e41bc 3145 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3146 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3147 */
614e41bc 3148 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3149 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3150
3151 if (kvm_irqchip_is_split()) {
3152 int i;
3153
3154 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3155 MSI routes for signaling interrupts to the local apics. */
3156 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3157 struct MSIMessage msg = { 0x0, 0x0 };
3158 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3159 error_report("Could not enable split IRQ mode.");
3160 exit(1);
3161 }
3162 }
3163 }
3164}
3165
3166int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3167{
3168 int ret;
3169 if (machine_kernel_irqchip_split(ms)) {
3170 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3171 if (ret) {
3172 error_report("Could not enable split irqchip mode: %s\n",
3173 strerror(-ret));
3174 exit(1);
3175 } else {
3176 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3177 kvm_split_irqchip = true;
3178 return 1;
3179 }
3180 } else {
3181 return 0;
3182 }
84b058d7 3183}
b139bd30
JK		 3184
3185/* Classic KVM device assignment interface. Will remain x86 only. */
3186int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3187 uint32_t flags, uint32_t *dev_id)
3188{
3189 struct kvm_assigned_pci_dev dev_data = {
3190 .segnr = dev_addr->domain,
3191 .busnr = dev_addr->bus,
3192 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3193 .flags = flags,
3194 };
3195 int ret;
3196
3197 dev_data.assigned_dev_id =
3198 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3199
3200 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3201 if (ret < 0) {
3202 return ret;
3203 }
3204
3205 *dev_id = dev_data.assigned_dev_id;
3206
3207 return 0;
3208}
3209
3210int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3211{
3212 struct kvm_assigned_pci_dev dev_data = {
3213 .assigned_dev_id = dev_id,
3214 };
3215
3216 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3217}
3218
3219static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3220 uint32_t irq_type, uint32_t guest_irq)
3221{
3222 struct kvm_assigned_irq assigned_irq = {
3223 .assigned_dev_id = dev_id,
3224 .guest_irq = guest_irq,
3225 .flags = irq_type,
3226 };
3227
3228 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3229 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3230 } else {
3231 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3232 }
3233}
3234
3235int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3236 uint32_t guest_irq)
3237{
3238 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3239 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3240
3241 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3242}
3243
3244int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3245{
3246 struct kvm_assigned_pci_dev dev_data = {
3247 .assigned_dev_id = dev_id,
3248 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3249 };
3250
3251 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3252}
3253
3254static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3255 uint32_t type)
3256{
3257 struct kvm_assigned_irq assigned_irq = {
3258 .assigned_dev_id = dev_id,
3259 .flags = type,
3260 };
3261
3262 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3263}
3264
3265int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3266{
3267 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3268 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3269}
3270
3271int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3272{
3273 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3274 KVM_DEV_IRQ_GUEST_MSI, virq);
3275}
3276
3277int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3278{
3279 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3280 KVM_DEV_IRQ_HOST_MSI);
3281}
3282
3283bool kvm_device_msix_supported(KVMState *s)
3284{
3285 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3286 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3287 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3288}
3289
3290int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3291 uint32_t nr_vectors)
3292{
3293 struct kvm_assigned_msix_nr msix_nr = {
3294 .assigned_dev_id = dev_id,
3295 .entry_nr = nr_vectors,
3296 };
3297
3298 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3299}
3300
3301int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3302 int virq)
3303{
3304 struct kvm_assigned_msix_entry msix_entry = {
3305 .assigned_dev_id = dev_id,
3306 .gsi = virq,
3307 .entry = vector,
3308 };
3309
3310 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3311}
3312
3313int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3314{
3315 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3316 KVM_DEV_IRQ_GUEST_MSIX, 0);
3317}
3318
3319int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3320{
3321 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3322 KVM_DEV_IRQ_HOST_MSIX);
3323}
9e03a040
FB		 3324
3325int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3326 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 3327{
3328 return 0;
3329}
1850b6b7
EA		 3330
3331int kvm_arch_msi_data_to_gsi(uint32_t data)
3332{
3333 abort();
3334}
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