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target/arm: Move GTimer definitions to new 'gtimer.h' header
[mirror_qemu.git] / hw / arm / allwinner-h3.c
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qemu/units.h"
25 #include "hw/qdev-core.h"
26 #include "hw/sysbus.h"
27 #include "hw/char/serial.h"
28 #include "hw/misc/unimp.h"
29 #include "hw/usb/hcd-ehci.h"
30 #include "hw/loader.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/arm/allwinner-h3.h"
33 #include "target/arm/cpu-qom.h"
34 #include "target/arm/gtimer.h"
35
36 /* Memory map */
37 const hwaddr allwinner_h3_memmap[] = {
38 [AW_H3_DEV_SRAM_A1] = 0x00000000,
39 [AW_H3_DEV_SRAM_A2] = 0x00044000,
40 [AW_H3_DEV_SRAM_C] = 0x00010000,
41 [AW_H3_DEV_SYSCTRL] = 0x01c00000,
42 [AW_H3_DEV_MMC0] = 0x01c0f000,
43 [AW_H3_DEV_SID] = 0x01c14000,
44 [AW_H3_DEV_EHCI0] = 0x01c1a000,
45 [AW_H3_DEV_OHCI0] = 0x01c1a400,
46 [AW_H3_DEV_EHCI1] = 0x01c1b000,
47 [AW_H3_DEV_OHCI1] = 0x01c1b400,
48 [AW_H3_DEV_EHCI2] = 0x01c1c000,
49 [AW_H3_DEV_OHCI2] = 0x01c1c400,
50 [AW_H3_DEV_EHCI3] = 0x01c1d000,
51 [AW_H3_DEV_OHCI3] = 0x01c1d400,
52 [AW_H3_DEV_CCU] = 0x01c20000,
53 [AW_H3_DEV_PIT] = 0x01c20c00,
54 [AW_H3_DEV_WDT] = 0x01c20ca0,
55 [AW_H3_DEV_UART0] = 0x01c28000,
56 [AW_H3_DEV_UART1] = 0x01c28400,
57 [AW_H3_DEV_UART2] = 0x01c28800,
58 [AW_H3_DEV_UART3] = 0x01c28c00,
59 [AW_H3_DEV_TWI0] = 0x01c2ac00,
60 [AW_H3_DEV_TWI1] = 0x01c2b000,
61 [AW_H3_DEV_TWI2] = 0x01c2b400,
62 [AW_H3_DEV_EMAC] = 0x01c30000,
63 [AW_H3_DEV_DRAMCOM] = 0x01c62000,
64 [AW_H3_DEV_DRAMCTL] = 0x01c63000,
65 [AW_H3_DEV_DRAMPHY] = 0x01c65000,
66 [AW_H3_DEV_GIC_DIST] = 0x01c81000,
67 [AW_H3_DEV_GIC_CPU] = 0x01c82000,
68 [AW_H3_DEV_GIC_HYP] = 0x01c84000,
69 [AW_H3_DEV_GIC_VCPU] = 0x01c86000,
70 [AW_H3_DEV_RTC] = 0x01f00000,
71 [AW_H3_DEV_CPUCFG] = 0x01f01c00,
72 [AW_H3_DEV_R_TWI] = 0x01f02400,
73 [AW_H3_DEV_SDRAM] = 0x40000000
74 };
75
76 /* List of unimplemented devices */
77 struct AwH3Unimplemented {
78 const char *device_name;
79 hwaddr base;
80 hwaddr size;
81 } unimplemented[] = {
82 { "d-engine", 0x01000000, 4 * MiB },
83 { "d-inter", 0x01400000, 128 * KiB },
84 { "dma", 0x01c02000, 4 * KiB },
85 { "nfdc", 0x01c03000, 4 * KiB },
86 { "ts", 0x01c06000, 4 * KiB },
87 { "keymem", 0x01c0b000, 4 * KiB },
88 { "lcd0", 0x01c0c000, 4 * KiB },
89 { "lcd1", 0x01c0d000, 4 * KiB },
90 { "ve", 0x01c0e000, 4 * KiB },
91 { "mmc1", 0x01c10000, 4 * KiB },
92 { "mmc2", 0x01c11000, 4 * KiB },
93 { "crypto", 0x01c15000, 4 * KiB },
94 { "msgbox", 0x01c17000, 4 * KiB },
95 { "spinlock", 0x01c18000, 4 * KiB },
96 { "usb0-otg", 0x01c19000, 4 * KiB },
97 { "usb0-phy", 0x01c1a000, 4 * KiB },
98 { "usb1-phy", 0x01c1b000, 4 * KiB },
99 { "usb2-phy", 0x01c1c000, 4 * KiB },
100 { "usb3-phy", 0x01c1d000, 4 * KiB },
101 { "smc", 0x01c1e000, 4 * KiB },
102 { "pio", 0x01c20800, 1 * KiB },
103 { "owa", 0x01c21000, 1 * KiB },
104 { "pwm", 0x01c21400, 1 * KiB },
105 { "keyadc", 0x01c21800, 1 * KiB },
106 { "pcm0", 0x01c22000, 1 * KiB },
107 { "pcm1", 0x01c22400, 1 * KiB },
108 { "pcm2", 0x01c22800, 1 * KiB },
109 { "audio", 0x01c22c00, 2 * KiB },
110 { "smta", 0x01c23400, 1 * KiB },
111 { "ths", 0x01c25000, 1 * KiB },
112 { "uart0", 0x01c28000, 1 * KiB },
113 { "uart1", 0x01c28400, 1 * KiB },
114 { "uart2", 0x01c28800, 1 * KiB },
115 { "uart3", 0x01c28c00, 1 * KiB },
116 { "scr", 0x01c2c400, 1 * KiB },
117 { "gpu", 0x01c40000, 64 * KiB },
118 { "hstmr", 0x01c60000, 4 * KiB },
119 { "spi0", 0x01c68000, 4 * KiB },
120 { "spi1", 0x01c69000, 4 * KiB },
121 { "csi", 0x01cb0000, 320 * KiB },
122 { "tve", 0x01e00000, 64 * KiB },
123 { "hdmi", 0x01ee0000, 128 * KiB },
124 { "r_timer", 0x01f00800, 1 * KiB },
125 { "r_intc", 0x01f00c00, 1 * KiB },
126 { "r_wdog", 0x01f01000, 1 * KiB },
127 { "r_prcm", 0x01f01400, 1 * KiB },
128 { "r_twd", 0x01f01800, 1 * KiB },
129 { "r_cir-rx", 0x01f02000, 1 * KiB },
130 { "r_uart", 0x01f02800, 1 * KiB },
131 { "r_pio", 0x01f02c00, 1 * KiB },
132 { "r_pwm", 0x01f03800, 1 * KiB },
133 { "core-dbg", 0x3f500000, 128 * KiB },
134 { "tsgen-ro", 0x3f506000, 4 * KiB },
135 { "tsgen-ctl", 0x3f507000, 4 * KiB },
136 { "ddr-mem", 0x40000000, 2 * GiB },
137 { "n-brom", 0xffff0000, 32 * KiB },
138 { "s-brom", 0xffff0000, 64 * KiB }
139 };
140
141 /* Per Processor Interrupts */
142 enum {
143 AW_H3_GIC_PPI_MAINT = 9,
144 AW_H3_GIC_PPI_HYPTIMER = 10,
145 AW_H3_GIC_PPI_VIRTTIMER = 11,
146 AW_H3_GIC_PPI_SECTIMER = 13,
147 AW_H3_GIC_PPI_PHYSTIMER = 14
148 };
149
150 /* Shared Processor Interrupts */
151 enum {
152 AW_H3_GIC_SPI_UART0 = 0,
153 AW_H3_GIC_SPI_UART1 = 1,
154 AW_H3_GIC_SPI_UART2 = 2,
155 AW_H3_GIC_SPI_UART3 = 3,
156 AW_H3_GIC_SPI_TWI0 = 6,
157 AW_H3_GIC_SPI_TWI1 = 7,
158 AW_H3_GIC_SPI_TWI2 = 8,
159 AW_H3_GIC_SPI_TIMER0 = 18,
160 AW_H3_GIC_SPI_TIMER1 = 19,
161 AW_H3_GIC_SPI_R_TWI = 44,
162 AW_H3_GIC_SPI_MMC0 = 60,
163 AW_H3_GIC_SPI_EHCI0 = 72,
164 AW_H3_GIC_SPI_OHCI0 = 73,
165 AW_H3_GIC_SPI_EHCI1 = 74,
166 AW_H3_GIC_SPI_OHCI1 = 75,
167 AW_H3_GIC_SPI_EHCI2 = 76,
168 AW_H3_GIC_SPI_OHCI2 = 77,
169 AW_H3_GIC_SPI_EHCI3 = 78,
170 AW_H3_GIC_SPI_OHCI3 = 79,
171 AW_H3_GIC_SPI_EMAC = 82
172 };
173
174 /* Allwinner H3 general constants */
175 enum {
176 AW_H3_GIC_NUM_SPI = 128
177 };
178
179 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
180 {
181 const int64_t rom_size = 32 * KiB;
182 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
183
184 if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
185 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
186 __func__);
187 return;
188 }
189
190 rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
191 rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
192 NULL, NULL, NULL, NULL, false);
193 }
194
195 static void allwinner_h3_init(Object *obj)
196 {
197 AwH3State *s = AW_H3(obj);
198
199 s->memmap = allwinner_h3_memmap;
200
201 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
202 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
203 ARM_CPU_TYPE_NAME("cortex-a7"));
204 }
205
206 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
207
208 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
209 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
210 "clk0-freq");
211 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
212 "clk1-freq");
213
214 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
215
216 object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
217
218 object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
219
220 object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
221 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
222 "identifier");
223
224 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
225
226 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
227
228 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
229 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
230 "ram-addr");
231 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
232 "ram-size");
233
234 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
235
236 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
237 object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);
238 object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);
239 object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
240
241 object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN6I);
242 }
243
244 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
245 {
246 AwH3State *s = AW_H3(dev);
247 unsigned i;
248
249 /* CPUs */
250 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
251
252 /*
253 * Disable secondary CPUs. Guest EL3 firmware will start
254 * them via CPU reset control registers.
255 */
256 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
257 i > 0);
258
259 /* All exception levels required */
260 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
261 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
262
263 /* Mark realized */
264 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
265 }
266
267 /* Generic Interrupt Controller */
268 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
269 GIC_INTERNAL);
270 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
271 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
273 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
274 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
275
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
280
281 /*
282 * Wire the outputs from each CPU's generic timer and the GICv3
283 * maintenance interrupt signal to the appropriate GIC PPI inputs,
284 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
285 */
286 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
287 DeviceState *cpudev = DEVICE(&s->cpus[i]);
288 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
289 int irq;
290 /*
291 * Mapping from the output timer irq lines from the CPU to the
292 * GIC PPI inputs used for this board.
293 */
294 const int timer_irq[] = {
295 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
296 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
297 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
298 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
299 };
300
301 /* Connect CPU timer outputs to GIC PPI inputs */
302 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
303 qdev_connect_gpio_out(cpudev, irq,
304 qdev_get_gpio_in(DEVICE(&s->gic),
305 ppibase + timer_irq[irq]));
306 }
307
308 /* Connect GIC outputs to CPU interrupt inputs */
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
310 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
311 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
312 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
314 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
316 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
317
318 /* GIC maintenance signal */
319 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
320 qdev_get_gpio_in(DEVICE(&s->gic),
321 ppibase + AW_H3_GIC_PPI_MAINT));
322 }
323
324 /* Timer */
325 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
326 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
328 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
329 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
330 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
331
332 /* SRAM */
333 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
334 64 * KiB, &error_abort);
335 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
336 32 * KiB, &error_abort);
337 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
338 44 * KiB, &error_abort);
339 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
340 &s->sram_a1);
341 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
342 &s->sram_a2);
343 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
344 &s->sram_c);
345
346 /* Clock Control Unit */
347 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
349
350 /* System Control */
351 sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
352 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
353
354 /* CPU Configuration */
355 sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
357
358 /* Security Identifier */
359 sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
361
362 /* SD/MMC */
363 object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
364 OBJECT(get_system_memory()), &error_fatal);
365 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
366 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
367 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
368 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
369
370 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
371 "sd-bus");
372
373 /* EMAC */
374 /* FIXME use qdev NIC properties instead of nd_table[] */
375 if (nd_table[0].used) {
376 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
377 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
378 }
379 object_property_set_link(OBJECT(&s->emac), "dma-memory",
380 OBJECT(get_system_memory()), &error_fatal);
381 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
383 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
384 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
385
386 /* Universal Serial Bus */
387 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
388 qdev_get_gpio_in(DEVICE(&s->gic),
389 AW_H3_GIC_SPI_EHCI0));
390 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
391 qdev_get_gpio_in(DEVICE(&s->gic),
392 AW_H3_GIC_SPI_EHCI1));
393 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
394 qdev_get_gpio_in(DEVICE(&s->gic),
395 AW_H3_GIC_SPI_EHCI2));
396 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
397 qdev_get_gpio_in(DEVICE(&s->gic),
398 AW_H3_GIC_SPI_EHCI3));
399
400 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
401 qdev_get_gpio_in(DEVICE(&s->gic),
402 AW_H3_GIC_SPI_OHCI0));
403 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
404 qdev_get_gpio_in(DEVICE(&s->gic),
405 AW_H3_GIC_SPI_OHCI1));
406 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
407 qdev_get_gpio_in(DEVICE(&s->gic),
408 AW_H3_GIC_SPI_OHCI2));
409 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
410 qdev_get_gpio_in(DEVICE(&s->gic),
411 AW_H3_GIC_SPI_OHCI3));
412
413 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
414 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
415 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
416 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
417 /* UART1 */
418 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
419 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
420 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
421 /* UART2 */
422 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
423 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
424 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
425 /* UART3 */
426 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
427 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
428 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
429
430 /* DRAMC */
431 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
432 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
435
436 /* RTC */
437 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
438 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
439
440 /* I2C */
441 sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
442 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
443 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
444 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
445
446 sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
447 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
449 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
450
451 sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
452 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
453 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
454 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
455
456 sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
457 sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
458 sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
459 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
460
461 /* WDT */
462 sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
463 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
464 s->memmap[AW_H3_DEV_WDT], 1);
465
466 /* Unimplemented devices */
467 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
468 create_unimplemented_device(unimplemented[i].device_name,
469 unimplemented[i].base,
470 unimplemented[i].size);
471 }
472 }
473
474 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
475 {
476 DeviceClass *dc = DEVICE_CLASS(oc);
477
478 dc->realize = allwinner_h3_realize;
479 /* Reason: uses serial_hd() in realize function */
480 dc->user_creatable = false;
481 }
482
483 static const TypeInfo allwinner_h3_type_info = {
484 .name = TYPE_AW_H3,
485 .parent = TYPE_DEVICE,
486 .instance_size = sizeof(AwH3State),
487 .instance_init = allwinner_h3_init,
488 .class_init = allwinner_h3_class_init,
489 };
490
491 static void allwinner_h3_register_types(void)
492 {
493 type_register_static(&allwinner_h3_type_info);
494 }
495
496 type_init(allwinner_h3_register_types)
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